linux/drivers/gpu/drm/nouveau/include/nvif/cl5070.h
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   1/* SPDX-License-Identifier: MIT */
   2#ifndef __NVIF_CL5070_H__
   3#define __NVIF_CL5070_H__
   4
   5#define NV50_DISP_MTHD                                                     0x00
   6
   7struct nv50_disp_mthd_v0 {
   8        __u8  version;
   9#define NV50_DISP_SCANOUTPOS                                               0x00
  10        __u8  method;
  11        __u8  head;
  12        __u8  pad03[5];
  13};
  14
  15struct nv50_disp_scanoutpos_v0 {
  16        __u8  version;
  17        __u8  pad01[7];
  18        __s64 time[2];
  19        __u16 vblanks;
  20        __u16 vblanke;
  21        __u16 vtotal;
  22        __u16 vline;
  23        __u16 hblanks;
  24        __u16 hblanke;
  25        __u16 htotal;
  26        __u16 hline;
  27};
  28
  29struct nv50_disp_mthd_v1 {
  30        __u8  version;
  31#define NV50_DISP_MTHD_V1_ACQUIRE                                          0x01
  32#define NV50_DISP_MTHD_V1_RELEASE                                          0x02
  33#define NV50_DISP_MTHD_V1_DAC_LOAD                                         0x11
  34#define NV50_DISP_MTHD_V1_SOR_HDA_ELD                                      0x21
  35#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR                                     0x22
  36#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT                                  0x23
  37#define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK                                  0x25
  38#define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI                                  0x26
  39        __u8  method;
  40        __u16 hasht;
  41        __u16 hashm;
  42        __u8  pad06[2];
  43};
  44
  45struct nv50_disp_acquire_v0 {
  46        __u8  version;
  47        __u8  or;
  48        __u8  link;
  49        __u8  pad03[5];
  50};
  51
  52struct nv50_disp_dac_load_v0 {
  53        __u8  version;
  54        __u8  load;
  55        __u8  pad02[2];
  56        __u32 data;
  57};
  58
  59struct nv50_disp_sor_hda_eld_v0 {
  60        __u8  version;
  61        __u8  pad01[7];
  62        __u8  data[];
  63};
  64
  65struct nv50_disp_sor_hdmi_pwr_v0 {
  66        __u8  version;
  67        __u8  state;
  68        __u8  max_ac_packet;
  69        __u8  rekey;
  70        __u8  avi_infoframe_length;
  71        __u8  vendor_infoframe_length;
  72#define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE (1 << 0)
  73#define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 (1 << 1)
  74        __u8  scdc;
  75        __u8  pad07[1];
  76};
  77
  78struct nv50_disp_sor_lvds_script_v0 {
  79        __u8  version;
  80        __u8  pad01[1];
  81        __u16 script;
  82        __u8  pad04[4];
  83};
  84
  85struct nv50_disp_sor_dp_mst_link_v0 {
  86        __u8  version;
  87        __u8  state;
  88        __u8  pad02[6];
  89};
  90
  91struct nv50_disp_sor_dp_mst_vcpi_v0 {
  92        __u8  version;
  93        __u8  pad01[1];
  94        __u8  start_slot;
  95        __u8  num_slots;
  96        __u16 pbn;
  97        __u16 aligned_pbn;
  98};
  99#endif
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