1/* SPDX-License-Identifier: MIT */ 2#ifndef __NVKM_DISP_DP_H__ 3#define __NVKM_DISP_DP_H__ 4#define nvkm_dp(p) container_of((p), struct nvkm_dp, outp) 5#include "outp.h" 6 7#include <core/notify.h> 8#include <subdev/bios.h> 9#include <subdev/bios/dp.h> 10 11struct nvkm_dp { 12 union { 13 struct nvkm_outp base; 14 struct nvkm_outp outp; 15 }; 16 17 struct nvbios_dpout info; 18 u8 version; 19 20 struct nvkm_i2c_aux *aux; 21 22 struct nvkm_notify hpd; 23 bool present; 24 u8 dpcd[16]; 25 26 struct mutex mutex; 27 struct { 28 atomic_t done; 29 bool mst; 30 } lt; 31}; 32 33int nvkm_dp_new(struct nvkm_disp *, int index, struct dcb_output *, 34 struct nvkm_outp **); 35void nvkm_dp_disable(struct nvkm_outp *, struct nvkm_ior *); 36 37/* DPCD Receiver Capabilities */ 38#define DPCD_RC00_DPCD_REV 0x00000 39#define DPCD_RC01_MAX_LINK_RATE 0x00001 40#define DPCD_RC02 0x00002 41#define DPCD_RC02_ENHANCED_FRAME_CAP 0x80 42#define DPCD_RC02_TPS3_SUPPORTED 0x40 43#define DPCD_RC02_MAX_LANE_COUNT 0x1f 44#define DPCD_RC03 0x00003 45#define DPCD_RC03_MAX_DOWNSPREAD 0x01 46#define DPCD_RC0E_AUX_RD_INTERVAL 0x0000e 47 48/* DPCD Link Configuration */ 49#define DPCD_LC00_LINK_BW_SET 0x00100 50#define DPCD_LC01 0x00101 51#define DPCD_LC01_ENHANCED_FRAME_EN 0x80 52#define DPCD_LC01_LANE_COUNT_SET 0x1f 53#define DPCD_LC02 0x00102 54#define DPCD_LC02_TRAINING_PATTERN_SET 0x03 55#define DPCD_LC03(l) ((l) + 0x00103) 56#define DPCD_LC03_MAX_PRE_EMPHASIS_REACHED 0x20 57#define DPCD_LC03_PRE_EMPHASIS_SET 0x18 58#define DPCD_LC03_MAX_SWING_REACHED 0x04 59#define DPCD_LC03_VOLTAGE_SWING_SET 0x03 60#define DPCD_LC0F 0x0010f 61#define DPCD_LC0F_LANE1_MAX_POST_CURSOR2_REACHED 0x40 62#define DPCD_LC0F_LANE1_POST_CURSOR2_SET 0x30 63#define DPCD_LC0F_LANE0_MAX_POST_CURSOR2_REACHED 0x04 64#define DPCD_LC0F_LANE0_POST_CURSOR2_SET 0x03 65#define DPCD_LC10 0x00110 66#define DPCD_LC10_LANE3_MAX_POST_CURSOR2_REACHED 0x40 67#define DPCD_LC10_LANE3_POST_CURSOR2_SET 0x30 68#define DPCD_LC10_LANE2_MAX_POST_CURSOR2_REACHED 0x04 69#define DPCD_LC10_LANE2_POST_CURSOR2_SET 0x03 70 71/* DPCD Link/Sink Status */ 72#define DPCD_LS02 0x00202 73#define DPCD_LS02_LANE1_SYMBOL_LOCKED 0x40 74#define DPCD_LS02_LANE1_CHANNEL_EQ_DONE 0x20 75#define DPCD_LS02_LANE1_CR_DONE 0x10 76#define DPCD_LS02_LANE0_SYMBOL_LOCKED 0x04 77#define DPCD_LS02_LANE0_CHANNEL_EQ_DONE 0x02 78#define DPCD_LS02_LANE0_CR_DONE 0x01 79#define DPCD_LS03 0x00203 80#define DPCD_LS03_LANE3_SYMBOL_LOCKED 0x40 81#define DPCD_LS03_LANE3_CHANNEL_EQ_DONE 0x20 82#define DPCD_LS03_LANE3_CR_DONE 0x10 83#define DPCD_LS03_LANE2_SYMBOL_LOCKED 0x04 84#define DPCD_LS03_LANE2_CHANNEL_EQ_DONE 0x02 85#define DPCD_LS03_LANE2_CR_DONE 0x01 86#define DPCD_LS04 0x00204 87#define DPCD_LS04_LINK_STATUS_UPDATED 0x80 88#define DPCD_LS04_DOWNSTREAM_PORT_STATUS_CHANGED 0x40 89#define DPCD_LS04_INTERLANE_ALIGN_DONE 0x01 90#define DPCD_LS06 0x00206 91#define DPCD_LS06_LANE1_PRE_EMPHASIS 0xc0 92#define DPCD_LS06_LANE1_VOLTAGE_SWING 0x30 93#define DPCD_LS06_LANE0_PRE_EMPHASIS 0x0c 94#define DPCD_LS06_LANE0_VOLTAGE_SWING 0x03 95#define DPCD_LS07 0x00207 96#define DPCD_LS07_LANE3_PRE_EMPHASIS 0xc0 97#define DPCD_LS07_LANE3_VOLTAGE_SWING 0x30 98#define DPCD_LS07_LANE2_PRE_EMPHASIS 0x0c 99#define DPCD_LS07_LANE2_VOLTAGE_SWING 0x03 100#define DPCD_LS0C 0x0020c 101#define DPCD_LS0C_LANE3_POST_CURSOR2 0xc0 102#define DPCD_LS0C_LANE2_POST_CURSOR2 0x30 103#define DPCD_LS0C_LANE1_POST_CURSOR2 0x0c 104#define DPCD_LS0C_LANE0_POST_CURSOR2 0x03 105 106/* DPCD Sink Control */ 107#define DPCD_SC00 0x00600 108#define DPCD_SC00_SET_POWER 0x03 109#define DPCD_SC00_SET_POWER_D0 0x01 110#define DPCD_SC00_SET_POWER_D3 0x03 111#endif 112