LXR linux/drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.c

   1/*
   2 * Copyright 2015 Red Hat Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Ben Skeggs
  23 */
  24#define gf119_pmu_code gk110_pmu_code
  25#define gf119_pmu_data gk110_pmu_data
  26#include "priv.h"
  27#include "fuc/gf119.fuc4.h"
  28
  29#include <subdev/timer.h>
  30
  31void
  32gk110_pmu_pgob(struct nvkm_pmu *pmu, bool enable)
  33{
  34        struct nvkm_device *device = pmu->subdev.device;
  35        static const struct {
  36                u32 addr;
  37                u32 data;
  38        } magic[] = {
  39                { 0x020520, 0xfffffffc },
  40                { 0x020524, 0xfffffffe },
  41                { 0x020524, 0xfffffffc },
  42                { 0x020524, 0xfffffff8 },
  43                { 0x020524, 0xffffffe0 },
  44                { 0x020530, 0xfffffffe },
  45                { 0x02052c, 0xfffffffa },
  46                { 0x02052c, 0xfffffff0 },
  47                { 0x02052c, 0xffffffc0 },
  48                { 0x02052c, 0xffffff00 },
  49                { 0x02052c, 0xfffffc00 },
  50                { 0x02052c, 0xfffcfc00 },
  51                { 0x02052c, 0xfff0fc00 },
  52                { 0x02052c, 0xff80fc00 },
  53                { 0x020528, 0xfffffffe },
  54                { 0x020528, 0xfffffffc },
  55        };
  56        int i;
  57
  58        nvkm_mask(device, 0x000200, 0x00001000, 0x00000000);
  59        nvkm_rd32(device, 0x000200);
  60        nvkm_mask(device, 0x000200, 0x08000000, 0x08000000);
  61        msleep(50);
  62
  63        nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000002);
  64        nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
  65        nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
  66
  67        nvkm_mask(device, 0x0206b4, 0x00000000, 0x00000000);
  68        for (i = 0; i < ARRAY_SIZE(magic); i++) {
  69                nvkm_wr32(device, magic[i].addr, magic[i].data);
  70                nvkm_msec(device, 2000,
  71                        if (!(nvkm_rd32(device, magic[i].addr) & 0x80000000))
  72                                break;
  73                );
  74        }
  75
  76        nvkm_mask(device, 0x10a78c, 0x00000002, 0x00000000);
  77        nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000001);
  78        nvkm_mask(device, 0x10a78c, 0x00000001, 0x00000000);
  79
  80        nvkm_mask(device, 0x000200, 0x08000000, 0x00000000);
  81        nvkm_mask(device, 0x000200, 0x00001000, 0x00001000);
  82        nvkm_rd32(device, 0x000200);
  83}
  84
  85static const struct nvkm_pmu_func
  86gk110_pmu = {
  87        .flcn = &gt215_pmu_flcn,
  88        .code.data = gk110_pmu_code,
  89        .code.size = sizeof(gk110_pmu_code),
  90        .data.data = gk110_pmu_data,
  91        .data.size = sizeof(gk110_pmu_data),
  92        .enabled = gf100_pmu_enabled,
  93        .reset = gf100_pmu_reset,
  94        .init = gt215_pmu_init,
  95        .fini = gt215_pmu_fini,
  96        .intr = gt215_pmu_intr,
  97        .send = gt215_pmu_send,
  98        .recv = gt215_pmu_recv,
  99        .pgob = gk110_pmu_pgob,
 100};
 101
 102static const struct nvkm_pmu_fwif
 103gk110_pmu_fwif[] = {
 104        { -1, gf100_pmu_nofw, &gk110_pmu },
 105        {}
 106};
 107
 108int
 109gk110_pmu_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 110              struct nvkm_pmu **ppmu)
 111{
 112        return nvkm_pmu_new_(gk110_pmu_fwif, device, type, inst, ppmu);
 113}
 114