LXR linux/drivers/gpu/drm/radeon/radeon

   1/*
   2 * Copyright 2008 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 * Copyright 2009 Jerome Glisse.
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a
   7 * copy of this software and associated documentation files (the "Software"),
   8 * to deal in the Software without restriction, including without limitation
   9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10 * and/or sell copies of the Software, and to permit persons to whom the
  11 * Software is furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22 * OTHER DEALINGS IN THE SOFTWARE.
  23 *
  24 * Authors: Dave Airlie
  25 *          Alex Deucher
  26 *          Jerome Glisse
  27 */
  28#ifndef __RADEON_ASIC_H__
  29#define __RADEON_ASIC_H__
  30
  31/*
  32 * common functions
  33 */
  34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
  35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
  37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
  38
  39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
  40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
  41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
  42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
  43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
  44
  45void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  46u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
  47void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
  48u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
  49
  50/*
  51 * r100,rv100,rs100,rv200,rs200
  52 */
  53struct r100_mc_save {
  54        u32     GENMO_WT;
  55        u32     CRTC_EXT_CNTL;
  56        u32     CRTC_GEN_CNTL;
  57        u32     CRTC2_GEN_CNTL;
  58        u32     CUR_OFFSET;
  59        u32     CUR2_OFFSET;
  60};
  61int r100_init(struct radeon_device *rdev);
  62void r100_fini(struct radeon_device *rdev);
  63int r100_suspend(struct radeon_device *rdev);
  64int r100_resume(struct radeon_device *rdev);
  65void r100_vga_set_state(struct radeon_device *rdev, bool state);
  66bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
  67int r100_asic_reset(struct radeon_device *rdev, bool hard);
  68u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
  69void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
  70uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags);
  71void r100_pci_gart_set_page(struct radeon_device *rdev, unsigned i,
  72                            uint64_t entry);
  73void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
  74int r100_irq_set(struct radeon_device *rdev);
  75int r100_irq_process(struct radeon_device *rdev);
  76void r100_fence_ring_emit(struct radeon_device *rdev,
  77                          struct radeon_fence *fence);
  78bool r100_semaphore_ring_emit(struct radeon_device *rdev,
  79                              struct radeon_ring *cp,
  80                              struct radeon_semaphore *semaphore,
  81                              bool emit_wait);
  82int r100_cs_parse(struct radeon_cs_parser *p);
  83void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
  84uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
  85struct radeon_fence *r100_copy_blit(struct radeon_device *rdev,
  86                                    uint64_t src_offset,
  87                                    uint64_t dst_offset,
  88                                    unsigned num_gpu_pages,
  89                                    struct dma_resv *resv);
  90int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  91                         uint32_t tiling_flags, uint32_t pitch,
  92                         uint32_t offset, uint32_t obj_size);
  93void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
  94void r100_bandwidth_update(struct radeon_device *rdev);
  95void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
  96int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
  97void r100_hpd_init(struct radeon_device *rdev);
  98void r100_hpd_fini(struct radeon_device *rdev);
  99bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 100void r100_hpd_set_polarity(struct radeon_device *rdev,
 101                           enum radeon_hpd_id hpd);
 102void r100_debugfs_rbbm_init(struct radeon_device *rdev);
 103void r100_debugfs_cp_init(struct radeon_device *rdev);
 104void r100_cp_disable(struct radeon_device *rdev);
 105int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
 106void r100_cp_fini(struct radeon_device *rdev);
 107int r100_pci_gart_init(struct radeon_device *rdev);
 108void r100_pci_gart_fini(struct radeon_device *rdev);
 109int r100_pci_gart_enable(struct radeon_device *rdev);
 110void r100_pci_gart_disable(struct radeon_device *rdev);
 111void  r100_debugfs_mc_info_init(struct radeon_device *rdev);
 112int r100_gui_wait_for_idle(struct radeon_device *rdev);
 113int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 114void r100_irq_disable(struct radeon_device *rdev);
 115void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
 116void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
 117void r100_vram_init_sizes(struct radeon_device *rdev);
 118int r100_cp_reset(struct radeon_device *rdev);
 119void r100_vga_render_disable(struct radeon_device *rdev);
 120void r100_restore_sanity(struct radeon_device *rdev);
 121int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
 122                                         struct radeon_cs_packet *pkt,
 123                                         struct radeon_bo *robj);
 124int r100_cs_parse_packet0(struct radeon_cs_parser *p,
 125                          struct radeon_cs_packet *pkt,
 126                          const unsigned *auth, unsigned n,
 127                          radeon_packet0_check_t check);
 128int r100_cs_packet_parse(struct radeon_cs_parser *p,
 129                         struct radeon_cs_packet *pkt,
 130                         unsigned idx);
 131void r100_enable_bm(struct radeon_device *rdev);
 132void r100_set_common_regs(struct radeon_device *rdev);
 133void r100_bm_disable(struct radeon_device *rdev);
 134extern bool r100_gui_idle(struct radeon_device *rdev);
 135extern void r100_pm_misc(struct radeon_device *rdev);
 136extern void r100_pm_prepare(struct radeon_device *rdev);
 137extern void r100_pm_finish(struct radeon_device *rdev);
 138extern void r100_pm_init_profile(struct radeon_device *rdev);
 139extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
 140extern void r100_page_flip(struct radeon_device *rdev, int crtc,
 141                           u64 crtc_base, bool async);
 142extern bool r100_page_flip_pending(struct radeon_device *rdev, int crtc);
 143extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
 144extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
 145
 146u32 r100_gfx_get_rptr(struct radeon_device *rdev,
 147                      struct radeon_ring *ring);
 148u32 r100_gfx_get_wptr(struct radeon_device *rdev,
 149                      struct radeon_ring *ring);
 150void r100_gfx_set_wptr(struct radeon_device *rdev,
 151                       struct radeon_ring *ring);
 152
 153/*
 154 * r200,rv250,rs300,rv280
 155 */
 156struct radeon_fence *r200_copy_dma(struct radeon_device *rdev,
 157                                   uint64_t src_offset,
 158                                   uint64_t dst_offset,
 159                                   unsigned num_gpu_pages,
 160                                   struct dma_resv *resv);
 161void r200_set_safe_registers(struct radeon_device *rdev);
 162
 163/*
 164 * r300,r350,rv350,rv380
 165 */
 166extern int r300_init(struct radeon_device *rdev);
 167extern void r300_fini(struct radeon_device *rdev);
 168extern int r300_suspend(struct radeon_device *rdev);
 169extern int r300_resume(struct radeon_device *rdev);
 170extern int r300_asic_reset(struct radeon_device *rdev, bool hard);
 171extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 172extern void r300_fence_ring_emit(struct radeon_device *rdev,
 173                                struct radeon_fence *fence);
 174extern int r300_cs_parse(struct radeon_cs_parser *p);
 175extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
 176extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags);
 177extern void rv370_pcie_gart_set_page(struct radeon_device *rdev, unsigned i,
 178                                     uint64_t entry);
 179extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 180extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
 181extern void r300_set_reg_safe(struct radeon_device *rdev);
 182extern void r300_mc_program(struct radeon_device *rdev);
 183extern void r300_mc_init(struct radeon_device *rdev);
 184extern void r300_clock_startup(struct radeon_device *rdev);
 185extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
 186extern int rv370_pcie_gart_init(struct radeon_device *rdev);
 187extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
 188extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
 189extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
 190
 191/*
 192 * r420,r423,rv410
 193 */
 194extern int r420_init(struct radeon_device *rdev);
 195extern void r420_fini(struct radeon_device *rdev);
 196extern int r420_suspend(struct radeon_device *rdev);
 197extern int r420_resume(struct radeon_device *rdev);
 198extern void r420_pm_init_profile(struct radeon_device *rdev);
 199extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
 200extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
 201extern void r420_debugfs_pipes_info_init(struct radeon_device *rdev);
 202extern void r420_pipes_init(struct radeon_device *rdev);
 203
 204/*
 205 * rs400,rs480
 206 */
 207extern int rs400_init(struct radeon_device *rdev);
 208extern void rs400_fini(struct radeon_device *rdev);
 209extern int rs400_suspend(struct radeon_device *rdev);
 210extern int rs400_resume(struct radeon_device *rdev);
 211void rs400_gart_tlb_flush(struct radeon_device *rdev);
 212uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags);
 213void rs400_gart_set_page(struct radeon_device *rdev, unsigned i,
 214                         uint64_t entry);
 215uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 216void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 217int rs400_gart_init(struct radeon_device *rdev);
 218int rs400_gart_enable(struct radeon_device *rdev);
 219void rs400_gart_adjust_size(struct radeon_device *rdev);
 220void rs400_gart_disable(struct radeon_device *rdev);
 221void rs400_gart_fini(struct radeon_device *rdev);
 222extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
 223
 224/*
 225 * rs600.
 226 */
 227extern int rs600_asic_reset(struct radeon_device *rdev, bool hard);
 228extern int rs600_init(struct radeon_device *rdev);
 229extern void rs600_fini(struct radeon_device *rdev);
 230extern int rs600_suspend(struct radeon_device *rdev);
 231extern int rs600_resume(struct radeon_device *rdev);
 232int rs600_irq_set(struct radeon_device *rdev);
 233int rs600_irq_process(struct radeon_device *rdev);
 234void rs600_irq_disable(struct radeon_device *rdev);
 235u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
 236void rs600_gart_tlb_flush(struct radeon_device *rdev);
 237uint64_t rs600_gart_get_page_entry(uint64_t addr, uint32_t flags);
 238void rs600_gart_set_page(struct radeon_device *rdev, unsigned i,
 239                         uint64_t entry);
 240uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 241void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 242void rs600_bandwidth_update(struct radeon_device *rdev);
 243void rs600_hpd_init(struct radeon_device *rdev);
 244void rs600_hpd_fini(struct radeon_device *rdev);
 245bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 246void rs600_hpd_set_polarity(struct radeon_device *rdev,
 247                            enum radeon_hpd_id hpd);
 248extern void rs600_pm_misc(struct radeon_device *rdev);
 249extern void rs600_pm_prepare(struct radeon_device *rdev);
 250extern void rs600_pm_finish(struct radeon_device *rdev);
 251extern void rs600_page_flip(struct radeon_device *rdev, int crtc,
 252                            u64 crtc_base, bool async);
 253extern bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc);
 254void rs600_set_safe_registers(struct radeon_device *rdev);
 255extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
 256extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
 257
 258/*
 259 * rs690,rs740
 260 */
 261int rs690_init(struct radeon_device *rdev);
 262void rs690_fini(struct radeon_device *rdev);
 263int rs690_resume(struct radeon_device *rdev);
 264int rs690_suspend(struct radeon_device *rdev);
 265uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 266void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 267void rs690_bandwidth_update(struct radeon_device *rdev);
 268void rs690_line_buffer_adjust(struct radeon_device *rdev,
 269                                        struct drm_display_mode *mode1,
 270                                        struct drm_display_mode *mode2);
 271extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
 272
 273/*
 274 * rv515
 275 */
 276struct rv515_mc_save {
 277        u32 vga_render_control;
 278        u32 vga_hdp_control;
 279        bool crtc_enabled[2];
 280};
 281
 282int rv515_init(struct radeon_device *rdev);
 283void rv515_fini(struct radeon_device *rdev);
 284uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 285void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 286void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
 287void rv515_bandwidth_update(struct radeon_device *rdev);
 288int rv515_resume(struct radeon_device *rdev);
 289int rv515_suspend(struct radeon_device *rdev);
 290void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
 291void rv515_vga_render_disable(struct radeon_device *rdev);
 292void rv515_set_safe_registers(struct radeon_device *rdev);
 293void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
 294void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
 295void rv515_clock_startup(struct radeon_device *rdev);
 296void rv515_debugfs(struct radeon_device *rdev);
 297int rv515_mc_wait_for_idle(struct radeon_device *rdev);
 298
 299/*
 300 * r520,rv530,rv560,rv570,r580
 301 */
 302int r520_init(struct radeon_device *rdev);
 303int r520_resume(struct radeon_device *rdev);
 304int r520_mc_wait_for_idle(struct radeon_device *rdev);
 305
 306/*
 307 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
 308 */
 309int r600_init(struct radeon_device *rdev);
 310void r600_fini(struct radeon_device *rdev);
 311int r600_suspend(struct radeon_device *rdev);
 312int r600_resume(struct radeon_device *rdev);
 313void r600_vga_set_state(struct radeon_device *rdev, bool state);
 314int r600_wb_init(struct radeon_device *rdev);
 315void r600_wb_fini(struct radeon_device *rdev);
 316void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
 317uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 318void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 319int r600_cs_parse(struct radeon_cs_parser *p);
 320int r600_dma_cs_parse(struct radeon_cs_parser *p);
 321void r600_fence_ring_emit(struct radeon_device *rdev,
 322                          struct radeon_fence *fence);
 323bool r600_semaphore_ring_emit(struct radeon_device *rdev,
 324                              struct radeon_ring *cp,
 325                              struct radeon_semaphore *semaphore,
 326                              bool emit_wait);
 327void r600_dma_fence_ring_emit(struct radeon_device *rdev,
 328                              struct radeon_fence *fence);
 329bool r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
 330                                  struct radeon_ring *ring,
 331                                  struct radeon_semaphore *semaphore,
 332                                  bool emit_wait);
 333void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 334bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 335bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 336int r600_asic_reset(struct radeon_device *rdev, bool hard);
 337int r600_set_surface_reg(struct radeon_device *rdev, int reg,
 338                         uint32_t tiling_flags, uint32_t pitch,
 339                         uint32_t offset, uint32_t obj_size);
 340void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
 341int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 342int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 343void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 344int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 345int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
 346struct radeon_fence *r600_copy_cpdma(struct radeon_device *rdev,
 347                                     uint64_t src_offset, uint64_t dst_offset,
 348                                     unsigned num_gpu_pages,
 349                                     struct dma_resv *resv);
 350struct radeon_fence *r600_copy_dma(struct radeon_device *rdev,
 351                                   uint64_t src_offset, uint64_t dst_offset,
 352                                   unsigned num_gpu_pages,
 353                                   struct dma_resv *resv);
 354void r600_hpd_init(struct radeon_device *rdev);
 355void r600_hpd_fini(struct radeon_device *rdev);
 356bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 357void r600_hpd_set_polarity(struct radeon_device *rdev,
 358                           enum radeon_hpd_id hpd);
 359extern void r600_mmio_hdp_flush(struct radeon_device *rdev);
 360extern bool r600_gui_idle(struct radeon_device *rdev);
 361extern void r600_pm_misc(struct radeon_device *rdev);
 362extern void r600_pm_init_profile(struct radeon_device *rdev);
 363extern void rs780_pm_init_profile(struct radeon_device *rdev);
 364extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
 365extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 366extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 367extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 368extern int r600_get_pcie_lanes(struct radeon_device *rdev);
 369bool r600_card_posted(struct radeon_device *rdev);
 370void r600_cp_stop(struct radeon_device *rdev);
 371int r600_cp_start(struct radeon_device *rdev);
 372void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
 373int r600_cp_resume(struct radeon_device *rdev);
 374void r600_cp_fini(struct radeon_device *rdev);
 375int r600_count_pipe_bits(uint32_t val);
 376int r600_mc_wait_for_idle(struct radeon_device *rdev);
 377int r600_pcie_gart_init(struct radeon_device *rdev);
 378void r600_scratch_init(struct radeon_device *rdev);
 379int r600_init_microcode(struct radeon_device *rdev);
 380u32 r600_gfx_get_rptr(struct radeon_device *rdev,
 381                      struct radeon_ring *ring);
 382u32 r600_gfx_get_wptr(struct radeon_device *rdev,
 383                      struct radeon_ring *ring);
 384void r600_gfx_set_wptr(struct radeon_device *rdev,
 385                       struct radeon_ring *ring);
 386int r600_get_allowed_info_register(struct radeon_device *rdev,
 387                                   u32 reg, u32 *val);
 388/* r600 irq */
 389int r600_irq_process(struct radeon_device *rdev);
 390int r600_irq_init(struct radeon_device *rdev);
 391void r600_irq_fini(struct radeon_device *rdev);
 392void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
 393int r600_irq_set(struct radeon_device *rdev);
 394void r600_irq_suspend(struct radeon_device *rdev);
 395void r600_disable_interrupts(struct radeon_device *rdev);
 396void r600_rlc_stop(struct radeon_device *rdev);
 397/* r600 audio */
 398void r600_audio_fini(struct radeon_device *rdev);
 399void r600_audio_set_dto(struct drm_encoder *encoder, u32 clock);
 400void r600_hdmi_update_avi_infoframe(struct drm_encoder *encoder, void *buffer,
 401                                    size_t size);
 402void r600_hdmi_update_ACR(struct drm_encoder *encoder, uint32_t clock);
 403void r600_hdmi_audio_workaround(struct drm_encoder *encoder);
 404int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
 405void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
 406u32 r600_get_xclk(struct radeon_device *rdev);
 407uint64_t r600_get_gpu_clock_counter(struct radeon_device *rdev);
 408int rv6xx_get_temp(struct radeon_device *rdev);
 409int r600_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 410int r600_dpm_pre_set_power_state(struct radeon_device *rdev);
 411void r600_dpm_post_set_power_state(struct radeon_device *rdev);
 412int r600_dpm_late_enable(struct radeon_device *rdev);
 413/* r600 dma */
 414uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
 415                           struct radeon_ring *ring);
 416uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
 417                           struct radeon_ring *ring);
 418void r600_dma_set_wptr(struct radeon_device *rdev,
 419                       struct radeon_ring *ring);
 420/* rv6xx dpm */
 421int rv6xx_dpm_init(struct radeon_device *rdev);
 422int rv6xx_dpm_enable(struct radeon_device *rdev);
 423void rv6xx_dpm_disable(struct radeon_device *rdev);
 424int rv6xx_dpm_set_power_state(struct radeon_device *rdev);
 425void rv6xx_setup_asic(struct radeon_device *rdev);
 426void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev);
 427void rv6xx_dpm_fini(struct radeon_device *rdev);
 428u32 rv6xx_dpm_get_sclk(struct radeon_device *rdev, bool low);
 429u32 rv6xx_dpm_get_mclk(struct radeon_device *rdev, bool low);
 430void rv6xx_dpm_print_power_state(struct radeon_device *rdev,
 431                                 struct radeon_ps *ps);
 432void rv6xx_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 433                                                       struct seq_file *m);
 434int rv6xx_dpm_force_performance_level(struct radeon_device *rdev,
 435                                      enum radeon_dpm_forced_level level);
 436u32 rv6xx_dpm_get_current_sclk(struct radeon_device *rdev);
 437u32 rv6xx_dpm_get_current_mclk(struct radeon_device *rdev);
 438/* rs780 dpm */
 439int rs780_dpm_init(struct radeon_device *rdev);
 440int rs780_dpm_enable(struct radeon_device *rdev);
 441void rs780_dpm_disable(struct radeon_device *rdev);
 442int rs780_dpm_set_power_state(struct radeon_device *rdev);
 443void rs780_dpm_setup_asic(struct radeon_device *rdev);
 444void rs780_dpm_display_configuration_changed(struct radeon_device *rdev);
 445void rs780_dpm_fini(struct radeon_device *rdev);
 446u32 rs780_dpm_get_sclk(struct radeon_device *rdev, bool low);
 447u32 rs780_dpm_get_mclk(struct radeon_device *rdev, bool low);
 448void rs780_dpm_print_power_state(struct radeon_device *rdev,
 449                                 struct radeon_ps *ps);
 450void rs780_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 451                                                       struct seq_file *m);
 452int rs780_dpm_force_performance_level(struct radeon_device *rdev,
 453                                      enum radeon_dpm_forced_level level);
 454u32 rs780_dpm_get_current_sclk(struct radeon_device *rdev);
 455u32 rs780_dpm_get_current_mclk(struct radeon_device *rdev);
 456
 457/*
 458 * rv770,rv730,rv710,rv740
 459 */
 460int rv770_init(struct radeon_device *rdev);
 461void rv770_fini(struct radeon_device *rdev);
 462int rv770_suspend(struct radeon_device *rdev);
 463int rv770_resume(struct radeon_device *rdev);
 464void rv770_pm_misc(struct radeon_device *rdev);
 465void rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base,
 466                     bool async);
 467bool rv770_page_flip_pending(struct radeon_device *rdev, int crtc);
 468void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 469void r700_cp_stop(struct radeon_device *rdev);
 470void r700_cp_fini(struct radeon_device *rdev);
 471struct radeon_fence *rv770_copy_dma(struct radeon_device *rdev,
 472                                    uint64_t src_offset, uint64_t dst_offset,
 473                                    unsigned num_gpu_pages,
 474                                    struct dma_resv *resv);
 475u32 rv770_get_xclk(struct radeon_device *rdev);
 476int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 477int rv770_get_temp(struct radeon_device *rdev);
 478/* rv7xx pm */
 479int rv770_dpm_init(struct radeon_device *rdev);
 480int rv770_dpm_enable(struct radeon_device *rdev);
 481int rv770_dpm_late_enable(struct radeon_device *rdev);
 482void rv770_dpm_disable(struct radeon_device *rdev);
 483int rv770_dpm_set_power_state(struct radeon_device *rdev);
 484void rv770_dpm_setup_asic(struct radeon_device *rdev);
 485void rv770_dpm_display_configuration_changed(struct radeon_device *rdev);
 486void rv770_dpm_fini(struct radeon_device *rdev);
 487u32 rv770_dpm_get_sclk(struct radeon_device *rdev, bool low);
 488u32 rv770_dpm_get_mclk(struct radeon_device *rdev, bool low);
 489void rv770_dpm_print_power_state(struct radeon_device *rdev,
 490                                 struct radeon_ps *ps);
 491void rv770_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 492                                                       struct seq_file *m);
 493int rv770_dpm_force_performance_level(struct radeon_device *rdev,
 494                                      enum radeon_dpm_forced_level level);
 495bool rv770_dpm_vblank_too_short(struct radeon_device *rdev);
 496u32 rv770_dpm_get_current_sclk(struct radeon_device *rdev);
 497u32 rv770_dpm_get_current_mclk(struct radeon_device *rdev);
 498
 499/*
 500 * evergreen
 501 */
 502struct evergreen_mc_save {
 503        u32 vga_render_control;
 504        u32 vga_hdp_control;
 505        bool crtc_enabled[RADEON_MAX_CRTCS];
 506};
 507
 508void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
 509int evergreen_init(struct radeon_device *rdev);
 510void evergreen_fini(struct radeon_device *rdev);
 511int evergreen_suspend(struct radeon_device *rdev);
 512int evergreen_resume(struct radeon_device *rdev);
 513bool evergreen_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 514bool evergreen_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 515int evergreen_asic_reset(struct radeon_device *rdev, bool hard);
 516void evergreen_bandwidth_update(struct radeon_device *rdev);
 517void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 518void evergreen_hpd_init(struct radeon_device *rdev);
 519void evergreen_hpd_fini(struct radeon_device *rdev);
 520bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
 521void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 522                                enum radeon_hpd_id hpd);
 523u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
 524int evergreen_irq_set(struct radeon_device *rdev);
 525int evergreen_irq_process(struct radeon_device *rdev);
 526extern int evergreen_cs_parse(struct radeon_cs_parser *p);
 527extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
 528extern void evergreen_pm_misc(struct radeon_device *rdev);
 529extern void evergreen_pm_prepare(struct radeon_device *rdev);
 530extern void evergreen_pm_finish(struct radeon_device *rdev);
 531extern void sumo_pm_init_profile(struct radeon_device *rdev);
 532extern void btc_pm_init_profile(struct radeon_device *rdev);
 533int sumo_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 534int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 535extern void evergreen_page_flip(struct radeon_device *rdev, int crtc,
 536                                u64 crtc_base, bool async);
 537extern bool evergreen_page_flip_pending(struct radeon_device *rdev, int crtc);
 538extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
 539void evergreen_disable_interrupt_state(struct radeon_device *rdev);
 540int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
 541void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
 542                                   struct radeon_fence *fence);
 543void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
 544                                   struct radeon_ib *ib);
 545struct radeon_fence *evergreen_copy_dma(struct radeon_device *rdev,
 546                                        uint64_t src_offset, uint64_t dst_offset,
 547                                        unsigned num_gpu_pages,
 548                                        struct dma_resv *resv);
 549int evergreen_get_temp(struct radeon_device *rdev);
 550int evergreen_get_allowed_info_register(struct radeon_device *rdev,
 551                                        u32 reg, u32 *val);
 552int sumo_get_temp(struct radeon_device *rdev);
 553int tn_get_temp(struct radeon_device *rdev);
 554int cypress_dpm_init(struct radeon_device *rdev);
 555void cypress_dpm_setup_asic(struct radeon_device *rdev);
 556int cypress_dpm_enable(struct radeon_device *rdev);
 557void cypress_dpm_disable(struct radeon_device *rdev);
 558int cypress_dpm_set_power_state(struct radeon_device *rdev);
 559void cypress_dpm_display_configuration_changed(struct radeon_device *rdev);
 560void cypress_dpm_fini(struct radeon_device *rdev);
 561bool cypress_dpm_vblank_too_short(struct radeon_device *rdev);
 562int btc_dpm_init(struct radeon_device *rdev);
 563void btc_dpm_setup_asic(struct radeon_device *rdev);
 564int btc_dpm_enable(struct radeon_device *rdev);
 565void btc_dpm_disable(struct radeon_device *rdev);
 566int btc_dpm_pre_set_power_state(struct radeon_device *rdev);
 567int btc_dpm_set_power_state(struct radeon_device *rdev);
 568void btc_dpm_post_set_power_state(struct radeon_device *rdev);
 569void btc_dpm_fini(struct radeon_device *rdev);
 570u32 btc_dpm_get_sclk(struct radeon_device *rdev, bool low);
 571u32 btc_dpm_get_mclk(struct radeon_device *rdev, bool low);
 572bool btc_dpm_vblank_too_short(struct radeon_device *rdev);
 573void btc_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 574                                                     struct seq_file *m);
 575u32 btc_dpm_get_current_sclk(struct radeon_device *rdev);
 576u32 btc_dpm_get_current_mclk(struct radeon_device *rdev);
 577int sumo_dpm_init(struct radeon_device *rdev);
 578int sumo_dpm_enable(struct radeon_device *rdev);
 579int sumo_dpm_late_enable(struct radeon_device *rdev);
 580void sumo_dpm_disable(struct radeon_device *rdev);
 581int sumo_dpm_pre_set_power_state(struct radeon_device *rdev);
 582int sumo_dpm_set_power_state(struct radeon_device *rdev);
 583void sumo_dpm_post_set_power_state(struct radeon_device *rdev);
 584void sumo_dpm_setup_asic(struct radeon_device *rdev);
 585void sumo_dpm_display_configuration_changed(struct radeon_device *rdev);
 586void sumo_dpm_fini(struct radeon_device *rdev);
 587u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low);
 588u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low);
 589void sumo_dpm_print_power_state(struct radeon_device *rdev,
 590                                struct radeon_ps *ps);
 591void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 592                                                      struct seq_file *m);
 593int sumo_dpm_force_performance_level(struct radeon_device *rdev,
 594                                     enum radeon_dpm_forced_level level);
 595u32 sumo_dpm_get_current_sclk(struct radeon_device *rdev);
 596u32 sumo_dpm_get_current_mclk(struct radeon_device *rdev);
 597u16 sumo_dpm_get_current_vddc(struct radeon_device *rdev);
 598
 599/*
 600 * cayman
 601 */
 602void cayman_fence_ring_emit(struct radeon_device *rdev,
 603                            struct radeon_fence *fence);
 604void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
 605int cayman_init(struct radeon_device *rdev);
 606void cayman_fini(struct radeon_device *rdev);
 607int cayman_suspend(struct radeon_device *rdev);
 608int cayman_resume(struct radeon_device *rdev);
 609int cayman_asic_reset(struct radeon_device *rdev, bool hard);
 610void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 611int cayman_vm_init(struct radeon_device *rdev);
 612void cayman_vm_fini(struct radeon_device *rdev);
 613void cayman_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 614                     unsigned vm_id, uint64_t pd_addr);
 615uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
 616int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 617int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 618void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
 619                                struct radeon_ib *ib);
 620bool cayman_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 621bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 622
 623void cayman_dma_vm_copy_pages(struct radeon_device *rdev,
 624                              struct radeon_ib *ib,
 625                              uint64_t pe, uint64_t src,
 626                              unsigned count);
 627void cayman_dma_vm_write_pages(struct radeon_device *rdev,
 628                               struct radeon_ib *ib,
 629                               uint64_t pe,
 630                               uint64_t addr, unsigned count,
 631                               uint32_t incr, uint32_t flags);
 632void cayman_dma_vm_set_pages(struct radeon_device *rdev,
 633                             struct radeon_ib *ib,
 634                             uint64_t pe,
 635                             uint64_t addr, unsigned count,
 636                             uint32_t incr, uint32_t flags);
 637void cayman_dma_vm_pad_ib(struct radeon_ib *ib);
 638
 639void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 640                         unsigned vm_id, uint64_t pd_addr);
 641
 642u32 cayman_gfx_get_rptr(struct radeon_device *rdev,
 643                        struct radeon_ring *ring);
 644u32 cayman_gfx_get_wptr(struct radeon_device *rdev,
 645                        struct radeon_ring *ring);
 646void cayman_gfx_set_wptr(struct radeon_device *rdev,
 647                         struct radeon_ring *ring);
 648uint32_t cayman_dma_get_rptr(struct radeon_device *rdev,
 649                             struct radeon_ring *ring);
 650uint32_t cayman_dma_get_wptr(struct radeon_device *rdev,
 651                             struct radeon_ring *ring);
 652void cayman_dma_set_wptr(struct radeon_device *rdev,
 653                         struct radeon_ring *ring);
 654int cayman_get_allowed_info_register(struct radeon_device *rdev,
 655                                     u32 reg, u32 *val);
 656
 657int ni_dpm_init(struct radeon_device *rdev);
 658void ni_dpm_setup_asic(struct radeon_device *rdev);
 659int ni_dpm_enable(struct radeon_device *rdev);
 660void ni_dpm_disable(struct radeon_device *rdev);
 661int ni_dpm_pre_set_power_state(struct radeon_device *rdev);
 662int ni_dpm_set_power_state(struct radeon_device *rdev);
 663void ni_dpm_post_set_power_state(struct radeon_device *rdev);
 664void ni_dpm_fini(struct radeon_device *rdev);
 665u32 ni_dpm_get_sclk(struct radeon_device *rdev, bool low);
 666u32 ni_dpm_get_mclk(struct radeon_device *rdev, bool low);
 667void ni_dpm_print_power_state(struct radeon_device *rdev,
 668                              struct radeon_ps *ps);
 669void ni_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 670                                                    struct seq_file *m);
 671int ni_dpm_force_performance_level(struct radeon_device *rdev,
 672                                   enum radeon_dpm_forced_level level);
 673bool ni_dpm_vblank_too_short(struct radeon_device *rdev);
 674u32 ni_dpm_get_current_sclk(struct radeon_device *rdev);
 675u32 ni_dpm_get_current_mclk(struct radeon_device *rdev);
 676int trinity_dpm_init(struct radeon_device *rdev);
 677int trinity_dpm_enable(struct radeon_device *rdev);
 678int trinity_dpm_late_enable(struct radeon_device *rdev);
 679void trinity_dpm_disable(struct radeon_device *rdev);
 680int trinity_dpm_pre_set_power_state(struct radeon_device *rdev);
 681int trinity_dpm_set_power_state(struct radeon_device *rdev);
 682void trinity_dpm_post_set_power_state(struct radeon_device *rdev);
 683void trinity_dpm_setup_asic(struct radeon_device *rdev);
 684void trinity_dpm_display_configuration_changed(struct radeon_device *rdev);
 685void trinity_dpm_fini(struct radeon_device *rdev);
 686u32 trinity_dpm_get_sclk(struct radeon_device *rdev, bool low);
 687u32 trinity_dpm_get_mclk(struct radeon_device *rdev, bool low);
 688void trinity_dpm_print_power_state(struct radeon_device *rdev,
 689                                   struct radeon_ps *ps);
 690void trinity_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 691                                                         struct seq_file *m);
 692int trinity_dpm_force_performance_level(struct radeon_device *rdev,
 693                                        enum radeon_dpm_forced_level level);
 694void trinity_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 695u32 trinity_dpm_get_current_sclk(struct radeon_device *rdev);
 696u32 trinity_dpm_get_current_mclk(struct radeon_device *rdev);
 697int tn_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 698
 699/* DCE6 - SI */
 700void dce6_bandwidth_update(struct radeon_device *rdev);
 701void dce6_audio_fini(struct radeon_device *rdev);
 702
 703/*
 704 * si
 705 */
 706void si_fence_ring_emit(struct radeon_device *rdev,
 707                        struct radeon_fence *fence);
 708void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
 709int si_init(struct radeon_device *rdev);
 710void si_fini(struct radeon_device *rdev);
 711int si_suspend(struct radeon_device *rdev);
 712int si_resume(struct radeon_device *rdev);
 713bool si_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 714bool si_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 715int si_asic_reset(struct radeon_device *rdev, bool hard);
 716void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 717int si_irq_set(struct radeon_device *rdev);
 718int si_irq_process(struct radeon_device *rdev);
 719int si_vm_init(struct radeon_device *rdev);
 720void si_vm_fini(struct radeon_device *rdev);
 721void si_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 722                 unsigned vm_id, uint64_t pd_addr);
 723int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 724struct radeon_fence *si_copy_dma(struct radeon_device *rdev,
 725                                 uint64_t src_offset, uint64_t dst_offset,
 726                                 unsigned num_gpu_pages,
 727                                 struct dma_resv *resv);
 728
 729void si_dma_vm_copy_pages(struct radeon_device *rdev,
 730                          struct radeon_ib *ib,
 731                          uint64_t pe, uint64_t src,
 732                          unsigned count);
 733void si_dma_vm_write_pages(struct radeon_device *rdev,
 734                           struct radeon_ib *ib,
 735                           uint64_t pe,
 736                           uint64_t addr, unsigned count,
 737                           uint32_t incr, uint32_t flags);
 738void si_dma_vm_set_pages(struct radeon_device *rdev,
 739                         struct radeon_ib *ib,
 740                         uint64_t pe,
 741                         uint64_t addr, unsigned count,
 742                         uint32_t incr, uint32_t flags);
 743
 744void si_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 745                     unsigned vm_id, uint64_t pd_addr);
 746u32 si_get_xclk(struct radeon_device *rdev);
 747uint64_t si_get_gpu_clock_counter(struct radeon_device *rdev);
 748int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 749int si_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 750int si_get_temp(struct radeon_device *rdev);
 751int si_get_allowed_info_register(struct radeon_device *rdev,
 752                                 u32 reg, u32 *val);
 753int si_dpm_init(struct radeon_device *rdev);
 754void si_dpm_setup_asic(struct radeon_device *rdev);
 755int si_dpm_enable(struct radeon_device *rdev);
 756int si_dpm_late_enable(struct radeon_device *rdev);
 757void si_dpm_disable(struct radeon_device *rdev);
 758int si_dpm_pre_set_power_state(struct radeon_device *rdev);
 759int si_dpm_set_power_state(struct radeon_device *rdev);
 760void si_dpm_post_set_power_state(struct radeon_device *rdev);
 761void si_dpm_fini(struct radeon_device *rdev);
 762void si_dpm_display_configuration_changed(struct radeon_device *rdev);
 763void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 764                                                    struct seq_file *m);
 765int si_dpm_force_performance_level(struct radeon_device *rdev,
 766                                   enum radeon_dpm_forced_level level);
 767int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
 768                                                 u32 *speed);
 769int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
 770                                                 u32 speed);
 771u32 si_fan_ctrl_get_mode(struct radeon_device *rdev);
 772void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
 773u32 si_dpm_get_current_sclk(struct radeon_device *rdev);
 774u32 si_dpm_get_current_mclk(struct radeon_device *rdev);
 775
 776/* DCE8 - CIK */
 777void dce8_bandwidth_update(struct radeon_device *rdev);
 778
 779/*
 780 * cik
 781 */
 782uint64_t cik_get_gpu_clock_counter(struct radeon_device *rdev);
 783u32 cik_get_xclk(struct radeon_device *rdev);
 784uint32_t cik_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
 785void cik_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 786int cik_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
 787int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk);
 788void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
 789                              struct radeon_fence *fence);
 790bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
 791                                  struct radeon_ring *ring,
 792                                  struct radeon_semaphore *semaphore,
 793                                  bool emit_wait);
 794void cik_sdma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 795struct radeon_fence *cik_copy_dma(struct radeon_device *rdev,
 796                                  uint64_t src_offset, uint64_t dst_offset,
 797                                  unsigned num_gpu_pages,
 798                                  struct dma_resv *resv);
 799struct radeon_fence *cik_copy_cpdma(struct radeon_device *rdev,
 800                                    uint64_t src_offset, uint64_t dst_offset,
 801                                    unsigned num_gpu_pages,
 802                                    struct dma_resv *resv);
 803int cik_sdma_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 804int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 805bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
 806void cik_fence_gfx_ring_emit(struct radeon_device *rdev,
 807                             struct radeon_fence *fence);
 808void cik_fence_compute_ring_emit(struct radeon_device *rdev,
 809                                 struct radeon_fence *fence);
 810bool cik_semaphore_ring_emit(struct radeon_device *rdev,
 811                             struct radeon_ring *cp,
 812                             struct radeon_semaphore *semaphore,
 813                             bool emit_wait);
 814void cik_pcie_gart_tlb_flush(struct radeon_device *rdev);
 815int cik_init(struct radeon_device *rdev);
 816void cik_fini(struct radeon_device *rdev);
 817int cik_suspend(struct radeon_device *rdev);
 818int cik_resume(struct radeon_device *rdev);
 819bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
 820int cik_asic_reset(struct radeon_device *rdev, bool hard);
 821void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 822int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 823int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 824int cik_irq_set(struct radeon_device *rdev);
 825int cik_irq_process(struct radeon_device *rdev);
 826int cik_vm_init(struct radeon_device *rdev);
 827void cik_vm_fini(struct radeon_device *rdev);
 828void cik_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 829                  unsigned vm_id, uint64_t pd_addr);
 830
 831void cik_sdma_vm_copy_pages(struct radeon_device *rdev,
 832                            struct radeon_ib *ib,
 833                            uint64_t pe, uint64_t src,
 834                            unsigned count);
 835void cik_sdma_vm_write_pages(struct radeon_device *rdev,
 836                             struct radeon_ib *ib,
 837                             uint64_t pe,
 838                             uint64_t addr, unsigned count,
 839                             uint32_t incr, uint32_t flags);
 840void cik_sdma_vm_set_pages(struct radeon_device *rdev,
 841                           struct radeon_ib *ib,
 842                           uint64_t pe,
 843                           uint64_t addr, unsigned count,
 844                           uint32_t incr, uint32_t flags);
 845void cik_sdma_vm_pad_ib(struct radeon_ib *ib);
 846
 847void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring,
 848                      unsigned vm_id, uint64_t pd_addr);
 849int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
 850u32 cik_gfx_get_rptr(struct radeon_device *rdev,
 851                     struct radeon_ring *ring);
 852u32 cik_gfx_get_wptr(struct radeon_device *rdev,
 853                     struct radeon_ring *ring);
 854void cik_gfx_set_wptr(struct radeon_device *rdev,
 855                      struct radeon_ring *ring);
 856u32 cik_compute_get_rptr(struct radeon_device *rdev,
 857                         struct radeon_ring *ring);
 858u32 cik_compute_get_wptr(struct radeon_device *rdev,
 859                         struct radeon_ring *ring);
 860void cik_compute_set_wptr(struct radeon_device *rdev,
 861                          struct radeon_ring *ring);
 862u32 cik_sdma_get_rptr(struct radeon_device *rdev,
 863                      struct radeon_ring *ring);
 864u32 cik_sdma_get_wptr(struct radeon_device *rdev,
 865                      struct radeon_ring *ring);
 866void cik_sdma_set_wptr(struct radeon_device *rdev,
 867                       struct radeon_ring *ring);
 868int ci_get_temp(struct radeon_device *rdev);
 869int kv_get_temp(struct radeon_device *rdev);
 870int cik_get_allowed_info_register(struct radeon_device *rdev,
 871                                  u32 reg, u32 *val);
 872
 873int ci_dpm_init(struct radeon_device *rdev);
 874int ci_dpm_enable(struct radeon_device *rdev);
 875int ci_dpm_late_enable(struct radeon_device *rdev);
 876void ci_dpm_disable(struct radeon_device *rdev);
 877int ci_dpm_pre_set_power_state(struct radeon_device *rdev);
 878int ci_dpm_set_power_state(struct radeon_device *rdev);
 879void ci_dpm_post_set_power_state(struct radeon_device *rdev);
 880void ci_dpm_setup_asic(struct radeon_device *rdev);
 881void ci_dpm_display_configuration_changed(struct radeon_device *rdev);
 882void ci_dpm_fini(struct radeon_device *rdev);
 883u32 ci_dpm_get_sclk(struct radeon_device *rdev, bool low);
 884u32 ci_dpm_get_mclk(struct radeon_device *rdev, bool low);
 885void ci_dpm_print_power_state(struct radeon_device *rdev,
 886                              struct radeon_ps *ps);
 887void ci_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 888                                                    struct seq_file *m);
 889int ci_dpm_force_performance_level(struct radeon_device *rdev,
 890                                   enum radeon_dpm_forced_level level);
 891bool ci_dpm_vblank_too_short(struct radeon_device *rdev);
 892void ci_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 893u32 ci_dpm_get_current_sclk(struct radeon_device *rdev);
 894u32 ci_dpm_get_current_mclk(struct radeon_device *rdev);
 895
 896int ci_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev,
 897                                                 u32 *speed);
 898int ci_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev,
 899                                                 u32 speed);
 900u32 ci_fan_ctrl_get_mode(struct radeon_device *rdev);
 901void ci_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode);
 902
 903int kv_dpm_init(struct radeon_device *rdev);
 904int kv_dpm_enable(struct radeon_device *rdev);
 905int kv_dpm_late_enable(struct radeon_device *rdev);
 906void kv_dpm_disable(struct radeon_device *rdev);
 907int kv_dpm_pre_set_power_state(struct radeon_device *rdev);
 908int kv_dpm_set_power_state(struct radeon_device *rdev);
 909void kv_dpm_post_set_power_state(struct radeon_device *rdev);
 910void kv_dpm_setup_asic(struct radeon_device *rdev);
 911void kv_dpm_display_configuration_changed(struct radeon_device *rdev);
 912void kv_dpm_fini(struct radeon_device *rdev);
 913u32 kv_dpm_get_sclk(struct radeon_device *rdev, bool low);
 914u32 kv_dpm_get_mclk(struct radeon_device *rdev, bool low);
 915void kv_dpm_print_power_state(struct radeon_device *rdev,
 916                              struct radeon_ps *ps);
 917void kv_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
 918                                                    struct seq_file *m);
 919int kv_dpm_force_performance_level(struct radeon_device *rdev,
 920                                   enum radeon_dpm_forced_level level);
 921void kv_dpm_powergate_uvd(struct radeon_device *rdev, bool gate);
 922void kv_dpm_enable_bapm(struct radeon_device *rdev, bool enable);
 923u32 kv_dpm_get_current_sclk(struct radeon_device *rdev);
 924u32 kv_dpm_get_current_mclk(struct radeon_device *rdev);
 925
 926/* uvd v1.0 */
 927uint32_t uvd_v1_0_get_rptr(struct radeon_device *rdev,
 928                           struct radeon_ring *ring);
 929uint32_t uvd_v1_0_get_wptr(struct radeon_device *rdev,
 930                           struct radeon_ring *ring);
 931void uvd_v1_0_set_wptr(struct radeon_device *rdev,
 932                       struct radeon_ring *ring);
 933int uvd_v1_0_resume(struct radeon_device *rdev);
 934
 935int uvd_v1_0_init(struct radeon_device *rdev);
 936void uvd_v1_0_fini(struct radeon_device *rdev);
 937int uvd_v1_0_start(struct radeon_device *rdev);
 938void uvd_v1_0_stop(struct radeon_device *rdev);
 939
 940int uvd_v1_0_ring_test(struct radeon_device *rdev, struct radeon_ring *ring);
 941void uvd_v1_0_fence_emit(struct radeon_device *rdev,
 942                         struct radeon_fence *fence);
 943int uvd_v1_0_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
 944bool uvd_v1_0_semaphore_emit(struct radeon_device *rdev,
 945                             struct radeon_ring *ring,
 946                             struct radeon_semaphore *semaphore,
 947                             bool emit_wait);
 948void uvd_v1_0_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
 949
 950/* uvd v2.2 */
 951int uvd_v2_2_resume(struct radeon_device *rdev);
 952void uvd_v2_2_fence_emit(struct radeon_device *rdev,
 953                         struct radeon_fence *fence);
 954bool uvd_v2_2_semaphore_emit(struct radeon_device *rdev,
 955                             struct radeon_ring *ring,
 956                             struct radeon_semaphore *semaphore,
 957                             bool emit_wait);
 958
 959/* uvd v3.1 */
 960bool uvd_v3_1_semaphore_emit(struct radeon_device *rdev,
 961                             struct radeon_ring *ring,
 962                             struct radeon_semaphore *semaphore,
 963                             bool emit_wait);
 964
 965/* uvd v4.2 */
 966int uvd_v4_2_resume(struct radeon_device *rdev);
 967
 968/* vce v1.0 */
 969uint32_t vce_v1_0_get_rptr(struct radeon_device *rdev,
 970                           struct radeon_ring *ring);
 971uint32_t vce_v1_0_get_wptr(struct radeon_device *rdev,
 972                           struct radeon_ring *ring);
 973void vce_v1_0_set_wptr(struct radeon_device *rdev,
 974                       struct radeon_ring *ring);
 975int vce_v1_0_load_fw(struct radeon_device *rdev, uint32_t *data);
 976unsigned vce_v1_0_bo_size(struct radeon_device *rdev);
 977int vce_v1_0_resume(struct radeon_device *rdev);
 978int vce_v1_0_init(struct radeon_device *rdev);
 979int vce_v1_0_start(struct radeon_device *rdev);
 980
 981/* vce v2.0 */
 982unsigned vce_v2_0_bo_size(struct radeon_device *rdev);
 983int vce_v2_0_resume(struct radeon_device *rdev);
 984
 985#endif
 986