linux/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
   4 */
   5
   6#include <linux/component.h>
   7#include <linux/module.h>
   8#include <linux/of_device.h>
   9#include <linux/platform_device.h>
  10
  11#include <drm/drm_crtc_helper.h>
  12#include <drm/drm_of.h>
  13#include <drm/drm_simple_kms_helper.h>
  14
  15#include "sun8i_dw_hdmi.h"
  16#include "sun8i_tcon_top.h"
  17
  18static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
  19                                           struct drm_display_mode *mode,
  20                                           struct drm_display_mode *adj_mode)
  21{
  22        struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);
  23
  24        clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
  25}
  26
  27static const struct drm_encoder_helper_funcs
  28sun8i_dw_hdmi_encoder_helper_funcs = {
  29        .mode_set = sun8i_dw_hdmi_encoder_mode_set,
  30};
  31
  32static enum drm_mode_status
  33sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data,
  34                              const struct drm_display_info *info,
  35                              const struct drm_display_mode *mode)
  36{
  37        if (mode->clock > 297000)
  38                return MODE_CLOCK_HIGH;
  39
  40        return MODE_OK;
  41}
  42
  43static enum drm_mode_status
  44sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data,
  45                            const struct drm_display_info *info,
  46                            const struct drm_display_mode *mode)
  47{
  48        /*
  49         * Controller support maximum of 594 MHz, which correlates to
  50         * 4K@60Hz 4:4:4 or RGB.
  51         */
  52        if (mode->clock > 594000)
  53                return MODE_CLOCK_HIGH;
  54
  55        return MODE_OK;
  56}
  57
  58static bool sun8i_dw_hdmi_node_is_tcon_top(struct device_node *node)
  59{
  60        return IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
  61                !!of_match_node(sun8i_tcon_top_of_table, node);
  62}
  63
  64static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm,
  65                                             struct device_node *node)
  66{
  67        struct device_node *port, *ep, *remote, *remote_port;
  68        u32 crtcs = 0;
  69
  70        remote = of_graph_get_remote_node(node, 0, -1);
  71        if (!remote)
  72                return 0;
  73
  74        if (sun8i_dw_hdmi_node_is_tcon_top(remote)) {
  75                port = of_graph_get_port_by_id(remote, 4);
  76                if (!port)
  77                        goto crtcs_exit;
  78
  79                for_each_child_of_node(port, ep) {
  80                        remote_port = of_graph_get_remote_port(ep);
  81                        if (remote_port) {
  82                                crtcs |= drm_of_crtc_port_mask(drm, remote_port);
  83                                of_node_put(remote_port);
  84                        }
  85                }
  86        } else {
  87                crtcs = drm_of_find_possible_crtcs(drm, node);
  88        }
  89
  90crtcs_exit:
  91        of_node_put(remote);
  92
  93        return crtcs;
  94}
  95
  96static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev,
  97                                             struct platform_device **pdev_out)
  98{
  99        struct platform_device *pdev;
 100        struct device_node *remote;
 101
 102        remote = of_graph_get_remote_node(dev->of_node, 1, -1);
 103        if (!remote)
 104                return -ENODEV;
 105
 106        if (!of_device_is_compatible(remote, "hdmi-connector")) {
 107                of_node_put(remote);
 108                return -ENODEV;
 109        }
 110
 111        pdev = of_find_device_by_node(remote);
 112        of_node_put(remote);
 113        if (!pdev)
 114                return -ENODEV;
 115
 116        *pdev_out = pdev;
 117        return 0;
 118}
 119
 120static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
 121                              void *data)
 122{
 123        struct platform_device *pdev = to_platform_device(dev), *connector_pdev;
 124        struct dw_hdmi_plat_data *plat_data;
 125        struct drm_device *drm = data;
 126        struct device_node *phy_node;
 127        struct drm_encoder *encoder;
 128        struct sun8i_dw_hdmi *hdmi;
 129        int ret;
 130
 131        if (!pdev->dev.of_node)
 132                return -ENODEV;
 133
 134        hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
 135        if (!hdmi)
 136                return -ENOMEM;
 137
 138        plat_data = &hdmi->plat_data;
 139        hdmi->dev = &pdev->dev;
 140        encoder = &hdmi->encoder;
 141
 142        hdmi->quirks = of_device_get_match_data(dev);
 143
 144        encoder->possible_crtcs =
 145                sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node);
 146        /*
 147         * If we failed to find the CRTC(s) which this encoder is
 148         * supposed to be connected to, it's because the CRTC has
 149         * not been registered yet.  Defer probing, and hope that
 150         * the required CRTC is added later.
 151         */
 152        if (encoder->possible_crtcs == 0)
 153                return -EPROBE_DEFER;
 154
 155        hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
 156        if (IS_ERR(hdmi->rst_ctrl)) {
 157                dev_err(dev, "Could not get ctrl reset control\n");
 158                return PTR_ERR(hdmi->rst_ctrl);
 159        }
 160
 161        hdmi->clk_tmds = devm_clk_get(dev, "tmds");
 162        if (IS_ERR(hdmi->clk_tmds)) {
 163                dev_err(dev, "Couldn't get the tmds clock\n");
 164                return PTR_ERR(hdmi->clk_tmds);
 165        }
 166
 167        hdmi->regulator = devm_regulator_get(dev, "hvcc");
 168        if (IS_ERR(hdmi->regulator)) {
 169                dev_err(dev, "Couldn't get regulator\n");
 170                return PTR_ERR(hdmi->regulator);
 171        }
 172
 173        ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev);
 174        if (!ret) {
 175                hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev,
 176                                                  "ddc-en", GPIOD_OUT_HIGH);
 177                platform_device_put(connector_pdev);
 178
 179                if (IS_ERR(hdmi->ddc_en)) {
 180                        dev_err(dev, "Couldn't get ddc-en gpio\n");
 181                        return PTR_ERR(hdmi->ddc_en);
 182                }
 183        }
 184
 185        ret = regulator_enable(hdmi->regulator);
 186        if (ret) {
 187                dev_err(dev, "Failed to enable regulator\n");
 188                goto err_unref_ddc_en;
 189        }
 190
 191        gpiod_set_value(hdmi->ddc_en, 1);
 192
 193        ret = reset_control_deassert(hdmi->rst_ctrl);
 194        if (ret) {
 195                dev_err(dev, "Could not deassert ctrl reset control\n");
 196                goto err_disable_ddc_en;
 197        }
 198
 199        ret = clk_prepare_enable(hdmi->clk_tmds);
 200        if (ret) {
 201                dev_err(dev, "Could not enable tmds clock\n");
 202                goto err_assert_ctrl_reset;
 203        }
 204
 205        phy_node = of_parse_phandle(dev->of_node, "phys", 0);
 206        if (!phy_node) {
 207                dev_err(dev, "Can't found PHY phandle\n");
 208                ret = -EINVAL;
 209                goto err_disable_clk_tmds;
 210        }
 211
 212        ret = sun8i_hdmi_phy_get(hdmi, phy_node);
 213        of_node_put(phy_node);
 214        if (ret) {
 215                dev_err(dev, "Couldn't get the HDMI PHY\n");
 216                goto err_disable_clk_tmds;
 217        }
 218
 219        ret = sun8i_hdmi_phy_init(hdmi->phy);
 220        if (ret)
 221                goto err_disable_clk_tmds;
 222
 223        drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
 224        drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
 225
 226        plat_data->mode_valid = hdmi->quirks->mode_valid;
 227        plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe;
 228        sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data);
 229
 230        platform_set_drvdata(pdev, hdmi);
 231
 232        hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
 233
 234        /*
 235         * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
 236         * which would have called the encoder cleanup.  Do it manually.
 237         */
 238        if (IS_ERR(hdmi->hdmi)) {
 239                ret = PTR_ERR(hdmi->hdmi);
 240                goto cleanup_encoder;
 241        }
 242
 243        return 0;
 244
 245cleanup_encoder:
 246        drm_encoder_cleanup(encoder);
 247err_disable_clk_tmds:
 248        clk_disable_unprepare(hdmi->clk_tmds);
 249err_assert_ctrl_reset:
 250        reset_control_assert(hdmi->rst_ctrl);
 251err_disable_ddc_en:
 252        gpiod_set_value(hdmi->ddc_en, 0);
 253        regulator_disable(hdmi->regulator);
 254err_unref_ddc_en:
 255        if (hdmi->ddc_en)
 256                gpiod_put(hdmi->ddc_en);
 257
 258        return ret;
 259}
 260
 261static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
 262                                 void *data)
 263{
 264        struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev);
 265
 266        dw_hdmi_unbind(hdmi->hdmi);
 267        sun8i_hdmi_phy_deinit(hdmi->phy);
 268        clk_disable_unprepare(hdmi->clk_tmds);
 269        reset_control_assert(hdmi->rst_ctrl);
 270        gpiod_set_value(hdmi->ddc_en, 0);
 271        regulator_disable(hdmi->regulator);
 272
 273        if (hdmi->ddc_en)
 274                gpiod_put(hdmi->ddc_en);
 275}
 276
 277static const struct component_ops sun8i_dw_hdmi_ops = {
 278        .bind   = sun8i_dw_hdmi_bind,
 279        .unbind = sun8i_dw_hdmi_unbind,
 280};
 281
 282static int sun8i_dw_hdmi_probe(struct platform_device *pdev)
 283{
 284        return component_add(&pdev->dev, &sun8i_dw_hdmi_ops);
 285}
 286
 287static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
 288{
 289        component_del(&pdev->dev, &sun8i_dw_hdmi_ops);
 290
 291        return 0;
 292}
 293
 294static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
 295        .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
 296};
 297
 298static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
 299        .mode_valid = sun8i_dw_hdmi_mode_valid_h6,
 300        .use_drm_infoframe = true,
 301};
 302
 303static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
 304        {
 305                .compatible = "allwinner,sun8i-a83t-dw-hdmi",
 306                .data = &sun8i_a83t_quirks,
 307        },
 308        {
 309                .compatible = "allwinner,sun50i-h6-dw-hdmi",
 310                .data = &sun50i_h6_quirks,
 311        },
 312        { /* sentinel */ },
 313};
 314MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
 315
 316static struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
 317        .probe  = sun8i_dw_hdmi_probe,
 318        .remove = sun8i_dw_hdmi_remove,
 319        .driver = {
 320                .name = "sun8i-dw-hdmi",
 321                .of_match_table = sun8i_dw_hdmi_dt_ids,
 322        },
 323};
 324
 325static int __init sun8i_dw_hdmi_init(void)
 326{
 327        int ret;
 328
 329        ret = platform_driver_register(&sun8i_dw_hdmi_pltfm_driver);
 330        if (ret)
 331                return ret;
 332
 333        ret = platform_driver_register(&sun8i_hdmi_phy_driver);
 334        if (ret) {
 335                platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
 336                return ret;
 337        }
 338
 339        return ret;
 340}
 341
 342static void __exit sun8i_dw_hdmi_exit(void)
 343{
 344        platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
 345        platform_driver_unregister(&sun8i_hdmi_phy_driver);
 346}
 347
 348module_init(sun8i_dw_hdmi_init);
 349module_exit(sun8i_dw_hdmi_exit);
 350
 351MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
 352MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
 353MODULE_LICENSE("GPL");
 354