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6#ifndef _SUN8I_DW_HDMI_H_
7#define _SUN8I_DW_HDMI_H_
8
9#include <drm/bridge/dw_hdmi.h>
10#include <drm/drm_encoder.h>
11#include <linux/clk.h>
12#include <linux/gpio/consumer.h>
13#include <linux/regmap.h>
14#include <linux/regulator/consumer.h>
15#include <linux/reset.h>
16
17#define SUN8I_HDMI_PHY_DBG_CTRL_REG 0x0000
18#define SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK BIT(0)
19#define SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK GENMASK(15, 8)
20#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC BIT(8)
21#define SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC BIT(9)
22#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK GENMASK(23, 16)
23#define SUN8I_HDMI_PHY_DBG_CTRL_ADDR(addr) (addr << 16)
24
25#define SUN8I_HDMI_PHY_REXT_CTRL_REG 0x0004
26#define SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN BIT(31)
27
28#define SUN8I_HDMI_PHY_READ_EN_REG 0x0010
29#define SUN8I_HDMI_PHY_READ_EN_MAGIC 0x54524545
30
31#define SUN8I_HDMI_PHY_UNSCRAMBLE_REG 0x0014
32#define SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC 0x42494E47
33
34#define SUN8I_HDMI_PHY_ANA_CFG1_REG 0x0020
35#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SWI BIT(31)
36#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWEND BIT(30)
37#define SUN8I_HDMI_PHY_ANA_CFG1_REG_PWENC BIT(29)
38#define SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW BIT(28)
39#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVRCAL(x) ((x) << 26)
40#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(x) ((x) << 24)
41#define SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT BIT(23)
42#define SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT BIT(22)
43#define SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT BIT(21)
44#define SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT BIT(20)
45#define SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL BIT(19)
46#define SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG BIT(18)
47#define SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS BIT(17)
48#define SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN BIT(16)
49#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK GENMASK(15, 12)
50#define SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL (0xf << 12)
51#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK BIT(11)
52#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 BIT(10)
53#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 BIT(9)
54#define SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 BIT(8)
55#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK BIT(7)
56#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 BIT(6)
57#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 BIT(5)
58#define SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 BIT(4)
59#define SUN8I_HDMI_PHY_ANA_CFG1_CKEN BIT(3)
60#define SUN8I_HDMI_PHY_ANA_CFG1_LDOEN BIT(2)
61#define SUN8I_HDMI_PHY_ANA_CFG1_ENVBS BIT(1)
62#define SUN8I_HDMI_PHY_ANA_CFG1_ENBI BIT(0)
63
64#define SUN8I_HDMI_PHY_ANA_CFG2_REG 0x0024
65#define SUN8I_HDMI_PHY_ANA_CFG2_M_EN BIT(31)
66#define SUN8I_HDMI_PHY_ANA_CFG2_PLLDBEN BIT(30)
67#define SUN8I_HDMI_PHY_ANA_CFG2_SEN BIT(29)
68#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDPD BIT(28)
69#define SUN8I_HDMI_PHY_ANA_CFG2_REG_HPDEN BIT(27)
70#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLRCK BIT(26)
71#define SUN8I_HDMI_PHY_ANA_CFG2_REG_PLR(x) ((x) << 23)
72#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK BIT(22)
73#define SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN BIT(21)
74#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CD(x) ((x) << 19)
75#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(x) ((x) << 17)
76#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK BIT(16)
77#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW BIT(15)
78#define SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(x) ((x) << 13)
79#define SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(x) ((x) << 10)
80#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOSTCK(x) ((x) << 8)
81#define SUN8I_HDMI_PHY_ANA_CFG2_REG_BOOST(x) ((x) << 6)
82#define SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(x) ((x) << 0)
83
84#define SUN8I_HDMI_PHY_ANA_CFG3_REG 0x0028
85#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOWCK(x) ((x) << 30)
86#define SUN8I_HDMI_PHY_ANA_CFG3_REG_SLOW(x) ((x) << 28)
87#define SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(x) ((x) << 18)
88#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(x) ((x) << 14)
89#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMPCK(x) ((x) << 11)
90#define SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(x) ((x) << 7)
91#define SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(x) ((x) << 4)
92#define SUN8I_HDMI_PHY_ANA_CFG3_SDAPD BIT(3)
93#define SUN8I_HDMI_PHY_ANA_CFG3_SDAEN BIT(2)
94#define SUN8I_HDMI_PHY_ANA_CFG3_SCLPD BIT(1)
95#define SUN8I_HDMI_PHY_ANA_CFG3_SCLEN BIT(0)
96
97#define SUN8I_HDMI_PHY_PLL_CFG1_REG 0x002c
98#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 BIT(31)
99#define SUN8I_HDMI_PHY_PLL_CFG1_REG_OD BIT(30)
100#define SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN BIT(29)
101#define SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN BIT(28)
102#define SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 BIT(27)
103#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK BIT(26)
104#define SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT 26
105#define SUN8I_HDMI_PHY_PLL_CFG1_PLLEN BIT(25)
106#define SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(x) ((x) << 22)
107#define SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(x) ((x) << 20)
108#define SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN BIT(19)
109#define SUN8I_HDMI_PHY_PLL_CFG1_CS BIT(18)
110#define SUN8I_HDMI_PHY_PLL_CFG1_CP_S(x) ((x) << 13)
111#define SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(x) ((x) << 7)
112#define SUN8I_HDMI_PHY_PLL_CFG1_BWS BIT(6)
113#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK GENMASK(5, 0)
114#define SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT 0
115
116#define SUN8I_HDMI_PHY_PLL_CFG2_REG 0x0030
117#define SUN8I_HDMI_PHY_PLL_CFG2_SV_H BIT(31)
118#define SUN8I_HDMI_PHY_PLL_CFG2_PDCLKSEL(x) ((x) << 29)
119#define SUN8I_HDMI_PHY_PLL_CFG2_CLKSTEP(x) ((x) << 27)
120#define SUN8I_HDMI_PHY_PLL_CFG2_PSET(x) ((x) << 24)
121#define SUN8I_HDMI_PHY_PLL_CFG2_PCLK_SEL BIT(23)
122#define SUN8I_HDMI_PHY_PLL_CFG2_AUTOSYNC_DIS BIT(22)
123#define SUN8I_HDMI_PHY_PLL_CFG2_VREG2_OUT_EN BIT(21)
124#define SUN8I_HDMI_PHY_PLL_CFG2_VREG1_OUT_EN BIT(20)
125#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN BIT(19)
126#define SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN(x) ((x) << 16)
127#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(x) ((x) << 12)
128#define SUN8I_HDMI_PHY_PLL_CFG2_VCO_RST_IN BIT(11)
129#define SUN8I_HDMI_PHY_PLL_CFG2_SINT_FRAC BIT(10)
130#define SUN8I_HDMI_PHY_PLL_CFG2_SDIV2 BIT(9)
131#define SUN8I_HDMI_PHY_PLL_CFG2_S(x) ((x) << 6)
132#define SUN8I_HDMI_PHY_PLL_CFG2_S6P25_7P5 BIT(5)
133#define SUN8I_HDMI_PHY_PLL_CFG2_S5_7 BIT(4)
134#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK GENMASK(3, 0)
135#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT 0
136#define SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(x) (((x) - 1) << 0)
137
138#define SUN8I_HDMI_PHY_PLL_CFG3_REG 0x0034
139#define SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2 BIT(0)
140
141#define SUN8I_HDMI_PHY_ANA_STS_REG 0x0038
142#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT 11
143#define SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK GENMASK(16, 11)
144#define SUN8I_HDMI_PHY_ANA_STS_RCALEND2D BIT(7)
145#define SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK GENMASK(5, 0)
146
147#define SUN8I_HDMI_PHY_CEC_REG 0x003c
148
149struct sun8i_hdmi_phy;
150
151struct sun8i_hdmi_phy_variant {
152 bool has_phy_clk;
153 bool has_second_pll;
154 unsigned int is_custom_phy : 1;
155 const struct dw_hdmi_curr_ctrl *cur_ctr;
156 const struct dw_hdmi_mpll_config *mpll_cfg;
157 const struct dw_hdmi_phy_config *phy_cfg;
158 void (*phy_init)(struct sun8i_hdmi_phy *phy);
159 void (*phy_disable)(struct dw_hdmi *hdmi,
160 struct sun8i_hdmi_phy *phy);
161 int (*phy_config)(struct dw_hdmi *hdmi,
162 struct sun8i_hdmi_phy *phy,
163 unsigned int clk_rate);
164};
165
166struct sun8i_hdmi_phy {
167 struct clk *clk_bus;
168 struct clk *clk_mod;
169 struct clk *clk_phy;
170 struct clk *clk_pll0;
171 struct clk *clk_pll1;
172 struct device *dev;
173 unsigned int rcal;
174 struct regmap *regs;
175 struct reset_control *rst_phy;
176 struct sun8i_hdmi_phy_variant *variant;
177};
178
179struct sun8i_dw_hdmi_quirks {
180 enum drm_mode_status (*mode_valid)(struct dw_hdmi *hdmi, void *data,
181 const struct drm_display_info *info,
182 const struct drm_display_mode *mode);
183 unsigned int use_drm_infoframe : 1;
184};
185
186struct sun8i_dw_hdmi {
187 struct clk *clk_tmds;
188 struct device *dev;
189 struct dw_hdmi *hdmi;
190 struct drm_encoder encoder;
191 struct sun8i_hdmi_phy *phy;
192 struct dw_hdmi_plat_data plat_data;
193 struct regulator *regulator;
194 const struct sun8i_dw_hdmi_quirks *quirks;
195 struct reset_control *rst_ctrl;
196 struct gpio_desc *ddc_en;
197};
198
199extern struct platform_driver sun8i_hdmi_phy_driver;
200
201static inline struct sun8i_dw_hdmi *
202encoder_to_sun8i_dw_hdmi(struct drm_encoder *encoder)
203{
204 return container_of(encoder, struct sun8i_dw_hdmi, encoder);
205}
206
207int sun8i_hdmi_phy_get(struct sun8i_dw_hdmi *hdmi, struct device_node *node);
208
209int sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy);
210void sun8i_hdmi_phy_deinit(struct sun8i_hdmi_phy *phy);
211void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy,
212 struct dw_hdmi_plat_data *plat_data);
213
214int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
215 bool second_parent);
216
217#endif
218
