LXR linux/drivers/gpu/drm/tegra/dp.h

   1/* SPDX-License-Identifier: MIT */
   2/*
   3 * Copyright (C) 2013-2019 NVIDIA Corporation.
   4 * Copyright (C) 2015 Rob Clark
   5 */
   6
   7#ifndef DRM_TEGRA_DP_H
   8#define DRM_TEGRA_DP_H 1
   9
  10#include <linux/types.h>
  11
  12struct drm_display_info;
  13struct drm_display_mode;
  14struct drm_dp_aux;
  15struct drm_dp_link;
  16
  17/**
  18 * struct drm_dp_link_caps - DP link capabilities
  19 */
  20struct drm_dp_link_caps {
  21        /**
  22         * @enhanced_framing:
  23         *
  24         * enhanced framing capability (mandatory as of DP 1.2)
  25         */
  26        bool enhanced_framing;
  27
  28        /**
  29         * tps3_supported:
  30         *
  31         * training pattern sequence 3 supported for equalization
  32         */
  33        bool tps3_supported;
  34
  35        /**
  36         * @fast_training:
  37         *
  38         * AUX CH handshake not required for link training
  39         */
  40        bool fast_training;
  41
  42        /**
  43         * @channel_coding:
  44         *
  45         * ANSI 8B/10B channel coding capability
  46         */
  47        bool channel_coding;
  48
  49        /**
  50         * @alternate_scrambler_reset:
  51         *
  52         * eDP alternate scrambler reset capability
  53         */
  54        bool alternate_scrambler_reset;
  55};
  56
  57void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
  58                           const struct drm_dp_link_caps *src);
  59
  60/**
  61 * struct drm_dp_link_ops - DP link operations
  62 */
  63struct drm_dp_link_ops {
  64        /**
  65         * @apply_training:
  66         */
  67        int (*apply_training)(struct drm_dp_link *link);
  68
  69        /**
  70         * @configure:
  71         */
  72        int (*configure)(struct drm_dp_link *link);
  73};
  74
  75#define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
  76#define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
  77#define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
  78
  79/**
  80 * struct drm_dp_link_train_set - link training settings
  81 * @voltage_swing: per-lane voltage swing
  82 * @pre_emphasis: per-lane pre-emphasis
  83 * @post_cursor: per-lane post-cursor
  84 */
  85struct drm_dp_link_train_set {
  86        unsigned int voltage_swing[4];
  87        unsigned int pre_emphasis[4];
  88        unsigned int post_cursor[4];
  89};
  90
  91/**
  92 * struct drm_dp_link_train - link training state information
  93 * @request: currently requested settings
  94 * @adjust: adjustments requested by sink
  95 * @pattern: currently requested training pattern
  96 * @clock_recovered: flag to track if clock recovery has completed
  97 * @channel_equalized: flag to track if channel equalization has completed
  98 */
  99struct drm_dp_link_train {
 100        struct drm_dp_link_train_set request;
 101        struct drm_dp_link_train_set adjust;
 102
 103        unsigned int pattern;
 104
 105        bool clock_recovered;
 106        bool channel_equalized;
 107};
 108
 109/**
 110 * struct drm_dp_link - DP link capabilities and configuration
 111 * @revision: DP specification revision supported on the link
 112 * @max_rate: maximum clock rate supported on the link
 113 * @max_lanes: maximum number of lanes supported on the link
 114 * @caps: capabilities supported on the link (see &drm_dp_link_caps)
 115 * @aux_rd_interval: AUX read interval to use for training (in microseconds)
 116 * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
 117 * @rate: currently configured link rate
 118 * @lanes: currently configured number of lanes
 119 * @rates: additional supported link rates in kHz (eDP 1.4)
 120 * @num_rates: number of additional supported link rates (eDP 1.4)
 121 */
 122struct drm_dp_link {
 123        unsigned char revision;
 124        unsigned int max_rate;
 125        unsigned int max_lanes;
 126
 127        struct drm_dp_link_caps caps;
 128
 129        /**
 130         * @cr: clock recovery read interval
 131         * @ce: channel equalization read interval
 132         */
 133        struct {
 134                unsigned int cr;
 135                unsigned int ce;
 136        } aux_rd_interval;
 137
 138        unsigned char edp;
 139
 140        unsigned int rate;
 141        unsigned int lanes;
 142
 143        unsigned long rates[DP_MAX_SUPPORTED_RATES];
 144        unsigned int num_rates;
 145
 146        /**
 147         * @ops: DP link operations
 148         */
 149        const struct drm_dp_link_ops *ops;
 150
 151        /**
 152         * @aux: DP AUX channel
 153         */
 154        struct drm_dp_aux *aux;
 155
 156        /**
 157         * @train: DP link training state
 158         */
 159        struct drm_dp_link_train train;
 160};
 161
 162int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
 163int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
 164void drm_dp_link_update_rates(struct drm_dp_link *link);
 165
 166int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
 167int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
 168int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
 169int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
 170int drm_dp_link_choose(struct drm_dp_link *link,
 171                       const struct drm_display_mode *mode,
 172                       const struct drm_display_info *info);
 173
 174void drm_dp_link_train_init(struct drm_dp_link_train *train);
 175int drm_dp_link_train(struct drm_dp_link *link);
 176
 177#endif
 178