linux/drivers/gpu/drm/tegra/hub.h
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   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#ifndef TEGRA_HUB_H
   7#define TEGRA_HUB_H 1
   8
   9#include <drm/drm_plane.h>
  10
  11#include "plane.h"
  12
  13struct tegra_dc;
  14
  15struct tegra_windowgroup {
  16        unsigned int usecount;
  17        struct mutex lock;
  18
  19        unsigned int index;
  20        struct host1x_client *parent;
  21        struct reset_control *rst;
  22};
  23
  24struct tegra_shared_plane {
  25        struct tegra_plane base;
  26        struct tegra_windowgroup *wgrp;
  27};
  28
  29static inline struct tegra_shared_plane *
  30to_tegra_shared_plane(struct drm_plane *plane)
  31{
  32        return container_of(plane, struct tegra_shared_plane, base.base);
  33}
  34
  35struct tegra_display_hub_soc {
  36        unsigned int num_wgrps;
  37        bool supports_dsc;
  38};
  39
  40struct tegra_display_hub {
  41        struct drm_private_obj base;
  42        struct host1x_client client;
  43        struct clk *clk_disp;
  44        struct clk *clk_dsc;
  45        struct clk *clk_hub;
  46        struct reset_control *rst;
  47
  48        unsigned int num_heads;
  49        struct clk **clk_heads;
  50
  51        const struct tegra_display_hub_soc *soc;
  52        struct tegra_windowgroup *wgrps;
  53};
  54
  55static inline struct tegra_display_hub *
  56to_tegra_display_hub(struct host1x_client *client)
  57{
  58        return container_of(client, struct tegra_display_hub, client);
  59}
  60
  61struct tegra_display_hub_state {
  62        struct drm_private_state base;
  63
  64        struct tegra_dc *dc;
  65        unsigned long rate;
  66        struct clk *clk;
  67};
  68
  69static inline struct tegra_display_hub_state *
  70to_tegra_display_hub_state(struct drm_private_state *priv)
  71{
  72        return container_of(priv, struct tegra_display_hub_state, base);
  73}
  74
  75struct tegra_dc;
  76struct tegra_plane;
  77
  78int tegra_display_hub_prepare(struct tegra_display_hub *hub);
  79void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
  80
  81struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
  82                                            struct tegra_dc *dc,
  83                                            unsigned int wgrp,
  84                                            unsigned int index);
  85
  86int tegra_display_hub_atomic_check(struct drm_device *drm,
  87                                   struct drm_atomic_state *state);
  88void tegra_display_hub_atomic_commit(struct drm_device *drm,
  89                                     struct drm_atomic_state *state);
  90
  91#define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
  92#define  LATENCY_EVENT (1 << 3)
  93
  94#define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
  95#define  CURS_SLOTS(x) (((x) & 0xff) << 8)
  96#define  WGRP_SLOTS(x) (((x) & 0xff) << 0)
  97
  98#endif /* TEGRA_HUB_H */
  99