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26#include <trace/events/dma_fence.h>
27
28#include "virtgpu_drv.h"
29
30#define to_virtio_gpu_fence(x) \
31 container_of(x, struct virtio_gpu_fence, f)
32
33static const char *virtio_gpu_get_driver_name(struct dma_fence *f)
34{
35 return "virtio_gpu";
36}
37
38static const char *virtio_gpu_get_timeline_name(struct dma_fence *f)
39{
40 return "controlq";
41}
42
43static bool virtio_gpu_fence_signaled(struct dma_fence *f)
44{
45
46
47
48 WARN_ON_ONCE(f->seqno == 0);
49 return false;
50}
51
52static void virtio_gpu_fence_value_str(struct dma_fence *f, char *str, int size)
53{
54 snprintf(str, size, "[%llu, %llu]", f->context, f->seqno);
55}
56
57static void virtio_gpu_timeline_value_str(struct dma_fence *f, char *str,
58 int size)
59{
60 struct virtio_gpu_fence *fence = to_virtio_gpu_fence(f);
61
62 snprintf(str, size, "%llu",
63 (u64)atomic64_read(&fence->drv->last_fence_id));
64}
65
66static const struct dma_fence_ops virtio_gpu_fence_ops = {
67 .get_driver_name = virtio_gpu_get_driver_name,
68 .get_timeline_name = virtio_gpu_get_timeline_name,
69 .signaled = virtio_gpu_fence_signaled,
70 .fence_value_str = virtio_gpu_fence_value_str,
71 .timeline_value_str = virtio_gpu_timeline_value_str,
72};
73
74struct virtio_gpu_fence *virtio_gpu_fence_alloc(struct virtio_gpu_device *vgdev)
75{
76 struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv;
77 struct virtio_gpu_fence *fence = kzalloc(sizeof(struct virtio_gpu_fence),
78 GFP_KERNEL);
79 if (!fence)
80 return fence;
81
82 fence->drv = drv;
83
84
85
86
87
88 dma_fence_init(&fence->f, &virtio_gpu_fence_ops, &drv->lock, drv->context,
89 0);
90
91 return fence;
92}
93
94void virtio_gpu_fence_emit(struct virtio_gpu_device *vgdev,
95 struct virtio_gpu_ctrl_hdr *cmd_hdr,
96 struct virtio_gpu_fence *fence)
97{
98 struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv;
99 unsigned long irq_flags;
100
101 spin_lock_irqsave(&drv->lock, irq_flags);
102 fence->fence_id = fence->f.seqno = ++drv->current_fence_id;
103 dma_fence_get(&fence->f);
104 list_add_tail(&fence->node, &drv->fences);
105 spin_unlock_irqrestore(&drv->lock, irq_flags);
106
107 trace_dma_fence_emit(&fence->f);
108
109 cmd_hdr->flags |= cpu_to_le32(VIRTIO_GPU_FLAG_FENCE);
110 cmd_hdr->fence_id = cpu_to_le64(fence->fence_id);
111}
112
113void virtio_gpu_fence_event_process(struct virtio_gpu_device *vgdev,
114 u64 fence_id)
115{
116 struct virtio_gpu_fence_driver *drv = &vgdev->fence_drv;
117 struct virtio_gpu_fence *signaled, *curr, *tmp;
118 unsigned long irq_flags;
119
120 spin_lock_irqsave(&drv->lock, irq_flags);
121 atomic64_set(&vgdev->fence_drv.last_fence_id, fence_id);
122 list_for_each_entry_safe(curr, tmp, &drv->fences, node) {
123 if (fence_id != curr->fence_id)
124 continue;
125
126 signaled = curr;
127
128
129
130
131
132 list_for_each_entry_safe(curr, tmp, &drv->fences, node) {
133
134 if (signaled->f.context != curr->f.context)
135 continue;
136
137 if (!dma_fence_is_later(&signaled->f, &curr->f))
138 continue;
139
140 dma_fence_signal_locked(&curr->f);
141 list_del(&curr->node);
142 dma_fence_put(&curr->f);
143 }
144
145 dma_fence_signal_locked(&signaled->f);
146 list_del(&signaled->node);
147 dma_fence_put(&signaled->f);
148 break;
149 }
150 spin_unlock_irqrestore(&drv->lock, irq_flags);
151}
152