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6#ifndef __IPU_PRV_H__
7#define __IPU_PRV_H__
8
9struct ipu_soc;
10
11#include <linux/types.h>
12#include <linux/device.h>
13#include <linux/clk.h>
14#include <linux/platform_device.h>
15
16#include <video/imx-ipu-v3.h>
17
18#define IPU_MCU_T_DEFAULT 8
19#define IPU_CM_IDMAC_REG_OFS 0x00008000
20#define IPU_CM_IC_REG_OFS 0x00020000
21#define IPU_CM_IRT_REG_OFS 0x00028000
22#define IPU_CM_CSI0_REG_OFS 0x00030000
23#define IPU_CM_CSI1_REG_OFS 0x00038000
24#define IPU_CM_SMFC_REG_OFS 0x00050000
25#define IPU_CM_DC_REG_OFS 0x00058000
26#define IPU_CM_DMFC_REG_OFS 0x00060000
27
28
29
30#define IPU_CM_REG(offset) (offset)
31
32#define IPU_CONF IPU_CM_REG(0)
33
34#define IPU_SRM_PRI1 IPU_CM_REG(0x00a0)
35#define IPU_SRM_PRI2 IPU_CM_REG(0x00a4)
36#define IPU_FS_PROC_FLOW1 IPU_CM_REG(0x00a8)
37#define IPU_FS_PROC_FLOW2 IPU_CM_REG(0x00ac)
38#define IPU_FS_PROC_FLOW3 IPU_CM_REG(0x00b0)
39#define IPU_FS_DISP_FLOW1 IPU_CM_REG(0x00b4)
40#define IPU_FS_DISP_FLOW2 IPU_CM_REG(0x00b8)
41#define IPU_SKIP IPU_CM_REG(0x00bc)
42#define IPU_DISP_ALT_CONF IPU_CM_REG(0x00c0)
43#define IPU_DISP_GEN IPU_CM_REG(0x00c4)
44#define IPU_DISP_ALT1 IPU_CM_REG(0x00c8)
45#define IPU_DISP_ALT2 IPU_CM_REG(0x00cc)
46#define IPU_DISP_ALT3 IPU_CM_REG(0x00d0)
47#define IPU_DISP_ALT4 IPU_CM_REG(0x00d4)
48#define IPU_SNOOP IPU_CM_REG(0x00d8)
49#define IPU_MEM_RST IPU_CM_REG(0x00dc)
50#define IPU_PM IPU_CM_REG(0x00e0)
51#define IPU_GPR IPU_CM_REG(0x00e4)
52#define IPU_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0150 + 4 * ((ch) / 32))
53#define IPU_ALT_CHA_DB_MODE_SEL(ch) IPU_CM_REG(0x0168 + 4 * ((ch) / 32))
54#define IPU_CHA_CUR_BUF(ch) IPU_CM_REG(0x023C + 4 * ((ch) / 32))
55#define IPU_ALT_CUR_BUF0 IPU_CM_REG(0x0244)
56#define IPU_ALT_CUR_BUF1 IPU_CM_REG(0x0248)
57#define IPU_SRM_STAT IPU_CM_REG(0x024C)
58#define IPU_PROC_TASK_STAT IPU_CM_REG(0x0250)
59#define IPU_DISP_TASK_STAT IPU_CM_REG(0x0254)
60#define IPU_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0268 + 4 * ((ch) / 32))
61#define IPU_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0270 + 4 * ((ch) / 32))
62#define IPU_CHA_BUF2_RDY(ch) IPU_CM_REG(0x0288 + 4 * ((ch) / 32))
63#define IPU_ALT_CHA_BUF0_RDY(ch) IPU_CM_REG(0x0278 + 4 * ((ch) / 32))
64#define IPU_ALT_CHA_BUF1_RDY(ch) IPU_CM_REG(0x0280 + 4 * ((ch) / 32))
65
66#define IPU_INT_CTRL(n) IPU_CM_REG(0x003C + 4 * (n))
67#define IPU_INT_STAT(n) IPU_CM_REG(0x0200 + 4 * (n))
68
69
70#define DP_S_SRM_MODE_MASK (0x3 << 3)
71#define DP_S_SRM_MODE_NOW (0x3 << 3)
72#define DP_S_SRM_MODE_NEXT_FRAME (0x1 << 3)
73
74
75#define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0)
76#define FS_PRPENC_ROT_SRC_SEL_ENC (0x7 << 0)
77#define FS_PRPVF_ROT_SRC_SEL_MASK (0xf << 8)
78#define FS_PRPVF_ROT_SRC_SEL_VF (0x8 << 8)
79#define FS_PP_SRC_SEL_MASK (0xf << 12)
80#define FS_PP_ROT_SRC_SEL_MASK (0xf << 16)
81#define FS_PP_ROT_SRC_SEL_PP (0x5 << 16)
82#define FS_VDI1_SRC_SEL_MASK (0x3 << 20)
83#define FS_VDI3_SRC_SEL_MASK (0x3 << 20)
84#define FS_PRP_SRC_SEL_MASK (0xf << 24)
85#define FS_VDI_SRC_SEL_MASK (0x3 << 28)
86#define FS_VDI_SRC_SEL_CSI_DIRECT (0x1 << 28)
87#define FS_VDI_SRC_SEL_VDOA (0x2 << 28)
88
89
90#define FS_PRP_ENC_DEST_SEL_MASK (0xf << 0)
91#define FS_PRP_ENC_DEST_SEL_IRT_ENC (0x1 << 0)
92#define FS_PRPVF_DEST_SEL_MASK (0xf << 4)
93#define FS_PRPVF_DEST_SEL_IRT_VF (0x1 << 4)
94#define FS_PRPVF_ROT_DEST_SEL_MASK (0xf << 8)
95#define FS_PP_DEST_SEL_MASK (0xf << 12)
96#define FS_PP_DEST_SEL_IRT_PP (0x3 << 12)
97#define FS_PP_ROT_DEST_SEL_MASK (0xf << 16)
98#define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20)
99#define FS_PRP_DEST_SEL_MASK (0xf << 24)
100
101#define IPU_DI0_COUNTER_RELEASE (1 << 24)
102#define IPU_DI1_COUNTER_RELEASE (1 << 25)
103
104#define IPU_IDMAC_REG(offset) (offset)
105
106#define IDMAC_CONF IPU_IDMAC_REG(0x0000)
107#define IDMAC_CHA_EN(ch) IPU_IDMAC_REG(0x0004 + 4 * ((ch) / 32))
108#define IDMAC_SEP_ALPHA IPU_IDMAC_REG(0x000c)
109#define IDMAC_ALT_SEP_ALPHA IPU_IDMAC_REG(0x0010)
110#define IDMAC_CHA_PRI(ch) IPU_IDMAC_REG(0x0014 + 4 * ((ch) / 32))
111#define IDMAC_WM_EN(ch) IPU_IDMAC_REG(0x001c + 4 * ((ch) / 32))
112#define IDMAC_CH_LOCK_EN_1 IPU_IDMAC_REG(0x0024)
113#define IDMAC_CH_LOCK_EN_2 IPU_IDMAC_REG(0x0028)
114#define IDMAC_SUB_ADDR_0 IPU_IDMAC_REG(0x002c)
115#define IDMAC_SUB_ADDR_1 IPU_IDMAC_REG(0x0030)
116#define IDMAC_SUB_ADDR_2 IPU_IDMAC_REG(0x0034)
117#define IDMAC_BAND_EN(ch) IPU_IDMAC_REG(0x0040 + 4 * ((ch) / 32))
118#define IDMAC_CHA_BUSY(ch) IPU_IDMAC_REG(0x0100 + 4 * ((ch) / 32))
119
120#define IPU_NUM_IRQS (32 * 15)
121
122enum ipu_modules {
123 IPU_CONF_CSI0_EN = (1 << 0),
124 IPU_CONF_CSI1_EN = (1 << 1),
125 IPU_CONF_IC_EN = (1 << 2),
126 IPU_CONF_ROT_EN = (1 << 3),
127 IPU_CONF_ISP_EN = (1 << 4),
128 IPU_CONF_DP_EN = (1 << 5),
129 IPU_CONF_DI0_EN = (1 << 6),
130 IPU_CONF_DI1_EN = (1 << 7),
131 IPU_CONF_SMFC_EN = (1 << 8),
132 IPU_CONF_DC_EN = (1 << 9),
133 IPU_CONF_DMFC_EN = (1 << 10),
134
135 IPU_CONF_VDI_EN = (1 << 12),
136
137 IPU_CONF_IDMAC_DIS = (1 << 22),
138
139 IPU_CONF_IC_DMFC_SEL = (1 << 25),
140 IPU_CONF_IC_DMFC_SYNC = (1 << 26),
141 IPU_CONF_VDI_DMFC_SYNC = (1 << 27),
142
143 IPU_CONF_CSI0_DATA_SOURCE = (1 << 28),
144 IPU_CONF_CSI1_DATA_SOURCE = (1 << 29),
145 IPU_CONF_IC_INPUT = (1 << 30),
146 IPU_CONF_CSI_SEL = (1 << 31),
147};
148
149struct ipuv3_channel {
150 unsigned int num;
151 struct ipu_soc *ipu;
152 struct list_head list;
153};
154
155struct ipu_cpmem;
156struct ipu_csi;
157struct ipu_dc_priv;
158struct ipu_dmfc_priv;
159struct ipu_di;
160struct ipu_ic_priv;
161struct ipu_vdi;
162struct ipu_image_convert_priv;
163struct ipu_smfc_priv;
164struct ipu_pre;
165struct ipu_prg;
166
167struct ipu_devtype;
168
169struct ipu_soc {
170 struct device *dev;
171 const struct ipu_devtype *devtype;
172 enum ipuv3_type ipu_type;
173 spinlock_t lock;
174 struct mutex channel_lock;
175 struct list_head channels;
176
177 void __iomem *cm_reg;
178 void __iomem *idmac_reg;
179
180 int id;
181 int usecount;
182
183 struct clk *clk;
184
185 int irq_sync;
186 int irq_err;
187 struct irq_domain *domain;
188
189 struct ipu_cpmem *cpmem_priv;
190 struct ipu_dc_priv *dc_priv;
191 struct ipu_dp_priv *dp_priv;
192 struct ipu_dmfc_priv *dmfc_priv;
193 struct ipu_di *di_priv[2];
194 struct ipu_csi *csi_priv[2];
195 struct ipu_ic_priv *ic_priv;
196 struct ipu_vdi *vdi_priv;
197 struct ipu_image_convert_priv *image_convert_priv;
198 struct ipu_smfc_priv *smfc_priv;
199 struct ipu_prg *prg_priv;
200};
201
202static inline u32 ipu_idmac_read(struct ipu_soc *ipu, unsigned offset)
203{
204 return readl(ipu->idmac_reg + offset);
205}
206
207static inline void ipu_idmac_write(struct ipu_soc *ipu, u32 value,
208 unsigned offset)
209{
210 writel(value, ipu->idmac_reg + offset);
211}
212
213void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync);
214
215int ipu_module_enable(struct ipu_soc *ipu, u32 mask);
216int ipu_module_disable(struct ipu_soc *ipu, u32 mask);
217
218bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno);
219
220int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
221 unsigned long base, u32 module, struct clk *clk_ipu);
222void ipu_csi_exit(struct ipu_soc *ipu, int id);
223
224int ipu_ic_init(struct ipu_soc *ipu, struct device *dev,
225 unsigned long base, unsigned long tpmem_base);
226void ipu_ic_exit(struct ipu_soc *ipu);
227
228int ipu_vdi_init(struct ipu_soc *ipu, struct device *dev,
229 unsigned long base, u32 module);
230void ipu_vdi_exit(struct ipu_soc *ipu);
231
232int ipu_image_convert_init(struct ipu_soc *ipu, struct device *dev);
233void ipu_image_convert_exit(struct ipu_soc *ipu);
234
235int ipu_di_init(struct ipu_soc *ipu, struct device *dev, int id,
236 unsigned long base, u32 module, struct clk *ipu_clk);
237void ipu_di_exit(struct ipu_soc *ipu, int id);
238
239int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
240 struct clk *ipu_clk);
241void ipu_dmfc_exit(struct ipu_soc *ipu);
242
243int ipu_dp_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
244void ipu_dp_exit(struct ipu_soc *ipu);
245
246int ipu_dc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
247 unsigned long template_base);
248void ipu_dc_exit(struct ipu_soc *ipu);
249
250int ipu_cpmem_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
251void ipu_cpmem_exit(struct ipu_soc *ipu);
252
253int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base);
254void ipu_smfc_exit(struct ipu_soc *ipu);
255
256struct ipu_pre *ipu_pre_lookup_by_phandle(struct device *dev, const char *name,
257 int index);
258int ipu_pre_get_available_count(void);
259int ipu_pre_get(struct ipu_pre *pre);
260void ipu_pre_put(struct ipu_pre *pre);
261u32 ipu_pre_get_baddr(struct ipu_pre *pre);
262void ipu_pre_configure(struct ipu_pre *pre, unsigned int width,
263 unsigned int height, unsigned int stride, u32 format,
264 uint64_t modifier, unsigned int bufaddr);
265void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr);
266bool ipu_pre_update_pending(struct ipu_pre *pre);
267
268struct ipu_prg *ipu_prg_lookup_by_phandle(struct device *dev, const char *name,
269 int ipu_id);
270
271extern struct platform_driver ipu_pre_drv;
272extern struct platform_driver ipu_prg_drv;
273
274#endif
275
