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16#include <linux/bitops.h>
17#include <linux/err.h>
18#include <linux/hwmon.h>
19#include <linux/init.h>
20#include <linux/module.h>
21#include <linux/pci.h>
22#include <linux/pci_ids.h>
23#include <asm/amd_nb.h>
24#include <asm/processor.h>
25
26MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
27MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
28MODULE_LICENSE("GPL");
29
30static bool force;
31module_param(force, bool, 0444);
32MODULE_PARM_DESC(force, "force loading on processors with erratum 319");
33
34
35static DEFINE_MUTEX(nb_smu_ind_mutex);
36
37#ifndef PCI_DEVICE_ID_AMD_15H_M70H_NB_F3
38#define PCI_DEVICE_ID_AMD_15H_M70H_NB_F3 0x15b3
39#endif
40
41
42#define CPUID_PKGTYPE_MASK GENMASK(31, 28)
43#define CPUID_PKGTYPE_F 0x00000000
44#define CPUID_PKGTYPE_AM2R2_AM3 0x10000000
45
46
47#define REG_DCT0_CONFIG_HIGH 0x094
48#define DDR3_MODE BIT(8)
49
50
51#define REG_HARDWARE_THERMAL_CONTROL 0x64
52#define HTC_ENABLE BIT(0)
53
54#define REG_REPORTED_TEMPERATURE 0xa4
55
56#define REG_NORTHBRIDGE_CAPABILITIES 0xe8
57#define NB_CAP_HTC BIT(10)
58
59
60
61
62
63
64
65#define F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET 0xd8200c64
66#define F15H_M60H_REPORTED_TEMP_CTRL_OFFSET 0xd8200ca4
67
68
69#define ZEN_REPORTED_TEMP_CTRL_BASE 0x00059800
70
71#define ZEN_CCD_TEMP(offset, x) (ZEN_REPORTED_TEMP_CTRL_BASE + \
72 (offset) + ((x) * 4))
73#define ZEN_CCD_TEMP_VALID BIT(11)
74#define ZEN_CCD_TEMP_MASK GENMASK(10, 0)
75
76#define ZEN_CUR_TEMP_SHIFT 21
77#define ZEN_CUR_TEMP_RANGE_SEL_MASK BIT(19)
78
79#define ZEN_SVI_BASE 0x0005A000
80
81
82#define F17H_M01H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0xc)
83#define F17H_M01H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
84#define F17H_M31H_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
85#define F17H_M31H_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
86
87#define F17H_M01H_CFACTOR_ICORE 1000000
88#define F17H_M01H_CFACTOR_ISOC 250000
89#define F17H_M31H_CFACTOR_ICORE 1000000
90#define F17H_M31H_CFACTOR_ISOC 310000
91
92
93#define F19H_M01_SVI_TEL_PLANE0 (ZEN_SVI_BASE + 0x14)
94#define F19H_M01_SVI_TEL_PLANE1 (ZEN_SVI_BASE + 0x10)
95
96#define F19H_M01H_CFACTOR_ICORE 1000000
97#define F19H_M01H_CFACTOR_ISOC 310000
98
99struct k10temp_data {
100 struct pci_dev *pdev;
101 void (*read_htcreg)(struct pci_dev *pdev, u32 *regval);
102 void (*read_tempreg)(struct pci_dev *pdev, u32 *regval);
103 int temp_offset;
104 u32 temp_adjust_mask;
105 u32 show_temp;
106 bool is_zen;
107 u32 ccd_offset;
108};
109
110#define TCTL_BIT 0
111#define TDIE_BIT 1
112#define TCCD_BIT(x) ((x) + 2)
113
114#define HAVE_TEMP(d, channel) ((d)->show_temp & BIT(channel))
115#define HAVE_TDIE(d) HAVE_TEMP(d, TDIE_BIT)
116
117struct tctl_offset {
118 u8 model;
119 char const *id;
120 int offset;
121};
122
123static const struct tctl_offset tctl_offset_table[] = {
124 { 0x17, "AMD Ryzen 5 1600X", 20000 },
125 { 0x17, "AMD Ryzen 7 1700X", 20000 },
126 { 0x17, "AMD Ryzen 7 1800X", 20000 },
127 { 0x17, "AMD Ryzen 7 2700X", 10000 },
128 { 0x17, "AMD Ryzen Threadripper 19", 27000 },
129 { 0x17, "AMD Ryzen Threadripper 29", 27000 },
130};
131
132static void read_htcreg_pci(struct pci_dev *pdev, u32 *regval)
133{
134 pci_read_config_dword(pdev, REG_HARDWARE_THERMAL_CONTROL, regval);
135}
136
137static void read_tempreg_pci(struct pci_dev *pdev, u32 *regval)
138{
139 pci_read_config_dword(pdev, REG_REPORTED_TEMPERATURE, regval);
140}
141
142static void amd_nb_index_read(struct pci_dev *pdev, unsigned int devfn,
143 unsigned int base, int offset, u32 *val)
144{
145 mutex_lock(&nb_smu_ind_mutex);
146 pci_bus_write_config_dword(pdev->bus, devfn,
147 base, offset);
148 pci_bus_read_config_dword(pdev->bus, devfn,
149 base + 4, val);
150 mutex_unlock(&nb_smu_ind_mutex);
151}
152
153static void read_htcreg_nb_f15(struct pci_dev *pdev, u32 *regval)
154{
155 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
156 F15H_M60H_HARDWARE_TEMP_CTRL_OFFSET, regval);
157}
158
159static void read_tempreg_nb_f15(struct pci_dev *pdev, u32 *regval)
160{
161 amd_nb_index_read(pdev, PCI_DEVFN(0, 0), 0xb8,
162 F15H_M60H_REPORTED_TEMP_CTRL_OFFSET, regval);
163}
164
165static void read_tempreg_nb_zen(struct pci_dev *pdev, u32 *regval)
166{
167 amd_smn_read(amd_pci_dev_to_node_id(pdev),
168 ZEN_REPORTED_TEMP_CTRL_BASE, regval);
169}
170
171static long get_raw_temp(struct k10temp_data *data)
172{
173 u32 regval;
174 long temp;
175
176 data->read_tempreg(data->pdev, ®val);
177 temp = (regval >> ZEN_CUR_TEMP_SHIFT) * 125;
178 if (regval & data->temp_adjust_mask)
179 temp -= 49000;
180 return temp;
181}
182
183static const char *k10temp_temp_label[] = {
184 "Tctl",
185 "Tdie",
186 "Tccd1",
187 "Tccd2",
188 "Tccd3",
189 "Tccd4",
190 "Tccd5",
191 "Tccd6",
192 "Tccd7",
193 "Tccd8",
194};
195
196static int k10temp_read_labels(struct device *dev,
197 enum hwmon_sensor_types type,
198 u32 attr, int channel, const char **str)
199{
200 switch (type) {
201 case hwmon_temp:
202 *str = k10temp_temp_label[channel];
203 break;
204 default:
205 return -EOPNOTSUPP;
206 }
207 return 0;
208}
209
210static int k10temp_read_temp(struct device *dev, u32 attr, int channel,
211 long *val)
212{
213 struct k10temp_data *data = dev_get_drvdata(dev);
214 u32 regval;
215
216 switch (attr) {
217 case hwmon_temp_input:
218 switch (channel) {
219 case 0:
220 *val = get_raw_temp(data);
221 if (*val < 0)
222 *val = 0;
223 break;
224 case 1:
225 *val = get_raw_temp(data) - data->temp_offset;
226 if (*val < 0)
227 *val = 0;
228 break;
229 case 2 ... 9:
230 amd_smn_read(amd_pci_dev_to_node_id(data->pdev),
231 ZEN_CCD_TEMP(data->ccd_offset, channel - 2),
232 ®val);
233 *val = (regval & ZEN_CCD_TEMP_MASK) * 125 - 49000;
234 break;
235 default:
236 return -EOPNOTSUPP;
237 }
238 break;
239 case hwmon_temp_max:
240 *val = 70 * 1000;
241 break;
242 case hwmon_temp_crit:
243 data->read_htcreg(data->pdev, ®val);
244 *val = ((regval >> 16) & 0x7f) * 500 + 52000;
245 break;
246 case hwmon_temp_crit_hyst:
247 data->read_htcreg(data->pdev, ®val);
248 *val = (((regval >> 16) & 0x7f)
249 - ((regval >> 24) & 0xf)) * 500 + 52000;
250 break;
251 default:
252 return -EOPNOTSUPP;
253 }
254 return 0;
255}
256
257static int k10temp_read(struct device *dev, enum hwmon_sensor_types type,
258 u32 attr, int channel, long *val)
259{
260 switch (type) {
261 case hwmon_temp:
262 return k10temp_read_temp(dev, attr, channel, val);
263 default:
264 return -EOPNOTSUPP;
265 }
266}
267
268static umode_t k10temp_is_visible(const void *_data,
269 enum hwmon_sensor_types type,
270 u32 attr, int channel)
271{
272 const struct k10temp_data *data = _data;
273 struct pci_dev *pdev = data->pdev;
274 u32 reg;
275
276 switch (type) {
277 case hwmon_temp:
278 switch (attr) {
279 case hwmon_temp_input:
280 if (!HAVE_TEMP(data, channel))
281 return 0;
282 break;
283 case hwmon_temp_max:
284 if (channel || data->is_zen)
285 return 0;
286 break;
287 case hwmon_temp_crit:
288 case hwmon_temp_crit_hyst:
289 if (channel || !data->read_htcreg)
290 return 0;
291
292 pci_read_config_dword(pdev,
293 REG_NORTHBRIDGE_CAPABILITIES,
294 ®);
295 if (!(reg & NB_CAP_HTC))
296 return 0;
297
298 data->read_htcreg(data->pdev, ®);
299 if (!(reg & HTC_ENABLE))
300 return 0;
301 break;
302 case hwmon_temp_label:
303
304 if (!data->is_zen || !HAVE_TEMP(data, channel))
305 return 0;
306 break;
307 default:
308 return 0;
309 }
310 break;
311 default:
312 return 0;
313 }
314 return 0444;
315}
316
317static bool has_erratum_319(struct pci_dev *pdev)
318{
319 u32 pkg_type, reg_dram_cfg;
320
321 if (boot_cpu_data.x86 != 0x10)
322 return false;
323
324
325
326
327
328 pkg_type = cpuid_ebx(0x80000001) & CPUID_PKGTYPE_MASK;
329 if (pkg_type == CPUID_PKGTYPE_F)
330 return true;
331 if (pkg_type != CPUID_PKGTYPE_AM2R2_AM3)
332 return false;
333
334
335 pci_bus_read_config_dword(pdev->bus,
336 PCI_DEVFN(PCI_SLOT(pdev->devfn), 2),
337 REG_DCT0_CONFIG_HIGH, ®_dram_cfg);
338 if (reg_dram_cfg & DDR3_MODE)
339 return false;
340
341
342
343
344
345
346
347 return boot_cpu_data.x86_model < 4 ||
348 (boot_cpu_data.x86_model == 4 && boot_cpu_data.x86_stepping <= 2);
349}
350
351static const struct hwmon_channel_info *k10temp_info[] = {
352 HWMON_CHANNEL_INFO(temp,
353 HWMON_T_INPUT | HWMON_T_MAX |
354 HWMON_T_CRIT | HWMON_T_CRIT_HYST |
355 HWMON_T_LABEL,
356 HWMON_T_INPUT | HWMON_T_LABEL,
357 HWMON_T_INPUT | HWMON_T_LABEL,
358 HWMON_T_INPUT | HWMON_T_LABEL,
359 HWMON_T_INPUT | HWMON_T_LABEL,
360 HWMON_T_INPUT | HWMON_T_LABEL,
361 HWMON_T_INPUT | HWMON_T_LABEL,
362 HWMON_T_INPUT | HWMON_T_LABEL,
363 HWMON_T_INPUT | HWMON_T_LABEL,
364 HWMON_T_INPUT | HWMON_T_LABEL),
365 NULL
366};
367
368static const struct hwmon_ops k10temp_hwmon_ops = {
369 .is_visible = k10temp_is_visible,
370 .read = k10temp_read,
371 .read_string = k10temp_read_labels,
372};
373
374static const struct hwmon_chip_info k10temp_chip_info = {
375 .ops = &k10temp_hwmon_ops,
376 .info = k10temp_info,
377};
378
379static void k10temp_get_ccd_support(struct pci_dev *pdev,
380 struct k10temp_data *data, int limit)
381{
382 u32 regval;
383 int i;
384
385 for (i = 0; i < limit; i++) {
386 amd_smn_read(amd_pci_dev_to_node_id(pdev),
387 ZEN_CCD_TEMP(data->ccd_offset, i), ®val);
388 if (regval & ZEN_CCD_TEMP_VALID)
389 data->show_temp |= BIT(TCCD_BIT(i));
390 }
391}
392
393static int k10temp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
394{
395 int unreliable = has_erratum_319(pdev);
396 struct device *dev = &pdev->dev;
397 struct k10temp_data *data;
398 struct device *hwmon_dev;
399 int i;
400
401 if (unreliable) {
402 if (!force) {
403 dev_err(dev,
404 "unreliable CPU thermal sensor; monitoring disabled\n");
405 return -ENODEV;
406 }
407 dev_warn(dev,
408 "unreliable CPU thermal sensor; check erratum 319\n");
409 }
410
411 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
412 if (!data)
413 return -ENOMEM;
414
415 data->pdev = pdev;
416 data->show_temp |= BIT(TCTL_BIT);
417
418 if (boot_cpu_data.x86 == 0x15 &&
419 ((boot_cpu_data.x86_model & 0xf0) == 0x60 ||
420 (boot_cpu_data.x86_model & 0xf0) == 0x70)) {
421 data->read_htcreg = read_htcreg_nb_f15;
422 data->read_tempreg = read_tempreg_nb_f15;
423 } else if (boot_cpu_data.x86 == 0x17 || boot_cpu_data.x86 == 0x18) {
424 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
425 data->read_tempreg = read_tempreg_nb_zen;
426 data->is_zen = true;
427
428 switch (boot_cpu_data.x86_model) {
429 case 0x1:
430 case 0x8:
431 case 0x11:
432 case 0x18:
433 data->ccd_offset = 0x154;
434 k10temp_get_ccd_support(pdev, data, 4);
435 break;
436 case 0x31:
437 case 0x60:
438 case 0x68:
439 case 0x71:
440 data->ccd_offset = 0x154;
441 k10temp_get_ccd_support(pdev, data, 8);
442 break;
443 }
444 } else if (boot_cpu_data.x86 == 0x19) {
445 data->temp_adjust_mask = ZEN_CUR_TEMP_RANGE_SEL_MASK;
446 data->read_tempreg = read_tempreg_nb_zen;
447 data->is_zen = true;
448
449 switch (boot_cpu_data.x86_model) {
450 case 0x0 ... 0x1:
451 case 0x21:
452 case 0x50 ... 0x5f:
453 data->ccd_offset = 0x154;
454 k10temp_get_ccd_support(pdev, data, 8);
455 break;
456 case 0x40 ... 0x4f:
457 data->ccd_offset = 0x300;
458 k10temp_get_ccd_support(pdev, data, 8);
459 break;
460 }
461 } else {
462 data->read_htcreg = read_htcreg_pci;
463 data->read_tempreg = read_tempreg_pci;
464 }
465
466 for (i = 0; i < ARRAY_SIZE(tctl_offset_table); i++) {
467 const struct tctl_offset *entry = &tctl_offset_table[i];
468
469 if (boot_cpu_data.x86 == entry->model &&
470 strstr(boot_cpu_data.x86_model_id, entry->id)) {
471 data->show_temp |= BIT(TDIE_BIT);
472 data->temp_offset = entry->offset;
473 break;
474 }
475 }
476
477 hwmon_dev = devm_hwmon_device_register_with_info(dev, "k10temp", data,
478 &k10temp_chip_info,
479 NULL);
480 return PTR_ERR_OR_ZERO(hwmon_dev);
481}
482
483static const struct pci_device_id k10temp_id_table[] = {
484 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
485 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
486 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
487 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
488 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
489 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
490 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
491 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F3) },
492 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
493 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
494 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
495 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
496 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
497 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
498 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
499 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
500 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M40H_DF_F3) },
501 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_19H_M50H_DF_F3) },
502 { PCI_VDEVICE(HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
503 {}
504};
505MODULE_DEVICE_TABLE(pci, k10temp_id_table);
506
507static struct pci_driver k10temp_driver = {
508 .name = "k10temp",
509 .id_table = k10temp_id_table,
510 .probe = k10temp_probe,
511};
512
513module_pci_driver(k10temp_driver);
514