LXR linux/drivers/hwtracing/coresight/coresight-etm.h

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
   4 */
   5
   6#ifndef _CORESIGHT_CORESIGHT_ETM_H
   7#define _CORESIGHT_CORESIGHT_ETM_H
   8
   9#include <asm/local.h>
  10#include <linux/spinlock.h>
  11#include "coresight-priv.h"
  12
  13/*
  14 * Device registers:
  15 * 0x000 - 0x2FC: Trace         registers
  16 * 0x300 - 0x314: Management    registers
  17 * 0x318 - 0xEFC: Trace         registers
  18 *
  19 * Coresight registers
  20 * 0xF00 - 0xF9C: Management    registers
  21 * 0xFA0 - 0xFA4: Management    registers in PFTv1.0
  22 *                Trace         registers in PFTv1.1
  23 * 0xFA8 - 0xFFC: Management    registers
  24 */
  25
  26/* Trace registers (0x000-0x2FC) */
  27#define ETMCR                   0x000
  28#define ETMCCR                  0x004
  29#define ETMTRIGGER              0x008
  30#define ETMSR                   0x010
  31#define ETMSCR                  0x014
  32#define ETMTSSCR                0x018
  33#define ETMTECR2                0x01c
  34#define ETMTEEVR                0x020
  35#define ETMTECR1                0x024
  36#define ETMFFLR                 0x02c
  37#define ETMACVRn(n)             (0x040 + (n * 4))
  38#define ETMACTRn(n)             (0x080 + (n * 4))
  39#define ETMCNTRLDVRn(n)         (0x140 + (n * 4))
  40#define ETMCNTENRn(n)           (0x150 + (n * 4))
  41#define ETMCNTRLDEVRn(n)        (0x160 + (n * 4))
  42#define ETMCNTVRn(n)            (0x170 + (n * 4))
  43#define ETMSQ12EVR              0x180
  44#define ETMSQ21EVR              0x184
  45#define ETMSQ23EVR              0x188
  46#define ETMSQ31EVR              0x18c
  47#define ETMSQ32EVR              0x190
  48#define ETMSQ13EVR              0x194
  49#define ETMSQR                  0x19c
  50#define ETMEXTOUTEVRn(n)        (0x1a0 + (n * 4))
  51#define ETMCIDCVRn(n)           (0x1b0 + (n * 4))
  52#define ETMCIDCMR               0x1bc
  53#define ETMIMPSPEC0             0x1c0
  54#define ETMIMPSPEC1             0x1c4
  55#define ETMIMPSPEC2             0x1c8
  56#define ETMIMPSPEC3             0x1cc
  57#define ETMIMPSPEC4             0x1d0
  58#define ETMIMPSPEC5             0x1d4
  59#define ETMIMPSPEC6             0x1d8
  60#define ETMIMPSPEC7             0x1dc
  61#define ETMSYNCFR               0x1e0
  62#define ETMIDR                  0x1e4
  63#define ETMCCER                 0x1e8
  64#define ETMEXTINSELR            0x1ec
  65#define ETMTESSEICR             0x1f0
  66#define ETMEIBCR                0x1f4
  67#define ETMTSEVR                0x1f8
  68#define ETMAUXCR                0x1fc
  69#define ETMTRACEIDR             0x200
  70#define ETMVMIDCVR              0x240
  71/* Management registers (0x300-0x314) */
  72#define ETMOSLAR                0x300
  73#define ETMOSLSR                0x304
  74#define ETMOSSRR                0x308
  75#define ETMPDCR                 0x310
  76#define ETMPDSR                 0x314
  77#define ETM_MAX_ADDR_CMP        16
  78#define ETM_MAX_CNTR            4
  79#define ETM_MAX_CTXID_CMP       3
  80
  81/* Register definition */
  82/* ETMCR - 0x00 */
  83#define ETMCR_PWD_DWN           BIT(0)
  84#define ETMCR_STALL_MODE        BIT(7)
  85#define ETMCR_BRANCH_BROADCAST  BIT(8)
  86#define ETMCR_ETM_PRG           BIT(10)
  87#define ETMCR_ETM_EN            BIT(11)
  88#define ETMCR_CYC_ACC           BIT(12)
  89#define ETMCR_CTXID_SIZE        (BIT(14)|BIT(15))
  90#define ETMCR_TIMESTAMP_EN      BIT(28)
  91#define ETMCR_RETURN_STACK      BIT(29)
  92/* ETMCCR - 0x04 */
  93#define ETMCCR_FIFOFULL         BIT(23)
  94/* ETMPDCR - 0x310 */
  95#define ETMPDCR_PWD_UP          BIT(3)
  96/* ETMTECR1 - 0x024 */
  97#define ETMTECR1_ADDR_COMP_1    BIT(0)
  98#define ETMTECR1_INC_EXC        BIT(24)
  99#define ETMTECR1_START_STOP     BIT(25)
 100/* ETMCCER - 0x1E8 */
 101#define ETMCCER_TIMESTAMP       BIT(22)
 102#define ETMCCER_RETSTACK        BIT(23)
 103
 104#define ETM_MODE_EXCLUDE        BIT(0)
 105#define ETM_MODE_CYCACC         BIT(1)
 106#define ETM_MODE_STALL          BIT(2)
 107#define ETM_MODE_TIMESTAMP      BIT(3)
 108#define ETM_MODE_CTXID          BIT(4)
 109#define ETM_MODE_BBROAD         BIT(5)
 110#define ETM_MODE_RET_STACK      BIT(6)
 111#define ETM_MODE_ALL            (ETM_MODE_EXCLUDE | ETM_MODE_CYCACC | \
 112                                 ETM_MODE_STALL | ETM_MODE_TIMESTAMP | \
 113                                 ETM_MODE_BBROAD | ETM_MODE_RET_STACK | \
 114                                 ETM_MODE_CTXID | ETM_MODE_EXCL_KERN | \
 115                                 ETM_MODE_EXCL_USER)
 116
 117#define ETM_SQR_MASK            0x3
 118#define ETM_TRACEID_MASK        0x3f
 119#define ETM_EVENT_MASK          0x1ffff
 120#define ETM_SYNC_MASK           0xfff
 121#define ETM_ALL_MASK            0xffffffff
 122
 123#define ETMSR_PROG_BIT          1
 124#define ETM_SEQ_STATE_MAX_VAL   (0x2)
 125#define PORT_SIZE_MASK          (GENMASK(21, 21) | GENMASK(6, 4))
 126
 127#define ETM_HARD_WIRE_RES_A     /* Hard wired, always true */   \
 128                                ((0x0f << 0)    |               \
 129                                /* Resource index A */          \
 130                                (0x06 << 4))
 131
 132#define ETM_ADD_COMP_0          /* Single addr comparator 1 */  \
 133                                ((0x00 << 7)    |               \
 134                                /* Resource index B */          \
 135                                (0x00 << 11))
 136
 137#define ETM_EVENT_NOT_A         BIT(14) /* NOT(A) */
 138
 139#define ETM_DEFAULT_EVENT_VAL   (ETM_HARD_WIRE_RES_A    |       \
 140                                 ETM_ADD_COMP_0         |       \
 141                                 ETM_EVENT_NOT_A)
 142
 143/**
 144 * struct etm_config - configuration information related to an ETM
 145 * @mode:       controls various modes supported by this ETM/PTM.
 146 * @ctrl:       used in conjunction with @mode.
 147 * @trigger_event: setting for register ETMTRIGGER.
 148 * @startstop_ctrl: setting for register ETMTSSCR.
 149 * @enable_event: setting for register ETMTEEVR.
 150 * @enable_ctrl1: setting for register ETMTECR1.
 151 * @enable_ctrl2: setting for register ETMTECR2.
 152 * @fifofull_level: setting for register ETMFFLR.
 153 * @addr_idx:   index for the address comparator selection.
 154 * @addr_val:   value for address comparator register.
 155 * @addr_acctype: access type for address comparator register.
 156 * @addr_type:  current status of the comparator register.
 157 * @cntr_idx:   index for the counter register selection.
 158 * @cntr_rld_val: reload value of a counter register.
 159 * @cntr_event: control for counter enable register.
 160 * @cntr_rld_event: value for counter reload event register.
 161 * @cntr_val:   counter value register.
 162 * @seq_12_event: event causing the transition from 1 to 2.
 163 * @seq_21_event: event causing the transition from 2 to 1.
 164 * @seq_23_event: event causing the transition from 2 to 3.
 165 * @seq_31_event: event causing the transition from 3 to 1.
 166 * @seq_32_event: event causing the transition from 3 to 2.
 167 * @seq_13_event: event causing the transition from 1 to 3.
 168 * @seq_curr_state: current value of the sequencer register.
 169 * @ctxid_idx: index for the context ID registers.
 170 * @ctxid_pid: value for the context ID to trigger on.
 171 * @ctxid_mask: mask applicable to all the context IDs.
 172 * @sync_freq:  Synchronisation frequency.
 173 * @timestamp_event: Defines an event that requests the insertion
 174 *                   of a timestamp into the trace stream.
 175 */
 176struct etm_config {
 177        u32                             mode;
 178        u32                             ctrl;
 179        u32                             trigger_event;
 180        u32                             startstop_ctrl;
 181        u32                             enable_event;
 182        u32                             enable_ctrl1;
 183        u32                             enable_ctrl2;
 184        u32                             fifofull_level;
 185        u8                              addr_idx;
 186        u32                             addr_val[ETM_MAX_ADDR_CMP];
 187        u32                             addr_acctype[ETM_MAX_ADDR_CMP];
 188        u32                             addr_type[ETM_MAX_ADDR_CMP];
 189        u8                              cntr_idx;
 190        u32                             cntr_rld_val[ETM_MAX_CNTR];
 191        u32                             cntr_event[ETM_MAX_CNTR];
 192        u32                             cntr_rld_event[ETM_MAX_CNTR];
 193        u32                             cntr_val[ETM_MAX_CNTR];
 194        u32                             seq_12_event;
 195        u32                             seq_21_event;
 196        u32                             seq_23_event;
 197        u32                             seq_31_event;
 198        u32                             seq_32_event;
 199        u32                             seq_13_event;
 200        u32                             seq_curr_state;
 201        u8                              ctxid_idx;
 202        u32                             ctxid_pid[ETM_MAX_CTXID_CMP];
 203        u32                             ctxid_mask;
 204        u32                             sync_freq;
 205        u32                             timestamp_event;
 206};
 207
 208/**
 209 * struct etm_drvdata - specifics associated to an ETM component
 210 * @base:       memory mapped base address for this component.
 211 * @atclk:      optional clock for the core parts of the ETM.
 212 * @csdev:      component vitals needed by the framework.
 213 * @spinlock:   only one at a time pls.
 214 * @cpu:        the cpu this component is affined to.
 215 * @port_size:  port size as reported by ETMCR bit 4-6 and 21.
 216 * @arch:       ETM/PTM version number.
 217 * @use_cpu14:  true if management registers need to be accessed via CP14.
 218 * @mode:       this tracer's mode, i.e sysFS, Perf or disabled.
 219 * @sticky_enable: true if ETM base configuration has been done.
 220 * @boot_enable:true if we should start tracing at boot time.
 221 * @os_unlock:  true if access to management registers is allowed.
 222 * @nr_addr_cmp:Number of pairs of address comparators as found in ETMCCR.
 223 * @nr_cntr:    Number of counters as found in ETMCCR bit 13-15.
 224 * @nr_ext_inp: Number of external input as found in ETMCCR bit 17-19.
 225 * @nr_ext_out: Number of external output as found in ETMCCR bit 20-22.
 226 * @nr_ctxid_cmp: Number of contextID comparators as found in ETMCCR bit 24-25.
 227 * @etmccr:     value of register ETMCCR.
 228 * @etmccer:    value of register ETMCCER.
 229 * @traceid:    value of the current ID for this component.
 230 * @config:     structure holding configuration parameters.
 231 */
 232struct etm_drvdata {
 233        void __iomem                    *base;
 234        struct clk                      *atclk;
 235        struct coresight_device         *csdev;
 236        spinlock_t                      spinlock;
 237        int                             cpu;
 238        int                             port_size;
 239        u8                              arch;
 240        bool                            use_cp14;
 241        local_t                         mode;
 242        bool                            sticky_enable;
 243        bool                            boot_enable;
 244        bool                            os_unlock;
 245        u8                              nr_addr_cmp;
 246        u8                              nr_cntr;
 247        u8                              nr_ext_inp;
 248        u8                              nr_ext_out;
 249        u8                              nr_ctxid_cmp;
 250        u32                             etmccr;
 251        u32                             etmccer;
 252        u32                             traceid;
 253        struct etm_config               config;
 254};
 255
 256static inline void etm_writel(struct etm_drvdata *drvdata,
 257                              u32 val, u32 off)
 258{
 259        if (drvdata->use_cp14) {
 260                if (etm_writel_cp14(off, val)) {
 261                        dev_err(&drvdata->csdev->dev,
 262                                "invalid CP14 access to ETM reg: %#x", off);
 263                }
 264        } else {
 265                writel_relaxed(val, drvdata->base + off);
 266        }
 267}
 268
 269static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
 270{
 271        u32 val;
 272
 273        if (drvdata->use_cp14) {
 274                if (etm_readl_cp14(off, &val)) {
 275                        dev_err(&drvdata->csdev->dev,
 276                                "invalid CP14 access to ETM reg: %#x", off);
 277                }
 278        } else {
 279                val = readl_relaxed(drvdata->base + off);
 280        }
 281
 282        return val;
 283}
 284
 285extern const struct attribute_group *coresight_etm_groups[];
 286int etm_get_trace_id(struct etm_drvdata *drvdata);
 287void etm_set_default(struct etm_config *config);
 288void etm_config_trace_mode(struct etm_config *config);
 289struct etm_config *get_etm_config(struct etm_drvdata *drvdata);
 290#endif
 291