LXR linux/drivers/i2c/busses/i2c-i801.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4    Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5    <mdsxyz123@yahoo.com>
   6    Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7    Copyright (C) 2010         Intel Corporation,
   8                               David Woodhouse <dwmw2@infradead.org>
   9
  10*/
  11
  12/*
  13 * Supports the following Intel I/O Controller Hubs (ICH):
  14 *
  15 *                                      I/O                     Block   I2C
  16 *                                      region  SMBus   Block   proc.   block
  17 * Chip name                    PCI ID  size    PEC     buffer  call    read
  18 * ---------------------------------------------------------------------------
  19 * 82801AA (ICH)                0x2413  16      no      no      no      no
  20 * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21 * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22 * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23 * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24 * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25 * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26 * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27 * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28 * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29 * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30 * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31 * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32 * ICH10                        0x3a30  32      hard    yes     yes     yes
  33 * ICH10                        0x3a60  32      hard    yes     yes     yes
  34 * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35 * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36 * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37 * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38 * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39 * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40 * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41 * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42 * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43 * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44 * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45 * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46 * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47 * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48 * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49 * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50 * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51 * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52 * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53 * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54 * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55 * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56 * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57 * Emmitsburg (PCH)             0x1bc9  32      hard    yes     yes     yes
  58 * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  59 * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  60 * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  61 * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  62 * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  63 * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  64 * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  65 * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  66 * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  67 * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  68 * Comet Lake-H (PCH)           0x06a3  32      hard    yes     yes     yes
  69 * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  70 * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  71 * Tiger Lake-H (PCH)           0x43a3  32      hard    yes     yes     yes
  72 * Jasper Lake (SOC)            0x4da3  32      hard    yes     yes     yes
  73 * Comet Lake-V (PCH)           0xa3a3  32      hard    yes     yes     yes
  74 * Alder Lake-S (PCH)           0x7aa3  32      hard    yes     yes     yes
  75 * Alder Lake-P (PCH)           0x51a3  32      hard    yes     yes     yes
  76 * Alder Lake-M (PCH)           0x54a3  32      hard    yes     yes     yes
  77 *
  78 * Features supported by this driver:
  79 * Software PEC                         no
  80 * Hardware PEC                         yes
  81 * Block buffer                         yes
  82 * Block process call transaction       yes
  83 * I2C block read transaction           yes (doesn't use the block buffer)
  84 * Slave mode                           no
  85 * SMBus Host Notify                    yes
  86 * Interrupt processing                 yes
  87 *
  88 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  89 */
  90
  91#define DRV_NAME        "i801_smbus"
  92
  93#include <linux/interrupt.h>
  94#include <linux/module.h>
  95#include <linux/pci.h>
  96#include <linux/kernel.h>
  97#include <linux/stddef.h>
  98#include <linux/delay.h>
  99#include <linux/ioport.h>
 100#include <linux/init.h>
 101#include <linux/i2c.h>
 102#include <linux/i2c-smbus.h>
 103#include <linux/acpi.h>
 104#include <linux/io.h>
 105#include <linux/dmi.h>
 106#include <linux/slab.h>
 107#include <linux/string.h>
 108#include <linux/completion.h>
 109#include <linux/err.h>
 110#include <linux/platform_device.h>
 111#include <linux/platform_data/itco_wdt.h>
 112#include <linux/pm_runtime.h>
 113#include <linux/mutex.h>
 114
 115#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 116#include <linux/gpio/machine.h>
 117#include <linux/platform_data/i2c-mux-gpio.h>
 118#endif
 119
 120/* I801 SMBus address offsets */
 121#define SMBHSTSTS(p)    (0 + (p)->smba)
 122#define SMBHSTCNT(p)    (2 + (p)->smba)
 123#define SMBHSTCMD(p)    (3 + (p)->smba)
 124#define SMBHSTADD(p)    (4 + (p)->smba)
 125#define SMBHSTDAT0(p)   (5 + (p)->smba)
 126#define SMBHSTDAT1(p)   (6 + (p)->smba)
 127#define SMBBLKDAT(p)    (7 + (p)->smba)
 128#define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 129#define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 130#define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 131#define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 132#define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 133#define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 134
 135/* PCI Address Constants */
 136#define SMBBAR          4
 137#define SMBHSTCFG       0x040
 138#define TCOBASE         0x050
 139#define TCOCTL          0x054
 140
 141#define SBREG_BAR               0x10
 142#define SBREG_SMBCTRL           0xc6000c
 143#define SBREG_SMBCTRL_DNV       0xcf000c
 144
 145/* Host configuration bits for SMBHSTCFG */
 146#define SMBHSTCFG_HST_EN        BIT(0)
 147#define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 148#define SMBHSTCFG_I2C_EN        BIT(2)
 149#define SMBHSTCFG_SPD_WD        BIT(4)
 150
 151/* TCO configuration bits for TCOCTL */
 152#define TCOCTL_EN               BIT(8)
 153
 154/* Auxiliary status register bits, ICH4+ only */
 155#define SMBAUXSTS_CRCE          BIT(0)
 156#define SMBAUXSTS_STCO          BIT(1)
 157
 158/* Auxiliary control register bits, ICH4+ only */
 159#define SMBAUXCTL_CRC           BIT(0)
 160#define SMBAUXCTL_E32B          BIT(1)
 161
 162/* I801 command constants */
 163#define I801_QUICK              0x00
 164#define I801_BYTE               0x04
 165#define I801_BYTE_DATA          0x08
 166#define I801_WORD_DATA          0x0C
 167#define I801_PROC_CALL          0x10    /* unimplemented */
 168#define I801_BLOCK_DATA         0x14
 169#define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 170#define I801_BLOCK_PROC_CALL    0x1C
 171
 172/* I801 Host Control register bits */
 173#define SMBHSTCNT_INTREN        BIT(0)
 174#define SMBHSTCNT_KILL          BIT(1)
 175#define SMBHSTCNT_LAST_BYTE     BIT(5)
 176#define SMBHSTCNT_START         BIT(6)
 177#define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 178
 179/* I801 Hosts Status register bits */
 180#define SMBHSTSTS_BYTE_DONE     BIT(7)
 181#define SMBHSTSTS_INUSE_STS     BIT(6)
 182#define SMBHSTSTS_SMBALERT_STS  BIT(5)
 183#define SMBHSTSTS_FAILED        BIT(4)
 184#define SMBHSTSTS_BUS_ERR       BIT(3)
 185#define SMBHSTSTS_DEV_ERR       BIT(2)
 186#define SMBHSTSTS_INTR          BIT(1)
 187#define SMBHSTSTS_HOST_BUSY     BIT(0)
 188
 189/* Host Notify Status register bits */
 190#define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 191
 192/* Host Notify Command register bits */
 193#define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 194
 195#define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 196                                 SMBHSTSTS_DEV_ERR)
 197
 198#define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 199                                 STATUS_ERROR_FLAGS)
 200
 201/* Older devices have their ID defined in <linux/pci_ids.h> */
 202#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 203#define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS           0x06a3
 204#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 205#define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 206#define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 207#define PCI_DEVICE_ID_INTEL_EBG_SMBUS                   0x1bc9
 208#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 209#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 210/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 211#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 212#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 213#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 214#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 215#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 216#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 217#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 218#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 219#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 220#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 221#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 222#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS           0x43a3
 223#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 224#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS           0x4da3
 225#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS          0x51a3
 226#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS          0x54a3
 227#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 228#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS          0x7aa3
 229#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 230#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 231#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 232#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 233#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 234#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 235#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 236#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 237#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 238#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 239#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 240#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 241#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 242#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 243#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 244#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 245#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS           0xa3a3
 246
 247struct i801_mux_config {
 248        char *gpio_chip;
 249        unsigned values[3];
 250        int n_values;
 251        unsigned classes[3];
 252        unsigned gpios[2];              /* Relative to gpio_chip->base */
 253        int n_gpios;
 254};
 255
 256struct i801_priv {
 257        struct i2c_adapter adapter;
 258        unsigned long smba;
 259        unsigned char original_hstcfg;
 260        unsigned char original_slvcmd;
 261        struct pci_dev *pci_dev;
 262        unsigned int features;
 263
 264        /* isr processing */
 265        struct completion done;
 266        u8 status;
 267
 268        /* Command state used by isr for byte-by-byte block transactions */
 269        u8 cmd;
 270        bool is_read;
 271        int count;
 272        int len;
 273        u8 *data;
 274
 275#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 276        const struct i801_mux_config *mux_drvdata;
 277        struct platform_device *mux_pdev;
 278        struct gpiod_lookup_table *lookup;
 279#endif
 280        struct platform_device *tco_pdev;
 281
 282        /*
 283         * If set to true the host controller registers are reserved for
 284         * ACPI AML use. Protected by acpi_lock.
 285         */
 286        bool acpi_reserved;
 287        struct mutex acpi_lock;
 288};
 289
 290#define FEATURE_SMBUS_PEC       BIT(0)
 291#define FEATURE_BLOCK_BUFFER    BIT(1)
 292#define FEATURE_BLOCK_PROC      BIT(2)
 293#define FEATURE_I2C_BLOCK_READ  BIT(3)
 294#define FEATURE_IRQ             BIT(4)
 295#define FEATURE_HOST_NOTIFY     BIT(5)
 296/* Not really a feature, but it's convenient to handle it as such */
 297#define FEATURE_IDF             BIT(15)
 298#define FEATURE_TCO_SPT         BIT(16)
 299#define FEATURE_TCO_CNL         BIT(17)
 300
 301static const char *i801_feature_names[] = {
 302        "SMBus PEC",
 303        "Block buffer",
 304        "Block process call",
 305        "I2C block read",
 306        "Interrupt",
 307        "SMBus Host Notify",
 308};
 309
 310static unsigned int disable_features;
 311module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 312MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 313        "\t\t  0x01  disable SMBus PEC\n"
 314        "\t\t  0x02  disable the block buffer\n"
 315        "\t\t  0x08  disable the I2C block read functionality\n"
 316        "\t\t  0x10  don't use interrupts\n"
 317        "\t\t  0x20  disable SMBus Host Notify ");
 318
 319/* Make sure the SMBus host is ready to start transmitting.
 320   Return 0 if it is, -EBUSY if it is not. */
 321static int i801_check_pre(struct i801_priv *priv)
 322{
 323        int status;
 324
 325        status = inb_p(SMBHSTSTS(priv));
 326        if (status & SMBHSTSTS_HOST_BUSY) {
 327                dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 328                return -EBUSY;
 329        }
 330
 331        status &= STATUS_FLAGS;
 332        if (status) {
 333                dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 334                        status);
 335                outb_p(status, SMBHSTSTS(priv));
 336                status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 337                if (status) {
 338                        dev_err(&priv->pci_dev->dev,
 339                                "Failed clearing status flags (%02x)\n",
 340                                status);
 341                        return -EBUSY;
 342                }
 343        }
 344
 345        /*
 346         * Clear CRC status if needed.
 347         * During normal operation, i801_check_post() takes care
 348         * of it after every operation.  We do it here only in case
 349         * the hardware was already in this state when the driver
 350         * started.
 351         */
 352        if (priv->features & FEATURE_SMBUS_PEC) {
 353                status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 354                if (status) {
 355                        dev_dbg(&priv->pci_dev->dev,
 356                                "Clearing aux status flags (%02x)\n", status);
 357                        outb_p(status, SMBAUXSTS(priv));
 358                        status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 359                        if (status) {
 360                                dev_err(&priv->pci_dev->dev,
 361                                        "Failed clearing aux status flags (%02x)\n",
 362                                        status);
 363                                return -EBUSY;
 364                        }
 365                }
 366        }
 367
 368        return 0;
 369}
 370
 371/*
 372 * Convert the status register to an error code, and clear it.
 373 * Note that status only contains the bits we want to clear, not the
 374 * actual register value.
 375 */
 376static int i801_check_post(struct i801_priv *priv, int status)
 377{
 378        int result = 0;
 379
 380        /*
 381         * If the SMBus is still busy, we give up
 382         * Note: This timeout condition only happens when using polling
 383         * transactions.  For interrupt operation, NAK/timeout is indicated by
 384         * DEV_ERR.
 385         */
 386        if (unlikely(status < 0)) {
 387                dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 388                /* try to stop the current command */
 389                dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 390                outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv));
 391                usleep_range(1000, 2000);
 392                outb_p(0, SMBHSTCNT(priv));
 393
 394                /* Check if it worked */
 395                status = inb_p(SMBHSTSTS(priv));
 396                if ((status & SMBHSTSTS_HOST_BUSY) ||
 397                    !(status & SMBHSTSTS_FAILED))
 398                        dev_err(&priv->pci_dev->dev,
 399                                "Failed terminating the transaction\n");
 400                outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 401                return -ETIMEDOUT;
 402        }
 403
 404        if (status & SMBHSTSTS_FAILED) {
 405                result = -EIO;
 406                dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 407        }
 408        if (status & SMBHSTSTS_DEV_ERR) {
 409                /*
 410                 * This may be a PEC error, check and clear it.
 411                 *
 412                 * AUXSTS is handled differently from HSTSTS.
 413                 * For HSTSTS, i801_isr() or i801_wait_intr()
 414                 * has already cleared the error bits in hardware,
 415                 * and we are passed a copy of the original value
 416                 * in "status".
 417                 * For AUXSTS, the hardware register is left
 418                 * for us to handle here.
 419                 * This is asymmetric, slightly iffy, but safe,
 420                 * since all this code is serialized and the CRCE
 421                 * bit is harmless as long as it's cleared before
 422                 * the next operation.
 423                 */
 424                if ((priv->features & FEATURE_SMBUS_PEC) &&
 425                    (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 426                        outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 427                        result = -EBADMSG;
 428                        dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 429                } else {
 430                        result = -ENXIO;
 431                        dev_dbg(&priv->pci_dev->dev, "No response\n");
 432                }
 433        }
 434        if (status & SMBHSTSTS_BUS_ERR) {
 435                result = -EAGAIN;
 436                dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 437        }
 438
 439        /* Clear status flags except BYTE_DONE, to be cleared by caller */
 440        outb_p(status, SMBHSTSTS(priv));
 441
 442        return result;
 443}
 444
 445/* Wait for BUSY being cleared and either INTR or an error flag being set */
 446static int i801_wait_intr(struct i801_priv *priv)
 447{
 448        unsigned long timeout = jiffies + priv->adapter.timeout;
 449        int status, busy;
 450
 451        do {
 452                usleep_range(250, 500);
 453                status = inb_p(SMBHSTSTS(priv));
 454                busy = status & SMBHSTSTS_HOST_BUSY;
 455                status &= STATUS_ERROR_FLAGS | SMBHSTSTS_INTR;
 456                if (!busy && status)
 457                        return status;
 458        } while (time_is_after_eq_jiffies(timeout));
 459
 460        return -ETIMEDOUT;
 461}
 462
 463/* Wait for either BYTE_DONE or an error flag being set */
 464static int i801_wait_byte_done(struct i801_priv *priv)
 465{
 466        unsigned long timeout = jiffies + priv->adapter.timeout;
 467        int status;
 468
 469        do {
 470                usleep_range(250, 500);
 471                status = inb_p(SMBHSTSTS(priv));
 472                if (status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE))
 473                        return status & STATUS_ERROR_FLAGS;
 474        } while (time_is_after_eq_jiffies(timeout));
 475
 476        return -ETIMEDOUT;
 477}
 478
 479static int i801_transaction(struct i801_priv *priv, int xact)
 480{
 481        int status;
 482        unsigned long result;
 483        const struct i2c_adapter *adap = &priv->adapter;
 484
 485        status = i801_check_pre(priv);
 486        if (status < 0)
 487                return status;
 488
 489        if (priv->features & FEATURE_IRQ) {
 490                reinit_completion(&priv->done);
 491                outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 492                       SMBHSTCNT(priv));
 493                result = wait_for_completion_timeout(&priv->done, adap->timeout);
 494                return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 495        }
 496
 497        /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 498         * SMBSCMD are passed in xact */
 499        outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 500
 501        status = i801_wait_intr(priv);
 502        return i801_check_post(priv, status);
 503}
 504
 505static int i801_block_transaction_by_block(struct i801_priv *priv,
 506                                           union i2c_smbus_data *data,
 507                                           char read_write, int command)
 508{
 509        int i, len, status, xact;
 510
 511        switch (command) {
 512        case I2C_SMBUS_BLOCK_PROC_CALL:
 513                xact = I801_BLOCK_PROC_CALL;
 514                break;
 515        case I2C_SMBUS_BLOCK_DATA:
 516                xact = I801_BLOCK_DATA;
 517                break;
 518        default:
 519                return -EOPNOTSUPP;
 520        }
 521
 522        inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 523
 524        /* Use 32-byte buffer to process this transaction */
 525        if (read_write == I2C_SMBUS_WRITE) {
 526                len = data->block[0];
 527                outb_p(len, SMBHSTDAT0(priv));
 528                for (i = 0; i < len; i++)
 529                        outb_p(data->block[i+1], SMBBLKDAT(priv));
 530        }
 531
 532        status = i801_transaction(priv, xact);
 533        if (status)
 534                return status;
 535
 536        if (read_write == I2C_SMBUS_READ ||
 537            command == I2C_SMBUS_BLOCK_PROC_CALL) {
 538                len = inb_p(SMBHSTDAT0(priv));
 539                if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 540                        return -EPROTO;
 541
 542                data->block[0] = len;
 543                for (i = 0; i < len; i++)
 544                        data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 545        }
 546        return 0;
 547}
 548
 549static void i801_isr_byte_done(struct i801_priv *priv)
 550{
 551        if (priv->is_read) {
 552                /* For SMBus block reads, length is received with first byte */
 553                if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 554                    (priv->count == 0)) {
 555                        priv->len = inb_p(SMBHSTDAT0(priv));
 556                        if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 557                                dev_err(&priv->pci_dev->dev,
 558                                        "Illegal SMBus block read size %d\n",
 559                                        priv->len);
 560                                /* FIXME: Recover */
 561                                priv->len = I2C_SMBUS_BLOCK_MAX;
 562                        }
 563                        priv->data[-1] = priv->len;
 564                }
 565
 566                /* Read next byte */
 567                if (priv->count < priv->len)
 568                        priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 569                else
 570                        dev_dbg(&priv->pci_dev->dev,
 571                                "Discarding extra byte on block read\n");
 572
 573                /* Set LAST_BYTE for last byte of read transaction */
 574                if (priv->count == priv->len - 1)
 575                        outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 576                               SMBHSTCNT(priv));
 577        } else if (priv->count < priv->len - 1) {
 578                /* Write next byte, except for IRQ after last byte */
 579                outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 580        }
 581
 582        /* Clear BYTE_DONE to continue with next byte */
 583        outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 584}
 585
 586static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 587{
 588        unsigned short addr;
 589
 590        addr = inb_p(SMBNTFDADD(priv)) >> 1;
 591
 592        /*
 593         * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 594         * always returns 0. Our current implementation doesn't provide
 595         * data, so we just ignore it.
 596         */
 597        i2c_handle_smbus_host_notify(&priv->adapter, addr);
 598
 599        /* clear Host Notify bit and return */
 600        outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 601        return IRQ_HANDLED;
 602}
 603
 604/*
 605 * There are three kinds of interrupts:
 606 *
 607 * 1) i801 signals transaction completion with one of these interrupts:
 608 *      INTR - Success
 609 *      DEV_ERR - Invalid command, NAK or communication timeout
 610 *      BUS_ERR - SMI# transaction collision
 611 *      FAILED - transaction was canceled due to a KILL request
 612 *    When any of these occur, update ->status and signal completion.
 613 *    ->status must be cleared before kicking off the next transaction.
 614 *
 615 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 616 *    occurs for each byte of a byte-by-byte to prepare the next byte.
 617 *
 618 * 3) Host Notify interrupts
 619 */
 620static irqreturn_t i801_isr(int irq, void *dev_id)
 621{
 622        struct i801_priv *priv = dev_id;
 623        u16 pcists;
 624        u8 status;
 625
 626        /* Confirm this is our interrupt */
 627        pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
 628        if (!(pcists & PCI_STATUS_INTERRUPT))
 629                return IRQ_NONE;
 630
 631        if (priv->features & FEATURE_HOST_NOTIFY) {
 632                status = inb_p(SMBSLVSTS(priv));
 633                if (status & SMBSLVSTS_HST_NTFY_STS)
 634                        return i801_host_notify_isr(priv);
 635        }
 636
 637        status = inb_p(SMBHSTSTS(priv));
 638        if (status & SMBHSTSTS_BYTE_DONE)
 639                i801_isr_byte_done(priv);
 640
 641        /*
 642         * Clear irq sources and report transaction result.
 643         * ->status must be cleared before the next transaction is started.
 644         */
 645        status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 646        if (status) {
 647                outb_p(status, SMBHSTSTS(priv));
 648                priv->status = status;
 649                complete(&priv->done);
 650        }
 651
 652        return IRQ_HANDLED;
 653}
 654
 655/*
 656 * For "byte-by-byte" block transactions:
 657 *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 658 *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 659 */
 660static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 661                                               union i2c_smbus_data *data,
 662                                               char read_write, int command)
 663{
 664        int i, len;
 665        int smbcmd;
 666        int status;
 667        unsigned long result;
 668        const struct i2c_adapter *adap = &priv->adapter;
 669
 670        if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 671                return -EOPNOTSUPP;
 672
 673        status = i801_check_pre(priv);
 674        if (status < 0)
 675                return status;
 676
 677        len = data->block[0];
 678
 679        if (read_write == I2C_SMBUS_WRITE) {
 680                outb_p(len, SMBHSTDAT0(priv));
 681                outb_p(data->block[1], SMBBLKDAT(priv));
 682        }
 683
 684        if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 685            read_write == I2C_SMBUS_READ)
 686                smbcmd = I801_I2C_BLOCK_DATA;
 687        else
 688                smbcmd = I801_BLOCK_DATA;
 689
 690        if (priv->features & FEATURE_IRQ) {
 691                priv->is_read = (read_write == I2C_SMBUS_READ);
 692                if (len == 1 && priv->is_read)
 693                        smbcmd |= SMBHSTCNT_LAST_BYTE;
 694                priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 695                priv->len = len;
 696                priv->count = 0;
 697                priv->data = &data->block[1];
 698
 699                reinit_completion(&priv->done);
 700                outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 701                result = wait_for_completion_timeout(&priv->done, adap->timeout);
 702                return i801_check_post(priv, result ? priv->status : -ETIMEDOUT);
 703        }
 704
 705        for (i = 1; i <= len; i++) {
 706                if (i == len && read_write == I2C_SMBUS_READ)
 707                        smbcmd |= SMBHSTCNT_LAST_BYTE;
 708                outb_p(smbcmd, SMBHSTCNT(priv));
 709
 710                if (i == 1)
 711                        outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 712                               SMBHSTCNT(priv));
 713
 714                status = i801_wait_byte_done(priv);
 715                if (status)
 716                        goto exit;
 717
 718                if (i == 1 && read_write == I2C_SMBUS_READ
 719                 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 720                        len = inb_p(SMBHSTDAT0(priv));
 721                        if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 722                                dev_err(&priv->pci_dev->dev,
 723                                        "Illegal SMBus block read size %d\n",
 724                                        len);
 725                                /* Recover */
 726                                while (inb_p(SMBHSTSTS(priv)) &
 727                                       SMBHSTSTS_HOST_BUSY)
 728                                        outb_p(SMBHSTSTS_BYTE_DONE,
 729                                               SMBHSTSTS(priv));
 730                                outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 731                                return -EPROTO;
 732                        }
 733                        data->block[0] = len;
 734                }
 735
 736                /* Retrieve/store value in SMBBLKDAT */
 737                if (read_write == I2C_SMBUS_READ)
 738                        data->block[i] = inb_p(SMBBLKDAT(priv));
 739                if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 740                        outb_p(data->block[i+1], SMBBLKDAT(priv));
 741
 742                /* signals SMBBLKDAT ready */
 743                outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 744        }
 745
 746        status = i801_wait_intr(priv);
 747exit:
 748        return i801_check_post(priv, status);
 749}
 750
 751static int i801_set_block_buffer_mode(struct i801_priv *priv)
 752{
 753        outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 754        if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 755                return -EIO;
 756        return 0;
 757}
 758
 759/* Block transaction function */
 760static int i801_block_transaction(struct i801_priv *priv, union i2c_smbus_data *data,
 761                                  char read_write, int command)
 762{
 763        int result = 0;
 764        unsigned char hostc;
 765
 766        if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 767                if (read_write == I2C_SMBUS_WRITE) {
 768                        /* set I2C_EN bit in configuration register */
 769                        pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 770                        pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 771                                              hostc | SMBHSTCFG_I2C_EN);
 772                } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 773                        dev_err(&priv->pci_dev->dev,
 774                                "I2C block read is unsupported!\n");
 775                        return -EOPNOTSUPP;
 776                }
 777        }
 778
 779        if (read_write == I2C_SMBUS_WRITE
 780         || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 781                if (data->block[0] < 1)
 782                        data->block[0] = 1;
 783                if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 784                        data->block[0] = I2C_SMBUS_BLOCK_MAX;
 785        } else {
 786                data->block[0] = 32;    /* max for SMBus block reads */
 787        }
 788
 789        /* Experience has shown that the block buffer can only be used for
 790           SMBus (not I2C) block transactions, even though the datasheet
 791           doesn't mention this limitation. */
 792        if ((priv->features & FEATURE_BLOCK_BUFFER)
 793         && command != I2C_SMBUS_I2C_BLOCK_DATA
 794         && i801_set_block_buffer_mode(priv) == 0)
 795                result = i801_block_transaction_by_block(priv, data,
 796                                                         read_write,
 797                                                         command);
 798        else
 799                result = i801_block_transaction_byte_by_byte(priv, data,
 800                                                             read_write,
 801                                                             command);
 802
 803        if (command == I2C_SMBUS_I2C_BLOCK_DATA
 804         && read_write == I2C_SMBUS_WRITE) {
 805                /* restore saved configuration register value */
 806                pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 807        }
 808        return result;
 809}
 810
 811/* Return negative errno on error. */
 812static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 813                       unsigned short flags, char read_write, u8 command,
 814                       int size, union i2c_smbus_data *data)
 815{
 816        int hwpec;
 817        int block = 0;
 818        int ret = 0, xact = 0;
 819        struct i801_priv *priv = i2c_get_adapdata(adap);
 820
 821        mutex_lock(&priv->acpi_lock);
 822        if (priv->acpi_reserved) {
 823                mutex_unlock(&priv->acpi_lock);
 824                return -EBUSY;
 825        }
 826
 827        pm_runtime_get_sync(&priv->pci_dev->dev);
 828
 829        hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 830                && size != I2C_SMBUS_QUICK
 831                && size != I2C_SMBUS_I2C_BLOCK_DATA;
 832
 833        switch (size) {
 834        case I2C_SMBUS_QUICK:
 835                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 836                       SMBHSTADD(priv));
 837                xact = I801_QUICK;
 838                break;
 839        case I2C_SMBUS_BYTE:
 840                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 841                       SMBHSTADD(priv));
 842                if (read_write == I2C_SMBUS_WRITE)
 843                        outb_p(command, SMBHSTCMD(priv));
 844                xact = I801_BYTE;
 845                break;
 846        case I2C_SMBUS_BYTE_DATA:
 847                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 848                       SMBHSTADD(priv));
 849                outb_p(command, SMBHSTCMD(priv));
 850                if (read_write == I2C_SMBUS_WRITE)
 851                        outb_p(data->byte, SMBHSTDAT0(priv));
 852                xact = I801_BYTE_DATA;
 853                break;
 854        case I2C_SMBUS_WORD_DATA:
 855                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 856                       SMBHSTADD(priv));
 857                outb_p(command, SMBHSTCMD(priv));
 858                if (read_write == I2C_SMBUS_WRITE) {
 859                        outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 860                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 861                }
 862                xact = I801_WORD_DATA;
 863                break;
 864        case I2C_SMBUS_BLOCK_DATA:
 865                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 866                       SMBHSTADD(priv));
 867                outb_p(command, SMBHSTCMD(priv));
 868                block = 1;
 869                break;
 870        case I2C_SMBUS_I2C_BLOCK_DATA:
 871                /*
 872                 * NB: page 240 of ICH5 datasheet shows that the R/#W
 873                 * bit should be cleared here, even when reading.
 874                 * However if SPD Write Disable is set (Lynx Point and later),
 875                 * the read will fail if we don't set the R/#W bit.
 876                 */
 877                outb_p(((addr & 0x7f) << 1) |
 878                       ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 879                        (read_write & 0x01) : 0),
 880                       SMBHSTADD(priv));
 881                if (read_write == I2C_SMBUS_READ) {
 882                        /* NB: page 240 of ICH5 datasheet also shows
 883                         * that DATA1 is the cmd field when reading */
 884                        outb_p(command, SMBHSTDAT1(priv));
 885                } else
 886                        outb_p(command, SMBHSTCMD(priv));
 887                block = 1;
 888                break;
 889        case I2C_SMBUS_BLOCK_PROC_CALL:
 890                /*
 891                 * Bit 0 of the slave address register always indicate a write
 892                 * command.
 893                 */
 894                outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 895                outb_p(command, SMBHSTCMD(priv));
 896                block = 1;
 897                break;
 898        default:
 899                dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 900                        size);
 901                ret = -EOPNOTSUPP;
 902                goto out;
 903        }
 904
 905        if (hwpec)      /* enable/disable hardware PEC */
 906                outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 907        else
 908                outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 909                       SMBAUXCTL(priv));
 910
 911        if (block)
 912                ret = i801_block_transaction(priv, data, read_write, size);
 913        else
 914                ret = i801_transaction(priv, xact);
 915
 916        /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 917           time, so we forcibly disable it after every transaction. Turn off
 918           E32B for the same reason. */
 919        if (hwpec || block)
 920                outb_p(inb_p(SMBAUXCTL(priv)) &
 921                       ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 922
 923        if (block)
 924                goto out;
 925        if (ret)
 926                goto out;
 927        if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 928                goto out;
 929
 930        switch (xact & 0x7f) {
 931        case I801_BYTE: /* Result put in SMBHSTDAT0 */
 932        case I801_BYTE_DATA:
 933                data->byte = inb_p(SMBHSTDAT0(priv));
 934                break;
 935        case I801_WORD_DATA:
 936                data->word = inb_p(SMBHSTDAT0(priv)) +
 937                             (inb_p(SMBHSTDAT1(priv)) << 8);
 938                break;
 939        }
 940
 941out:
 942        /* Unlock the SMBus device for use by BIOS/ACPI */
 943        outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv));
 944
 945        pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 946        pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 947        mutex_unlock(&priv->acpi_lock);
 948        return ret;
 949}
 950
 951
 952static u32 i801_func(struct i2c_adapter *adapter)
 953{
 954        struct i801_priv *priv = i2c_get_adapdata(adapter);
 955
 956        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 957               I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 958               I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 959               ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 960               ((priv->features & FEATURE_BLOCK_PROC) ?
 961                I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 962               ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 963                I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 964               ((priv->features & FEATURE_HOST_NOTIFY) ?
 965                I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 966}
 967
 968static void i801_enable_host_notify(struct i2c_adapter *adapter)
 969{
 970        struct i801_priv *priv = i2c_get_adapdata(adapter);
 971
 972        if (!(priv->features & FEATURE_HOST_NOTIFY))
 973                return;
 974
 975        if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
 976                outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
 977                       SMBSLVCMD(priv));
 978
 979        /* clear Host Notify bit to allow a new notification */
 980        outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 981}
 982
 983static void i801_disable_host_notify(struct i801_priv *priv)
 984{
 985        if (!(priv->features & FEATURE_HOST_NOTIFY))
 986                return;
 987
 988        outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
 989}
 990
 991static const struct i2c_algorithm smbus_algorithm = {
 992        .smbus_xfer     = i801_access,
 993        .functionality  = i801_func,
 994};
 995
 996static const struct pci_device_id i801_ids[] = {
 997        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 998        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 999        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1000        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },

1001        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1002        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1003        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1004        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1005        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1006        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1007        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1008        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1009        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1010        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1011        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1012        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1013        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1014        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1015        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1016        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1017        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1018        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1019        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1020        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1021        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1022        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1023        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1024        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1025        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1026        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1027        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1028        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1029        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1030        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1031        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1032        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1033        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1034        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1035        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1036        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1037        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) },
1038        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1039        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1040        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1041        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1042        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1043        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1044        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1045        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1046        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) },
1047        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) },
1048        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1049        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1050        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) },
1051        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) },
1052        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) },
1053        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS) },
1054        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS) },
1055        { 0, }
1056};
1057
1058MODULE_DEVICE_TABLE(pci, i801_ids);
1059
1060#if defined CONFIG_X86 && defined CONFIG_DMI
1061static unsigned char apanel_addr;
1062
1063/* Scan the system ROM for the signature "FJKEYINF" */
1064static __init const void __iomem *bios_signature(const void __iomem *bios)
1065{
1066        ssize_t offset;
1067        const unsigned char signature[] = "FJKEYINF";
1068
1069        for (offset = 0; offset < 0x10000; offset += 0x10) {
1070                if (check_signature(bios + offset, signature,
1071                                    sizeof(signature)-1))
1072                        return bios + offset;
1073        }
1074        return NULL;
1075}
1076
1077static void __init input_apanel_init(void)
1078{
1079        void __iomem *bios;
1080        const void __iomem *p;
1081
1082        bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1083        p = bios_signature(bios);
1084        if (p) {
1085                /* just use the first address */
1086                apanel_addr = readb(p + 8 + 3) >> 1;
1087        }
1088        iounmap(bios);
1089}
1090
1091struct dmi_onboard_device_info {
1092        const char *name;
1093        u8 type;
1094        unsigned short i2c_addr;
1095        const char *i2c_type;
1096};
1097
1098static const struct dmi_onboard_device_info dmi_devices[] = {
1099        { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1100        { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1101        { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1102};
1103
1104static void dmi_check_onboard_device(u8 type, const char *name,
1105                                     struct i2c_adapter *adap)
1106{
1107        int i;
1108        struct i2c_board_info info;
1109
1110        for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1111                /* & ~0x80, ignore enabled/disabled bit */
1112                if ((type & ~0x80) != dmi_devices[i].type)
1113                        continue;
1114                if (strcasecmp(name, dmi_devices[i].name))
1115                        continue;
1116
1117                memset(&info, 0, sizeof(struct i2c_board_info));
1118                info.addr = dmi_devices[i].i2c_addr;
1119                strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1120                i2c_new_client_device(adap, &info);
1121                break;
1122        }
1123}
1124
1125/* We use our own function to check for onboard devices instead of
1126   dmi_find_device() as some buggy BIOS's have the devices we are interested
1127   in marked as disabled */
1128static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1129{
1130        int i, count;
1131
1132        if (dm->type != 10)
1133                return;
1134
1135        count = (dm->length - sizeof(struct dmi_header)) / 2;
1136        for (i = 0; i < count; i++) {
1137                const u8 *d = (char *)(dm + 1) + (i * 2);
1138                const char *name = ((char *) dm) + dm->length;
1139                u8 type = d[0];
1140                u8 s = d[1];
1141
1142                if (!s)
1143                        continue;
1144                s--;
1145                while (s > 0 && name[0]) {
1146                        name += strlen(name) + 1;
1147                        s--;
1148                }
1149                if (name[0] == 0) /* Bogus string reference */
1150                        continue;
1151
1152                dmi_check_onboard_device(type, name, adap);
1153        }
1154}
1155
1156/* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1157static const char *const acpi_smo8800_ids[] = {
1158        "SMO8800",
1159        "SMO8801",
1160        "SMO8810",
1161        "SMO8811",
1162        "SMO8820",
1163        "SMO8821",
1164        "SMO8830",
1165        "SMO8831",
1166};
1167
1168static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1169                                             u32 nesting_level,
1170                                             void *context,
1171                                             void **return_value)
1172{
1173        struct acpi_device_info *info;
1174        acpi_status status;
1175        char *hid;
1176        int i;
1177
1178        status = acpi_get_object_info(obj_handle, &info);
1179        if (ACPI_FAILURE(status))
1180                return AE_OK;
1181
1182        if (!(info->valid & ACPI_VALID_HID))
1183                goto smo88xx_not_found;
1184
1185        hid = info->hardware_id.string;
1186        if (!hid)
1187                goto smo88xx_not_found;
1188
1189        i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1190        if (i < 0)
1191                goto smo88xx_not_found;
1192
1193        kfree(info);
1194
1195        *((bool *)return_value) = true;
1196        return AE_CTRL_TERMINATE;
1197
1198smo88xx_not_found:
1199        kfree(info);
1200        return AE_OK;
1201}
1202
1203static bool is_dell_system_with_lis3lv02d(void)
1204{
1205        bool found;
1206        const char *vendor;
1207
1208        vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1209        if (!vendor || strcmp(vendor, "Dell Inc."))
1210                return false;
1211
1212        /*
1213         * Check that ACPI device SMO88xx is present and is functioning.
1214         * Function acpi_get_devices() already filters all ACPI devices
1215         * which are not present or are not functioning.
1216         * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1217         * accelerometer but unfortunately ACPI does not provide any other
1218         * information (like I2C address).
1219         */
1220        found = false;
1221        acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1222                         (void **)&found);
1223
1224        return found;
1225}
1226
1227/*
1228 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1229 * so it is needed to define mapping table based on DMI product names.
1230 */
1231static const struct {
1232        const char *dmi_product_name;
1233        unsigned short i2c_addr;
1234} dell_lis3lv02d_devices[] = {
1235        /*
1236         * Dell platform team told us that these Latitude devices have
1237         * ST microelectronics accelerometer at I2C address 0x29.
1238         */
1239        { "Latitude E5250",     0x29 },
1240        { "Latitude E5450",     0x29 },
1241        { "Latitude E5550",     0x29 },
1242        { "Latitude E6440",     0x29 },
1243        { "Latitude E6440 ATG", 0x29 },
1244        { "Latitude E6540",     0x29 },
1245        /*
1246         * Additional individual entries were added after verification.
1247         */
1248        { "Latitude 5480",      0x29 },
1249        { "Vostro V131",        0x1d },
1250};
1251
1252static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1253{
1254        struct i2c_board_info info;
1255        const char *dmi_product_name;
1256        int i;
1257
1258        dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1259        for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1260                if (strcmp(dmi_product_name,
1261                           dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1262                        break;
1263        }
1264
1265        if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1266                dev_warn(&priv->pci_dev->dev,
1267                         "Accelerometer lis3lv02d is present on SMBus but its"
1268                         " address is unknown, skipping registration\n");
1269                return;
1270        }
1271
1272        memset(&info, 0, sizeof(struct i2c_board_info));
1273        info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1274        strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1275        i2c_new_client_device(&priv->adapter, &info);
1276}
1277
1278/* Register optional slaves */
1279static void i801_probe_optional_slaves(struct i801_priv *priv)
1280{
1281        /* Only register slaves on main SMBus channel */
1282        if (priv->features & FEATURE_IDF)
1283                return;
1284
1285        if (apanel_addr) {
1286                struct i2c_board_info info = {
1287                        .addr = apanel_addr,
1288                        .type = "fujitsu_apanel",
1289                };
1290
1291                i2c_new_client_device(&priv->adapter, &info);
1292        }
1293
1294        if (dmi_name_in_vendors("FUJITSU"))
1295                dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1296
1297        if (is_dell_system_with_lis3lv02d())
1298                register_dell_lis3lv02d_i2c_device(priv);
1299
1300        /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */
1301#if IS_ENABLED(CONFIG_I2C_MUX_GPIO)
1302        if (!priv->mux_drvdata)
1303#endif
1304                i2c_register_spd(&priv->adapter);
1305}
1306#else
1307static void __init input_apanel_init(void) {}
1308static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1309#endif  /* CONFIG_X86 && CONFIG_DMI */
1310
1311#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1312static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1313        .gpio_chip = "gpio_ich",
1314        .values = { 0x02, 0x03 },
1315        .n_values = 2,
1316        .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1317        .gpios = { 52, 53 },
1318        .n_gpios = 2,
1319};
1320
1321static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1322        .gpio_chip = "gpio_ich",
1323        .values = { 0x02, 0x03, 0x01 },
1324        .n_values = 3,
1325        .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1326        .gpios = { 52, 53 },
1327        .n_gpios = 2,
1328};
1329
1330static const struct dmi_system_id mux_dmi_table[] = {
1331        {
1332                .matches = {
1333                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1334                        DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1335                },
1336                .driver_data = &i801_mux_config_asus_z8_d12,
1337        },
1338        {
1339                .matches = {
1340                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1341                        DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1342                },
1343                .driver_data = &i801_mux_config_asus_z8_d12,
1344        },
1345        {
1346                .matches = {
1347                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1348                        DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1349                },
1350                .driver_data = &i801_mux_config_asus_z8_d12,
1351        },
1352        {
1353                .matches = {
1354                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1355                        DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1356                },
1357                .driver_data = &i801_mux_config_asus_z8_d12,
1358        },
1359        {
1360                .matches = {
1361                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1362                        DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1363                },
1364                .driver_data = &i801_mux_config_asus_z8_d12,
1365        },
1366        {
1367                .matches = {
1368                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1369                        DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1370                },
1371                .driver_data = &i801_mux_config_asus_z8_d12,
1372        },
1373        {
1374                .matches = {
1375                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1376                        DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1377                },
1378                .driver_data = &i801_mux_config_asus_z8_d18,
1379        },
1380        {
1381                .matches = {
1382                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1383                        DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1384                },
1385                .driver_data = &i801_mux_config_asus_z8_d18,
1386        },
1387        {
1388                .matches = {
1389                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1390                        DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1391                },
1392                .driver_data = &i801_mux_config_asus_z8_d12,
1393        },
1394        { }
1395};
1396
1397/* Setup multiplexing if needed */
1398static int i801_add_mux(struct i801_priv *priv)
1399{
1400        struct device *dev = &priv->adapter.dev;
1401        const struct i801_mux_config *mux_config;
1402        struct i2c_mux_gpio_platform_data gpio_data;
1403        struct gpiod_lookup_table *lookup;
1404        int i;
1405
1406        if (!priv->mux_drvdata)
1407                return 0;
1408        mux_config = priv->mux_drvdata;
1409
1410        /* Prepare the platform data */
1411        memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1412        gpio_data.parent = priv->adapter.nr;
1413        gpio_data.values = mux_config->values;
1414        gpio_data.n_values = mux_config->n_values;
1415        gpio_data.classes = mux_config->classes;
1416        gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1417
1418        /* Register GPIO descriptor lookup table */
1419        lookup = devm_kzalloc(dev,
1420                              struct_size(lookup, table, mux_config->n_gpios + 1),
1421                              GFP_KERNEL);
1422        if (!lookup)
1423                return -ENOMEM;
1424        lookup->dev_id = "i2c-mux-gpio";
1425        for (i = 0; i < mux_config->n_gpios; i++) {
1426                lookup->table[i] = (struct gpiod_lookup)
1427                        GPIO_LOOKUP(mux_config->gpio_chip,
1428                                    mux_config->gpios[i], "mux", 0);
1429        }
1430        gpiod_add_lookup_table(lookup);
1431        priv->lookup = lookup;
1432
1433        /*
1434         * Register the mux device, we use PLATFORM_DEVID_NONE here
1435         * because since we are referring to the GPIO chip by name we are
1436         * anyways in deep trouble if there is more than one of these
1437         * devices, and there should likely only be one platform controller
1438         * hub.
1439         */
1440        priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1441                                PLATFORM_DEVID_NONE, &gpio_data,
1442                                sizeof(struct i2c_mux_gpio_platform_data));
1443        if (IS_ERR(priv->mux_pdev)) {
1444                gpiod_remove_lookup_table(lookup);
1445                dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1446        }
1447
1448        return PTR_ERR_OR_ZERO(priv->mux_pdev);
1449}
1450
1451static void i801_del_mux(struct i801_priv *priv)
1452{
1453        platform_device_unregister(priv->mux_pdev);
1454        gpiod_remove_lookup_table(priv->lookup);
1455}
1456
1457static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1458{
1459        const struct dmi_system_id *id;
1460        const struct i801_mux_config *mux_config;
1461        unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1462        int i;
1463
1464        id = dmi_first_match(mux_dmi_table);
1465        if (id) {
1466                /* Remove branch classes from trunk */
1467                mux_config = id->driver_data;
1468                for (i = 0; i < mux_config->n_values; i++)
1469                        class &= ~mux_config->classes[i];
1470
1471                /* Remember for later */
1472                priv->mux_drvdata = mux_config;
1473        }
1474
1475        return class;
1476}
1477#else
1478static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1479static inline void i801_del_mux(struct i801_priv *priv) { }
1480
1481static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1482{
1483        return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1484}
1485#endif
1486
1487static const struct itco_wdt_platform_data spt_tco_platform_data = {
1488        .name = "Intel PCH",
1489        .version = 4,
1490};
1491
1492static struct platform_device *
1493i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1494                 struct resource *tco_res)
1495{
1496        static DEFINE_MUTEX(p2sb_mutex);
1497        struct resource *res;
1498        unsigned int devfn;
1499        u64 base64_addr;
1500        u32 base_addr;
1501        u8 hidden;
1502
1503        /*
1504         * We must access the NO_REBOOT bit over the Primary to Sideband
1505         * bridge (P2SB). The BIOS prevents the P2SB device from being
1506         * enumerated by the PCI subsystem, so we need to unhide/hide it
1507         * to lookup the P2SB BAR.
1508         */
1509        mutex_lock(&p2sb_mutex);
1510
1511        devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1512
1513        /* Unhide the P2SB device, if it is hidden */
1514        pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1515        if (hidden)
1516                pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1517
1518        pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1519        base64_addr = base_addr & 0xfffffff0;
1520
1521        pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1522        base64_addr |= (u64)base_addr << 32;
1523
1524        /* Hide the P2SB device, if it was hidden before */
1525        if (hidden)
1526                pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1527        mutex_unlock(&p2sb_mutex);
1528
1529        res = &tco_res[1];
1530        if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1531                res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1532        else
1533                res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1534
1535        res->end = res->start + 3;
1536        res->flags = IORESOURCE_MEM;
1537
1538        return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1539                                        tco_res, 2, &spt_tco_platform_data,
1540                                        sizeof(spt_tco_platform_data));
1541}
1542
1543static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1544        .name = "Intel PCH",
1545        .version = 6,
1546};
1547
1548static struct platform_device *
1549i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1550                 struct resource *tco_res)
1551{
1552        return platform_device_register_resndata(&pci_dev->dev,
1553                        "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data,
1554                        sizeof(cnl_tco_platform_data));
1555}
1556
1557static void i801_add_tco(struct i801_priv *priv)
1558{
1559        struct pci_dev *pci_dev = priv->pci_dev;
1560        struct resource tco_res[2], *res;
1561        u32 tco_base, tco_ctl;
1562
1563        /* If we have ACPI based watchdog use that instead */
1564        if (acpi_has_watchdog())
1565                return;
1566
1567        if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1568                return;
1569
1570        pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1571        pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1572        if (!(tco_ctl & TCOCTL_EN))
1573                return;
1574
1575        memset(tco_res, 0, sizeof(tco_res));
1576        /*
1577         * Always populate the main iTCO IO resource here. The second entry
1578         * for NO_REBOOT MMIO is filled by the SPT specific function.
1579         */
1580        res = &tco_res[0];
1581        res->start = tco_base & ~1;
1582        res->end = res->start + 32 - 1;
1583        res->flags = IORESOURCE_IO;
1584
1585        if (priv->features & FEATURE_TCO_CNL)
1586                priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1587        else
1588                priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1589
1590        if (IS_ERR(priv->tco_pdev))
1591                dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1592}
1593
1594#ifdef CONFIG_ACPI
1595static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1596                                      acpi_physical_address address)
1597{
1598        return address >= priv->smba &&
1599               address <= pci_resource_end(priv->pci_dev, SMBBAR);
1600}
1601
1602static acpi_status
1603i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1604                     u64 *value, void *handler_context, void *region_context)
1605{
1606        struct i801_priv *priv = handler_context;
1607        struct pci_dev *pdev = priv->pci_dev;
1608        acpi_status status;
1609
1610        /*
1611         * Once BIOS AML code touches the OpRegion we warn and inhibit any
1612         * further access from the driver itself. This device is now owned
1613         * by the system firmware.
1614         */
1615        mutex_lock(&priv->acpi_lock);
1616
1617        if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1618                priv->acpi_reserved = true;
1619
1620                dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1621                dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1622
1623                /*
1624                 * BIOS is accessing the host controller so prevent it from
1625                 * suspending automatically from now on.
1626                 */
1627                pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1628        }
1629
1630        if ((function & ACPI_IO_MASK) == ACPI_READ)
1631                status = acpi_os_read_port(address, (u32 *)value, bits);
1632        else
1633                status = acpi_os_write_port(address, (u32)*value, bits);
1634
1635        mutex_unlock(&priv->acpi_lock);
1636
1637        return status;
1638}
1639
1640static int i801_acpi_probe(struct i801_priv *priv)
1641{
1642        struct acpi_device *adev;
1643        acpi_status status;
1644
1645        adev = ACPI_COMPANION(&priv->pci_dev->dev);
1646        if (adev) {
1647                status = acpi_install_address_space_handler(adev->handle,
1648                                ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1649                                NULL, priv);
1650                if (ACPI_SUCCESS(status))
1651                        return 0;
1652        }
1653
1654        return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1655}
1656
1657static void i801_acpi_remove(struct i801_priv *priv)
1658{
1659        struct acpi_device *adev;
1660
1661        adev = ACPI_COMPANION(&priv->pci_dev->dev);
1662        if (!adev)
1663                return;
1664
1665        acpi_remove_address_space_handler(adev->handle,
1666                ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1667}
1668#else
1669static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1670static inline void i801_acpi_remove(struct i801_priv *priv) { }
1671#endif
1672
1673static void i801_setup_hstcfg(struct i801_priv *priv)
1674{
1675        unsigned char hstcfg = priv->original_hstcfg;
1676
1677        hstcfg &= ~SMBHSTCFG_I2C_EN;    /* SMBus timing */
1678        hstcfg &= ~SMBHSTCNT_PEC_EN;    /* Disable software PEC */
1679        hstcfg |= SMBHSTCFG_HST_EN;
1680        pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg);
1681}
1682
1683static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1684{
1685        int err, i;
1686        struct i801_priv *priv;
1687
1688        priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1689        if (!priv)
1690                return -ENOMEM;
1691
1692        i2c_set_adapdata(&priv->adapter, priv);
1693        priv->adapter.owner = THIS_MODULE;
1694        priv->adapter.class = i801_get_adapter_class(priv);
1695        priv->adapter.algo = &smbus_algorithm;
1696        priv->adapter.dev.parent = &dev->dev;
1697        ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1698        priv->adapter.retries = 3;
1699        mutex_init(&priv->acpi_lock);
1700
1701        priv->pci_dev = dev;
1702        switch (dev->device) {
1703        case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1704        case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1705        case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1706        case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1707        case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1708        case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1709        case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS:
1710                priv->features |= FEATURE_BLOCK_PROC;
1711                priv->features |= FEATURE_I2C_BLOCK_READ;
1712                priv->features |= FEATURE_IRQ;
1713                priv->features |= FEATURE_SMBUS_PEC;
1714                priv->features |= FEATURE_BLOCK_BUFFER;
1715                priv->features |= FEATURE_TCO_SPT;
1716                priv->features |= FEATURE_HOST_NOTIFY;
1717                break;
1718
1719        case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1720        case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1721        case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1722        case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1723        case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1724        case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS:
1725        case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1726        case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1727        case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS:
1728        case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS:
1729        case PCI_DEVICE_ID_INTEL_EBG_SMBUS:
1730        case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS:
1731        case PCI_DEVICE_ID_INTEL_ALDER_LAKE_P_SMBUS:
1732        case PCI_DEVICE_ID_INTEL_ALDER_LAKE_M_SMBUS:
1733                priv->features |= FEATURE_BLOCK_PROC;
1734                priv->features |= FEATURE_I2C_BLOCK_READ;
1735                priv->features |= FEATURE_IRQ;
1736                priv->features |= FEATURE_SMBUS_PEC;
1737                priv->features |= FEATURE_BLOCK_BUFFER;
1738                priv->features |= FEATURE_TCO_CNL;
1739                priv->features |= FEATURE_HOST_NOTIFY;
1740                break;
1741
1742        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1743        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1744        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1745        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1746        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1747        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1748                priv->features |= FEATURE_IDF;
1749                fallthrough;
1750        default:
1751                priv->features |= FEATURE_BLOCK_PROC;
1752                priv->features |= FEATURE_I2C_BLOCK_READ;
1753                priv->features |= FEATURE_IRQ;
1754                fallthrough;
1755        case PCI_DEVICE_ID_INTEL_82801DB_3:
1756                priv->features |= FEATURE_SMBUS_PEC;
1757                priv->features |= FEATURE_BLOCK_BUFFER;
1758                fallthrough;
1759        case PCI_DEVICE_ID_INTEL_82801CA_3:
1760                priv->features |= FEATURE_HOST_NOTIFY;
1761                fallthrough;
1762        case PCI_DEVICE_ID_INTEL_82801BA_2:
1763        case PCI_DEVICE_ID_INTEL_82801AB_3:
1764        case PCI_DEVICE_ID_INTEL_82801AA_3:
1765                break;
1766        }
1767
1768        /* Disable features on user request */
1769        for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1770                if (priv->features & disable_features & (1 << i))
1771                        dev_notice(&dev->dev, "%s disabled by user\n",
1772                                   i801_feature_names[i]);
1773        }
1774        priv->features &= ~disable_features;
1775
1776        err = pcim_enable_device(dev);
1777        if (err) {
1778                dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1779                        err);
1780                return err;
1781        }
1782        pcim_pin_device(dev);
1783
1784        /* Determine the address of the SMBus area */
1785        priv->smba = pci_resource_start(dev, SMBBAR);
1786        if (!priv->smba) {
1787                dev_err(&dev->dev,
1788                        "SMBus base address uninitialized, upgrade BIOS\n");
1789                return -ENODEV;
1790        }
1791
1792        if (i801_acpi_probe(priv))
1793                return -ENODEV;
1794
1795        err = pcim_iomap_regions(dev, 1 << SMBBAR, DRV_NAME);
1796        if (err) {
1797                dev_err(&dev->dev,
1798                        "Failed to request SMBus region 0x%lx-0x%Lx\n",
1799                        priv->smba,
1800                        (unsigned long long)pci_resource_end(dev, SMBBAR));
1801                i801_acpi_remove(priv);
1802                return err;
1803        }
1804
1805        pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg);
1806        i801_setup_hstcfg(priv);
1807        if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN))
1808                dev_info(&dev->dev, "Enabling SMBus device\n");
1809
1810        if (priv->original_hstcfg & SMBHSTCFG_SMB_SMI_EN) {
1811                dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1812                /* Disable SMBus interrupt feature if SMBus using SMI# */
1813                priv->features &= ~FEATURE_IRQ;
1814        }
1815        if (priv->original_hstcfg & SMBHSTCFG_SPD_WD)
1816                dev_info(&dev->dev, "SPD Write Disable is set\n");
1817
1818        /* Clear special mode bits */
1819        if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1820                outb_p(inb_p(SMBAUXCTL(priv)) &
1821                       ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1822
1823        /* Remember original Host Notify setting */
1824        if (priv->features & FEATURE_HOST_NOTIFY)
1825                priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1826
1827        /* Default timeout in interrupt mode: 200 ms */
1828        priv->adapter.timeout = HZ / 5;
1829
1830        if (dev->irq == IRQ_NOTCONNECTED)
1831                priv->features &= ~FEATURE_IRQ;
1832
1833        if (priv->features & FEATURE_IRQ) {
1834                u16 pcictl, pcists;
1835
1836                /* Complain if an interrupt is already pending */
1837                pci_read_config_word(priv->pci_dev, PCI_STATUS, &pcists);
1838                if (pcists & PCI_STATUS_INTERRUPT)
1839                        dev_warn(&dev->dev, "An interrupt is pending!\n");
1840
1841                /* Check if interrupts have been disabled */
1842                pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pcictl);
1843                if (pcictl & PCI_COMMAND_INTX_DISABLE) {
1844                        dev_info(&dev->dev, "Interrupts are disabled\n");
1845                        priv->features &= ~FEATURE_IRQ;
1846                }
1847        }
1848
1849        if (priv->features & FEATURE_IRQ) {
1850                init_completion(&priv->done);
1851
1852                err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1853                                       IRQF_SHARED, DRV_NAME, priv);
1854                if (err) {
1855                        dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1856                                dev->irq, err);
1857                        priv->features &= ~FEATURE_IRQ;
1858                }
1859        }
1860        dev_info(&dev->dev, "SMBus using %s\n",
1861                 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1862
1863        i801_add_tco(priv);
1864
1865        snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1866                "SMBus I801 adapter at %04lx", priv->smba);
1867        err = i2c_add_adapter(&priv->adapter);
1868        if (err) {
1869                i801_acpi_remove(priv);
1870                return err;
1871        }
1872
1873        i801_enable_host_notify(&priv->adapter);
1874
1875        i801_probe_optional_slaves(priv);
1876        /* We ignore errors - multiplexing is optional */
1877        i801_add_mux(priv);
1878
1879        pci_set_drvdata(dev, priv);
1880
1881        dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
1882        pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1883        pm_runtime_use_autosuspend(&dev->dev);
1884        pm_runtime_put_autosuspend(&dev->dev);
1885        pm_runtime_allow(&dev->dev);
1886
1887        return 0;
1888}
1889
1890static void i801_remove(struct pci_dev *dev)
1891{
1892        struct i801_priv *priv = pci_get_drvdata(dev);
1893
1894        pm_runtime_forbid(&dev->dev);
1895        pm_runtime_get_noresume(&dev->dev);
1896
1897        i801_disable_host_notify(priv);
1898        i801_del_mux(priv);
1899        i2c_del_adapter(&priv->adapter);
1900        i801_acpi_remove(priv);
1901        pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1902
1903        platform_device_unregister(priv->tco_pdev);
1904
1905        /*
1906         * do not call pci_disable_device(dev) since it can cause hard hangs on
1907         * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1908         */
1909}
1910
1911static void i801_shutdown(struct pci_dev *dev)
1912{
1913        struct i801_priv *priv = pci_get_drvdata(dev);
1914
1915        /* Restore config registers to avoid hard hang on some systems */
1916        i801_disable_host_notify(priv);
1917        pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1918}
1919
1920#ifdef CONFIG_PM_SLEEP
1921static int i801_suspend(struct device *dev)
1922{
1923        struct i801_priv *priv = dev_get_drvdata(dev);
1924
1925        pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg);
1926        return 0;
1927}
1928
1929static int i801_resume(struct device *dev)
1930{
1931        struct i801_priv *priv = dev_get_drvdata(dev);
1932
1933        i801_setup_hstcfg(priv);
1934        i801_enable_host_notify(&priv->adapter);
1935
1936        return 0;
1937}
1938#endif
1939
1940static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1941
1942static struct pci_driver i801_driver = {
1943        .name           = DRV_NAME,
1944        .id_table       = i801_ids,
1945        .probe          = i801_probe,
1946        .remove         = i801_remove,
1947        .shutdown       = i801_shutdown,
1948        .driver         = {
1949                .pm     = &i801_pm_ops,
1950        },
1951};
1952
1953static int __init i2c_i801_init(void)
1954{
1955        if (dmi_name_in_vendors("FUJITSU"))
1956                input_apanel_init();
1957        return pci_register_driver(&i801_driver);
1958}
1959
1960static void __exit i2c_i801_exit(void)
1961{
1962        pci_unregister_driver(&i801_driver);
1963}
1964
1965MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>");
1966MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>");
1967MODULE_DESCRIPTION("I801 SMBus driver");
1968MODULE_LICENSE("GPL");
1969
1970module_init(i2c_i801_init);
1971module_exit(i2c_i801_exit);
1972