linux/drivers/i2c/busses/i2c-i801.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3    Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   4    Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   5    <mdsxyz123@yahoo.com>
   6    Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   7    Copyright (C) 2010         Intel Corporation,
   8                               David Woodhouse <dwmw2@infradead.org>
   9
  10*/
  11
  12/*
  13 * Supports the following Intel I/O Controller Hubs (ICH):
  14 *
  15 *                                      I/O                     Block   I2C
  16 *                                      region  SMBus   Block   proc.   block
  17 * Chip name                    PCI ID  size    PEC     buffer  call    read
  18 * ---------------------------------------------------------------------------
  19 * 82801AA (ICH)                0x2413  16      no      no      no      no
  20 * 82801AB (ICH0)               0x2423  16      no      no      no      no
  21 * 82801BA (ICH2)               0x2443  16      no      no      no      no
  22 * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  23 * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  24 * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  25 * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  26 * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  27 * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  28 * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  29 * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  30 * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  31 * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  32 * ICH10                        0x3a30  32      hard    yes     yes     yes
  33 * ICH10                        0x3a60  32      hard    yes     yes     yes
  34 * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  35 * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  36 * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  37 * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  38 * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  39 * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  40 * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  41 * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  42 * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  43 * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  44 * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  45 * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  46 * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  47 * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  48 * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  49 * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  50 * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  51 * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  52 * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  53 * Braswell (SOC)               0x2292  32      hard    yes     yes     yes
  54 * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  55 * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  56 * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  57 * Broxton (SOC)                0x5ad4  32      hard    yes     yes     yes
  58 * Lewisburg (PCH)              0xa1a3  32      hard    yes     yes     yes
  59 * Lewisburg Supersku (PCH)     0xa223  32      hard    yes     yes     yes
  60 * Kaby Lake PCH-H (PCH)        0xa2a3  32      hard    yes     yes     yes
  61 * Gemini Lake (SOC)            0x31d4  32      hard    yes     yes     yes
  62 * Cannon Lake-H (PCH)          0xa323  32      hard    yes     yes     yes
  63 * Cannon Lake-LP (PCH)         0x9da3  32      hard    yes     yes     yes
  64 * Cedar Fork (PCH)             0x18df  32      hard    yes     yes     yes
  65 * Ice Lake-LP (PCH)            0x34a3  32      hard    yes     yes     yes
  66 * Comet Lake (PCH)             0x02a3  32      hard    yes     yes     yes
  67 * Elkhart Lake (PCH)           0x4b23  32      hard    yes     yes     yes
  68 * Tiger Lake-LP (PCH)          0xa0a3  32      hard    yes     yes     yes
  69 *
  70 * Features supported by this driver:
  71 * Software PEC                         no
  72 * Hardware PEC                         yes
  73 * Block buffer                         yes
  74 * Block process call transaction       yes
  75 * I2C block read transaction           yes (doesn't use the block buffer)
  76 * Slave mode                           no
  77 * SMBus Host Notify                    yes
  78 * Interrupt processing                 yes
  79 *
  80 * See the file Documentation/i2c/busses/i2c-i801.rst for details.
  81 */
  82
  83#include <linux/interrupt.h>
  84#include <linux/module.h>
  85#include <linux/pci.h>
  86#include <linux/kernel.h>
  87#include <linux/stddef.h>
  88#include <linux/delay.h>
  89#include <linux/ioport.h>
  90#include <linux/init.h>
  91#include <linux/i2c.h>
  92#include <linux/i2c-smbus.h>
  93#include <linux/acpi.h>
  94#include <linux/io.h>
  95#include <linux/dmi.h>
  96#include <linux/slab.h>
  97#include <linux/string.h>
  98#include <linux/wait.h>
  99#include <linux/err.h>
 100#include <linux/platform_device.h>
 101#include <linux/platform_data/itco_wdt.h>
 102#include <linux/pm_runtime.h>
 103
 104#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 105#include <linux/gpio/machine.h>
 106#include <linux/platform_data/i2c-mux-gpio.h>
 107#endif
 108
 109/* I801 SMBus address offsets */
 110#define SMBHSTSTS(p)    (0 + (p)->smba)
 111#define SMBHSTCNT(p)    (2 + (p)->smba)
 112#define SMBHSTCMD(p)    (3 + (p)->smba)
 113#define SMBHSTADD(p)    (4 + (p)->smba)
 114#define SMBHSTDAT0(p)   (5 + (p)->smba)
 115#define SMBHSTDAT1(p)   (6 + (p)->smba)
 116#define SMBBLKDAT(p)    (7 + (p)->smba)
 117#define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 118#define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 119#define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 120#define SMBSLVSTS(p)    (16 + (p)->smba)        /* ICH3 and later */
 121#define SMBSLVCMD(p)    (17 + (p)->smba)        /* ICH3 and later */
 122#define SMBNTFDADD(p)   (20 + (p)->smba)        /* ICH3 and later */
 123
 124/* PCI Address Constants */
 125#define SMBBAR          4
 126#define SMBPCICTL       0x004
 127#define SMBPCISTS       0x006
 128#define SMBHSTCFG       0x040
 129#define TCOBASE         0x050
 130#define TCOCTL          0x054
 131
 132#define ACPIBASE                0x040
 133#define ACPIBASE_SMI_OFF        0x030
 134#define ACPICTRL                0x044
 135#define ACPICTRL_EN             0x080
 136
 137#define SBREG_BAR               0x10
 138#define SBREG_SMBCTRL           0xc6000c
 139#define SBREG_SMBCTRL_DNV       0xcf000c
 140
 141/* Host status bits for SMBPCISTS */
 142#define SMBPCISTS_INTS          BIT(3)
 143
 144/* Control bits for SMBPCICTL */
 145#define SMBPCICTL_INTDIS        BIT(10)
 146
 147/* Host configuration bits for SMBHSTCFG */
 148#define SMBHSTCFG_HST_EN        BIT(0)
 149#define SMBHSTCFG_SMB_SMI_EN    BIT(1)
 150#define SMBHSTCFG_I2C_EN        BIT(2)
 151#define SMBHSTCFG_SPD_WD        BIT(4)
 152
 153/* TCO configuration bits for TCOCTL */
 154#define TCOCTL_EN               BIT(8)
 155
 156/* Auxiliary status register bits, ICH4+ only */
 157#define SMBAUXSTS_CRCE          BIT(0)
 158#define SMBAUXSTS_STCO          BIT(1)
 159
 160/* Auxiliary control register bits, ICH4+ only */
 161#define SMBAUXCTL_CRC           BIT(0)
 162#define SMBAUXCTL_E32B          BIT(1)
 163
 164/* Other settings */
 165#define MAX_RETRIES             400
 166
 167/* I801 command constants */
 168#define I801_QUICK              0x00
 169#define I801_BYTE               0x04
 170#define I801_BYTE_DATA          0x08
 171#define I801_WORD_DATA          0x0C
 172#define I801_PROC_CALL          0x10    /* unimplemented */
 173#define I801_BLOCK_DATA         0x14
 174#define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 175#define I801_BLOCK_PROC_CALL    0x1C
 176
 177/* I801 Host Control register bits */
 178#define SMBHSTCNT_INTREN        BIT(0)
 179#define SMBHSTCNT_KILL          BIT(1)
 180#define SMBHSTCNT_LAST_BYTE     BIT(5)
 181#define SMBHSTCNT_START         BIT(6)
 182#define SMBHSTCNT_PEC_EN        BIT(7)  /* ICH3 and later */
 183
 184/* I801 Hosts Status register bits */
 185#define SMBHSTSTS_BYTE_DONE     BIT(7)
 186#define SMBHSTSTS_INUSE_STS     BIT(6)
 187#define SMBHSTSTS_SMBALERT_STS  BIT(5)
 188#define SMBHSTSTS_FAILED        BIT(4)
 189#define SMBHSTSTS_BUS_ERR       BIT(3)
 190#define SMBHSTSTS_DEV_ERR       BIT(2)
 191#define SMBHSTSTS_INTR          BIT(1)
 192#define SMBHSTSTS_HOST_BUSY     BIT(0)
 193
 194/* Host Notify Status register bits */
 195#define SMBSLVSTS_HST_NTFY_STS  BIT(0)
 196
 197/* Host Notify Command register bits */
 198#define SMBSLVCMD_HST_NTFY_INTREN       BIT(0)
 199
 200#define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 201                                 SMBHSTSTS_DEV_ERR)
 202
 203#define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 204                                 STATUS_ERROR_FLAGS)
 205
 206/* Older devices have their ID defined in <linux/pci_ids.h> */
 207#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS             0x02a3
 208#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 209#define PCI_DEVICE_ID_INTEL_CDF_SMBUS                   0x18df
 210#define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 211#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 212#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 213/* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 214#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 215#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 216#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 217#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 218#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 219#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 220#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 221#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 222#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS            0x31d4
 223#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS            0x34a3
 224#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 225#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS          0x4b23
 226#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS               0x5ad4
 227#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 228#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 229#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 230#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 231#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 232#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 233#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 234#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 235#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 236#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS         0x9da3
 237#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS          0xa0a3
 238#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 239#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS             0xa1a3
 240#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS        0xa223
 241#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS        0xa2a3
 242#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS          0xa323
 243
 244struct i801_mux_config {
 245        char *gpio_chip;
 246        unsigned values[3];
 247        int n_values;
 248        unsigned classes[3];
 249        unsigned gpios[2];              /* Relative to gpio_chip->base */
 250        int n_gpios;
 251};
 252
 253struct i801_priv {
 254        struct i2c_adapter adapter;
 255        unsigned long smba;
 256        unsigned char original_hstcfg;
 257        unsigned char original_slvcmd;
 258        struct pci_dev *pci_dev;
 259        unsigned int features;
 260
 261        /* isr processing */
 262        wait_queue_head_t waitq;
 263        u8 status;
 264
 265        /* Command state used by isr for byte-by-byte block transactions */
 266        u8 cmd;
 267        bool is_read;
 268        int count;
 269        int len;
 270        u8 *data;
 271
 272#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
 273        const struct i801_mux_config *mux_drvdata;
 274        struct platform_device *mux_pdev;
 275        struct gpiod_lookup_table *lookup;
 276#endif
 277        struct platform_device *tco_pdev;
 278
 279        /*
 280         * If set to true the host controller registers are reserved for
 281         * ACPI AML use. Protected by acpi_lock.
 282         */
 283        bool acpi_reserved;
 284        struct mutex acpi_lock;
 285};
 286
 287#define FEATURE_SMBUS_PEC       BIT(0)
 288#define FEATURE_BLOCK_BUFFER    BIT(1)
 289#define FEATURE_BLOCK_PROC      BIT(2)
 290#define FEATURE_I2C_BLOCK_READ  BIT(3)
 291#define FEATURE_IRQ             BIT(4)
 292#define FEATURE_HOST_NOTIFY     BIT(5)
 293/* Not really a feature, but it's convenient to handle it as such */
 294#define FEATURE_IDF             BIT(15)
 295#define FEATURE_TCO_SPT         BIT(16)
 296#define FEATURE_TCO_CNL         BIT(17)
 297
 298static const char *i801_feature_names[] = {
 299        "SMBus PEC",
 300        "Block buffer",
 301        "Block process call",
 302        "I2C block read",
 303        "Interrupt",
 304        "SMBus Host Notify",
 305};
 306
 307static unsigned int disable_features;
 308module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 309MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 310        "\t\t  0x01  disable SMBus PEC\n"
 311        "\t\t  0x02  disable the block buffer\n"
 312        "\t\t  0x08  disable the I2C block read functionality\n"
 313        "\t\t  0x10  don't use interrupts\n"
 314        "\t\t  0x20  disable SMBus Host Notify ");
 315
 316/* Make sure the SMBus host is ready to start transmitting.
 317   Return 0 if it is, -EBUSY if it is not. */
 318static int i801_check_pre(struct i801_priv *priv)
 319{
 320        int status;
 321
 322        status = inb_p(SMBHSTSTS(priv));
 323        if (status & SMBHSTSTS_HOST_BUSY) {
 324                dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 325                return -EBUSY;
 326        }
 327
 328        status &= STATUS_FLAGS;
 329        if (status) {
 330                dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 331                        status);
 332                outb_p(status, SMBHSTSTS(priv));
 333                status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 334                if (status) {
 335                        dev_err(&priv->pci_dev->dev,
 336                                "Failed clearing status flags (%02x)\n",
 337                                status);
 338                        return -EBUSY;
 339                }
 340        }
 341
 342        /*
 343         * Clear CRC status if needed.
 344         * During normal operation, i801_check_post() takes care
 345         * of it after every operation.  We do it here only in case
 346         * the hardware was already in this state when the driver
 347         * started.
 348         */
 349        if (priv->features & FEATURE_SMBUS_PEC) {
 350                status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 351                if (status) {
 352                        dev_dbg(&priv->pci_dev->dev,
 353                                "Clearing aux status flags (%02x)\n", status);
 354                        outb_p(status, SMBAUXSTS(priv));
 355                        status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE;
 356                        if (status) {
 357                                dev_err(&priv->pci_dev->dev,
 358                                        "Failed clearing aux status flags (%02x)\n",
 359                                        status);
 360                                return -EBUSY;
 361                        }
 362                }
 363        }
 364
 365        return 0;
 366}
 367
 368/*
 369 * Convert the status register to an error code, and clear it.
 370 * Note that status only contains the bits we want to clear, not the
 371 * actual register value.
 372 */
 373static int i801_check_post(struct i801_priv *priv, int status)
 374{
 375        int result = 0;
 376
 377        /*
 378         * If the SMBus is still busy, we give up
 379         * Note: This timeout condition only happens when using polling
 380         * transactions.  For interrupt operation, NAK/timeout is indicated by
 381         * DEV_ERR.
 382         */
 383        if (unlikely(status < 0)) {
 384                dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 385                /* try to stop the current command */
 386                dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 387                outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 388                       SMBHSTCNT(priv));
 389                usleep_range(1000, 2000);
 390                outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 391                       SMBHSTCNT(priv));
 392
 393                /* Check if it worked */
 394                status = inb_p(SMBHSTSTS(priv));
 395                if ((status & SMBHSTSTS_HOST_BUSY) ||
 396                    !(status & SMBHSTSTS_FAILED))
 397                        dev_err(&priv->pci_dev->dev,
 398                                "Failed terminating the transaction\n");
 399                outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 400                return -ETIMEDOUT;
 401        }
 402
 403        if (status & SMBHSTSTS_FAILED) {
 404                result = -EIO;
 405                dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 406        }
 407        if (status & SMBHSTSTS_DEV_ERR) {
 408                /*
 409                 * This may be a PEC error, check and clear it.
 410                 *
 411                 * AUXSTS is handled differently from HSTSTS.
 412                 * For HSTSTS, i801_isr() or i801_wait_intr()
 413                 * has already cleared the error bits in hardware,
 414                 * and we are passed a copy of the original value
 415                 * in "status".
 416                 * For AUXSTS, the hardware register is left
 417                 * for us to handle here.
 418                 * This is asymmetric, slightly iffy, but safe,
 419                 * since all this code is serialized and the CRCE
 420                 * bit is harmless as long as it's cleared before
 421                 * the next operation.
 422                 */
 423                if ((priv->features & FEATURE_SMBUS_PEC) &&
 424                    (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) {
 425                        outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv));
 426                        result = -EBADMSG;
 427                        dev_dbg(&priv->pci_dev->dev, "PEC error\n");
 428                } else {
 429                        result = -ENXIO;
 430                        dev_dbg(&priv->pci_dev->dev, "No response\n");
 431                }
 432        }
 433        if (status & SMBHSTSTS_BUS_ERR) {
 434                result = -EAGAIN;
 435                dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 436        }
 437
 438        /* Clear status flags except BYTE_DONE, to be cleared by caller */
 439        outb_p(status, SMBHSTSTS(priv));
 440
 441        return result;
 442}
 443
 444/* Wait for BUSY being cleared and either INTR or an error flag being set */
 445static int i801_wait_intr(struct i801_priv *priv)
 446{
 447        int timeout = 0;
 448        int status;
 449
 450        /* We will always wait for a fraction of a second! */
 451        do {
 452                usleep_range(250, 500);
 453                status = inb_p(SMBHSTSTS(priv));
 454        } while (((status & SMBHSTSTS_HOST_BUSY) ||
 455                  !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 456                 (timeout++ < MAX_RETRIES));
 457
 458        if (timeout > MAX_RETRIES) {
 459                dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 460                return -ETIMEDOUT;
 461        }
 462        return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 463}
 464
 465/* Wait for either BYTE_DONE or an error flag being set */
 466static int i801_wait_byte_done(struct i801_priv *priv)
 467{
 468        int timeout = 0;
 469        int status;
 470
 471        /* We will always wait for a fraction of a second! */
 472        do {
 473                usleep_range(250, 500);
 474                status = inb_p(SMBHSTSTS(priv));
 475        } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 476                 (timeout++ < MAX_RETRIES));
 477
 478        if (timeout > MAX_RETRIES) {
 479                dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 480                return -ETIMEDOUT;
 481        }
 482        return status & STATUS_ERROR_FLAGS;
 483}
 484
 485static int i801_transaction(struct i801_priv *priv, int xact)
 486{
 487        int status;
 488        int result;
 489        const struct i2c_adapter *adap = &priv->adapter;
 490
 491        result = i801_check_pre(priv);
 492        if (result < 0)
 493                return result;
 494
 495        if (priv->features & FEATURE_IRQ) {
 496                outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 497                       SMBHSTCNT(priv));
 498                result = wait_event_timeout(priv->waitq,
 499                                            (status = priv->status),
 500                                            adap->timeout);
 501                if (!result) {
 502                        status = -ETIMEDOUT;
 503                        dev_warn(&priv->pci_dev->dev,
 504                                 "Timeout waiting for interrupt!\n");
 505                }
 506                priv->status = 0;
 507                return i801_check_post(priv, status);
 508        }
 509
 510        /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 511         * SMBSCMD are passed in xact */
 512        outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 513
 514        status = i801_wait_intr(priv);
 515        return i801_check_post(priv, status);
 516}
 517
 518static int i801_block_transaction_by_block(struct i801_priv *priv,
 519                                           union i2c_smbus_data *data,
 520                                           char read_write, int command,
 521                                           int hwpec)
 522{
 523        int i, len;
 524        int status;
 525        int xact = hwpec ? SMBHSTCNT_PEC_EN : 0;
 526
 527        switch (command) {
 528        case I2C_SMBUS_BLOCK_PROC_CALL:
 529                xact |= I801_BLOCK_PROC_CALL;
 530                break;
 531        case I2C_SMBUS_BLOCK_DATA:
 532                xact |= I801_BLOCK_DATA;
 533                break;
 534        default:
 535                return -EOPNOTSUPP;
 536        }
 537
 538        inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 539
 540        /* Use 32-byte buffer to process this transaction */
 541        if (read_write == I2C_SMBUS_WRITE) {
 542                len = data->block[0];
 543                outb_p(len, SMBHSTDAT0(priv));
 544                for (i = 0; i < len; i++)
 545                        outb_p(data->block[i+1], SMBBLKDAT(priv));
 546        }
 547
 548        status = i801_transaction(priv, xact);
 549        if (status)
 550                return status;
 551
 552        if (read_write == I2C_SMBUS_READ ||
 553            command == I2C_SMBUS_BLOCK_PROC_CALL) {
 554                len = inb_p(SMBHSTDAT0(priv));
 555                if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 556                        return -EPROTO;
 557
 558                data->block[0] = len;
 559                for (i = 0; i < len; i++)
 560                        data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 561        }
 562        return 0;
 563}
 564
 565static void i801_isr_byte_done(struct i801_priv *priv)
 566{
 567        if (priv->is_read) {
 568                /* For SMBus block reads, length is received with first byte */
 569                if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 570                    (priv->count == 0)) {
 571                        priv->len = inb_p(SMBHSTDAT0(priv));
 572                        if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 573                                dev_err(&priv->pci_dev->dev,
 574                                        "Illegal SMBus block read size %d\n",
 575                                        priv->len);
 576                                /* FIXME: Recover */
 577                                priv->len = I2C_SMBUS_BLOCK_MAX;
 578                        } else {
 579                                dev_dbg(&priv->pci_dev->dev,
 580                                        "SMBus block read size is %d\n",
 581                                        priv->len);
 582                        }
 583                        priv->data[-1] = priv->len;
 584                }
 585
 586                /* Read next byte */
 587                if (priv->count < priv->len)
 588                        priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 589                else
 590                        dev_dbg(&priv->pci_dev->dev,
 591                                "Discarding extra byte on block read\n");
 592
 593                /* Set LAST_BYTE for last byte of read transaction */
 594                if (priv->count == priv->len - 1)
 595                        outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 596                               SMBHSTCNT(priv));
 597        } else if (priv->count < priv->len - 1) {
 598                /* Write next byte, except for IRQ after last byte */
 599                outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 600        }
 601
 602        /* Clear BYTE_DONE to continue with next byte */
 603        outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 604}
 605
 606static irqreturn_t i801_host_notify_isr(struct i801_priv *priv)
 607{
 608        unsigned short addr;
 609
 610        addr = inb_p(SMBNTFDADD(priv)) >> 1;
 611
 612        /*
 613         * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba)
 614         * always returns 0. Our current implementation doesn't provide
 615         * data, so we just ignore it.
 616         */
 617        i2c_handle_smbus_host_notify(&priv->adapter, addr);
 618
 619        /* clear Host Notify bit and return */
 620        outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
 621        return IRQ_HANDLED;
 622}
 623
 624/*
 625 * There are three kinds of interrupts:
 626 *
 627 * 1) i801 signals transaction completion with one of these interrupts:
 628 *      INTR - Success
 629 *      DEV_ERR - Invalid command, NAK or communication timeout
 630 *      BUS_ERR - SMI# transaction collision
 631 *      FAILED - transaction was canceled due to a KILL request
 632 *    When any of these occur, update ->status and wake up the waitq.
 633 *    ->status must be cleared before kicking off the next transaction.
 634 *
 635 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 636 *    occurs for each byte of a byte-by-byte to prepare the next byte.
 637 *
 638 * 3) Host Notify interrupts
 639 */
 640static irqreturn_t i801_isr(int irq, void *dev_id)
 641{
 642        struct i801_priv *priv = dev_id;
 643        u16 pcists;
 644        u8 status;
 645
 646        /* Confirm this is our interrupt */
 647        pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 648        if (!(pcists & SMBPCISTS_INTS))
 649                return IRQ_NONE;
 650
 651        if (priv->features & FEATURE_HOST_NOTIFY) {
 652                status = inb_p(SMBSLVSTS(priv));
 653                if (status & SMBSLVSTS_HST_NTFY_STS)
 654                        return i801_host_notify_isr(priv);
 655        }
 656
 657        status = inb_p(SMBHSTSTS(priv));
 658        if (status & SMBHSTSTS_BYTE_DONE)
 659                i801_isr_byte_done(priv);
 660
 661        /*
 662         * Clear irq sources and report transaction result.
 663         * ->status must be cleared before the next transaction is started.
 664         */
 665        status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 666        if (status) {
 667                outb_p(status, SMBHSTSTS(priv));
 668                priv->status = status;
 669                wake_up(&priv->waitq);
 670        }
 671
 672        return IRQ_HANDLED;
 673}
 674
 675/*
 676 * For "byte-by-byte" block transactions:
 677 *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 678 *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 679 */
 680static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 681                                               union i2c_smbus_data *data,
 682                                               char read_write, int command,
 683                                               int hwpec)
 684{
 685        int i, len;
 686        int smbcmd;
 687        int status;
 688        int result;
 689        const struct i2c_adapter *adap = &priv->adapter;
 690
 691        if (command == I2C_SMBUS_BLOCK_PROC_CALL)
 692                return -EOPNOTSUPP;
 693
 694        result = i801_check_pre(priv);
 695        if (result < 0)
 696                return result;
 697
 698        len = data->block[0];
 699
 700        if (read_write == I2C_SMBUS_WRITE) {
 701                outb_p(len, SMBHSTDAT0(priv));
 702                outb_p(data->block[1], SMBBLKDAT(priv));
 703        }
 704
 705        if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 706            read_write == I2C_SMBUS_READ)
 707                smbcmd = I801_I2C_BLOCK_DATA;
 708        else
 709                smbcmd = I801_BLOCK_DATA;
 710
 711        if (priv->features & FEATURE_IRQ) {
 712                priv->is_read = (read_write == I2C_SMBUS_READ);
 713                if (len == 1 && priv->is_read)
 714                        smbcmd |= SMBHSTCNT_LAST_BYTE;
 715                priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 716                priv->len = len;
 717                priv->count = 0;
 718                priv->data = &data->block[1];
 719
 720                outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 721                result = wait_event_timeout(priv->waitq,
 722                                            (status = priv->status),
 723                                            adap->timeout);
 724                if (!result) {
 725                        status = -ETIMEDOUT;
 726                        dev_warn(&priv->pci_dev->dev,
 727                                 "Timeout waiting for interrupt!\n");
 728                }
 729                priv->status = 0;
 730                return i801_check_post(priv, status);
 731        }
 732
 733        for (i = 1; i <= len; i++) {
 734                if (i == len && read_write == I2C_SMBUS_READ)
 735                        smbcmd |= SMBHSTCNT_LAST_BYTE;
 736                outb_p(smbcmd, SMBHSTCNT(priv));
 737
 738                if (i == 1)
 739                        outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 740                               SMBHSTCNT(priv));
 741
 742                status = i801_wait_byte_done(priv);
 743                if (status)
 744                        goto exit;
 745
 746                if (i == 1 && read_write == I2C_SMBUS_READ
 747                 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 748                        len = inb_p(SMBHSTDAT0(priv));
 749                        if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 750                                dev_err(&priv->pci_dev->dev,
 751                                        "Illegal SMBus block read size %d\n",
 752                                        len);
 753                                /* Recover */
 754                                while (inb_p(SMBHSTSTS(priv)) &
 755                                       SMBHSTSTS_HOST_BUSY)
 756                                        outb_p(SMBHSTSTS_BYTE_DONE,
 757                                               SMBHSTSTS(priv));
 758                                outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 759                                return -EPROTO;
 760                        }
 761                        data->block[0] = len;
 762                }
 763
 764                /* Retrieve/store value in SMBBLKDAT */
 765                if (read_write == I2C_SMBUS_READ)
 766                        data->block[i] = inb_p(SMBBLKDAT(priv));
 767                if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 768                        outb_p(data->block[i+1], SMBBLKDAT(priv));
 769
 770                /* signals SMBBLKDAT ready */
 771                outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 772        }
 773
 774        status = i801_wait_intr(priv);
 775exit:
 776        return i801_check_post(priv, status);
 777}
 778
 779static int i801_set_block_buffer_mode(struct i801_priv *priv)
 780{
 781        outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 782        if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 783                return -EIO;
 784        return 0;
 785}
 786
 787/* Block transaction function */
 788static int i801_block_transaction(struct i801_priv *priv,
 789                                  union i2c_smbus_data *data, char read_write,
 790                                  int command, int hwpec)
 791{
 792        int result = 0;
 793        unsigned char hostc;
 794
 795        if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 796                if (read_write == I2C_SMBUS_WRITE) {
 797                        /* set I2C_EN bit in configuration register */
 798                        pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 799                        pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 800                                              hostc | SMBHSTCFG_I2C_EN);
 801                } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 802                        dev_err(&priv->pci_dev->dev,
 803                                "I2C block read is unsupported!\n");
 804                        return -EOPNOTSUPP;
 805                }
 806        }
 807
 808        if (read_write == I2C_SMBUS_WRITE
 809         || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 810                if (data->block[0] < 1)
 811                        data->block[0] = 1;
 812                if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 813                        data->block[0] = I2C_SMBUS_BLOCK_MAX;
 814        } else {
 815                data->block[0] = 32;    /* max for SMBus block reads */
 816        }
 817
 818        /* Experience has shown that the block buffer can only be used for
 819           SMBus (not I2C) block transactions, even though the datasheet
 820           doesn't mention this limitation. */
 821        if ((priv->features & FEATURE_BLOCK_BUFFER)
 822         && command != I2C_SMBUS_I2C_BLOCK_DATA
 823         && i801_set_block_buffer_mode(priv) == 0)
 824                result = i801_block_transaction_by_block(priv, data,
 825                                                         read_write,
 826                                                         command, hwpec);
 827        else
 828                result = i801_block_transaction_byte_by_byte(priv, data,
 829                                                             read_write,
 830                                                             command, hwpec);
 831
 832        if (command == I2C_SMBUS_I2C_BLOCK_DATA
 833         && read_write == I2C_SMBUS_WRITE) {
 834                /* restore saved configuration register value */
 835                pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 836        }
 837        return result;
 838}
 839
 840/* Return negative errno on error. */
 841static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 842                       unsigned short flags, char read_write, u8 command,
 843                       int size, union i2c_smbus_data *data)
 844{
 845        int hwpec;
 846        int block = 0;
 847        int ret = 0, xact = 0;
 848        struct i801_priv *priv = i2c_get_adapdata(adap);
 849
 850        mutex_lock(&priv->acpi_lock);
 851        if (priv->acpi_reserved) {
 852                mutex_unlock(&priv->acpi_lock);
 853                return -EBUSY;
 854        }
 855
 856        pm_runtime_get_sync(&priv->pci_dev->dev);
 857
 858        hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 859                && size != I2C_SMBUS_QUICK
 860                && size != I2C_SMBUS_I2C_BLOCK_DATA;
 861
 862        switch (size) {
 863        case I2C_SMBUS_QUICK:
 864                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 865                       SMBHSTADD(priv));
 866                xact = I801_QUICK;
 867                break;
 868        case I2C_SMBUS_BYTE:
 869                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 870                       SMBHSTADD(priv));
 871                if (read_write == I2C_SMBUS_WRITE)
 872                        outb_p(command, SMBHSTCMD(priv));
 873                xact = I801_BYTE;
 874                break;
 875        case I2C_SMBUS_BYTE_DATA:
 876                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 877                       SMBHSTADD(priv));
 878                outb_p(command, SMBHSTCMD(priv));
 879                if (read_write == I2C_SMBUS_WRITE)
 880                        outb_p(data->byte, SMBHSTDAT0(priv));
 881                xact = I801_BYTE_DATA;
 882                break;
 883        case I2C_SMBUS_WORD_DATA:
 884                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 885                       SMBHSTADD(priv));
 886                outb_p(command, SMBHSTCMD(priv));
 887                if (read_write == I2C_SMBUS_WRITE) {
 888                        outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 889                        outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 890                }
 891                xact = I801_WORD_DATA;
 892                break;
 893        case I2C_SMBUS_BLOCK_DATA:
 894                outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 895                       SMBHSTADD(priv));
 896                outb_p(command, SMBHSTCMD(priv));
 897                block = 1;
 898                break;
 899        case I2C_SMBUS_I2C_BLOCK_DATA:
 900                /*
 901                 * NB: page 240 of ICH5 datasheet shows that the R/#W
 902                 * bit should be cleared here, even when reading.
 903                 * However if SPD Write Disable is set (Lynx Point and later),
 904                 * the read will fail if we don't set the R/#W bit.
 905                 */
 906                outb_p(((addr & 0x7f) << 1) |
 907                       ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ?
 908                        (read_write & 0x01) : 0),
 909                       SMBHSTADD(priv));
 910                if (read_write == I2C_SMBUS_READ) {
 911                        /* NB: page 240 of ICH5 datasheet also shows
 912                         * that DATA1 is the cmd field when reading */
 913                        outb_p(command, SMBHSTDAT1(priv));
 914                } else
 915                        outb_p(command, SMBHSTCMD(priv));
 916                block = 1;
 917                break;
 918        case I2C_SMBUS_BLOCK_PROC_CALL:
 919                /*
 920                 * Bit 0 of the slave address register always indicate a write
 921                 * command.
 922                 */
 923                outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 924                outb_p(command, SMBHSTCMD(priv));
 925                block = 1;
 926                break;
 927        default:
 928                dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 929                        size);
 930                ret = -EOPNOTSUPP;
 931                goto out;
 932        }
 933
 934        if (hwpec)      /* enable/disable hardware PEC */
 935                outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 936        else
 937                outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 938                       SMBAUXCTL(priv));
 939
 940        if (block)
 941                ret = i801_block_transaction(priv, data, read_write, size,
 942                                             hwpec);
 943        else
 944                ret = i801_transaction(priv, xact);
 945
 946        /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 947           time, so we forcibly disable it after every transaction. Turn off
 948           E32B for the same reason. */
 949        if (hwpec || block)
 950                outb_p(inb_p(SMBAUXCTL(priv)) &
 951                       ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 952
 953        if (block)
 954                goto out;
 955        if (ret)
 956                goto out;
 957        if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 958                goto out;
 959
 960        switch (xact & 0x7f) {
 961        case I801_BYTE: /* Result put in SMBHSTDAT0 */
 962        case I801_BYTE_DATA:
 963                data->byte = inb_p(SMBHSTDAT0(priv));
 964                break;
 965        case I801_WORD_DATA:
 966                data->word = inb_p(SMBHSTDAT0(priv)) +
 967                             (inb_p(SMBHSTDAT1(priv)) << 8);
 968                break;
 969        }
 970
 971out:
 972        pm_runtime_mark_last_busy(&priv->pci_dev->dev);
 973        pm_runtime_put_autosuspend(&priv->pci_dev->dev);
 974        mutex_unlock(&priv->acpi_lock);
 975        return ret;
 976}
 977
 978
 979static u32 i801_func(struct i2c_adapter *adapter)
 980{
 981        struct i801_priv *priv = i2c_get_adapdata(adapter);
 982
 983        return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 984               I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 985               I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 986               ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 987               ((priv->features & FEATURE_BLOCK_PROC) ?
 988                I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) |
 989               ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 990                I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) |
 991               ((priv->features & FEATURE_HOST_NOTIFY) ?
 992                I2C_FUNC_SMBUS_HOST_NOTIFY : 0);
 993}
 994
 995static void i801_enable_host_notify(struct i2c_adapter *adapter)
 996{
 997        struct i801_priv *priv = i2c_get_adapdata(adapter);
 998
 999        if (!(priv->features & FEATURE_HOST_NOTIFY))
1000                return;
1001
1002        if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd))
1003                outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd,
1004                       SMBSLVCMD(priv));
1005
1006        /* clear Host Notify bit to allow a new notification */
1007        outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv));
1008}
1009
1010static void i801_disable_host_notify(struct i801_priv *priv)
1011{
1012        if (!(priv->features & FEATURE_HOST_NOTIFY))
1013                return;
1014
1015        outb_p(priv->original_slvcmd, SMBSLVCMD(priv));
1016}
1017
1018static const struct i2c_algorithm smbus_algorithm = {
1019        .smbus_xfer     = i801_access,
1020        .functionality  = i801_func,
1021};
1022
1023static const struct pci_device_id i801_ids[] = {
1024        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
1025        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
1026        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
1027        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
1028        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
1029        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
1030        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
1031        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
1032        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
1033        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
1034        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
1035        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
1036        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
1037        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
1038        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
1039        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
1040        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
1041        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
1042        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
1043        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
1044        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
1045        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
1046        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
1047        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
1048        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
1049        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
1050        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
1051        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
1052        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
1053        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
1054        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
1055        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) },
1056        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
1057        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
1058        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
1059        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
1060        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
1061        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
1062        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) },
1063        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
1064        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) },
1065        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) },
1066        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) },
1067        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) },
1068        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) },
1069        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) },
1070        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) },
1071        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) },
1072        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) },
1073        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) },
1074        { 0, }
1075};
1076
1077MODULE_DEVICE_TABLE(pci, i801_ids);
1078
1079#if defined CONFIG_X86 && defined CONFIG_DMI
1080static unsigned char apanel_addr;
1081
1082/* Scan the system ROM for the signature "FJKEYINF" */
1083static __init const void __iomem *bios_signature(const void __iomem *bios)
1084{
1085        ssize_t offset;
1086        const unsigned char signature[] = "FJKEYINF";
1087
1088        for (offset = 0; offset < 0x10000; offset += 0x10) {
1089                if (check_signature(bios + offset, signature,
1090                                    sizeof(signature)-1))
1091                        return bios + offset;
1092        }
1093        return NULL;
1094}
1095
1096static void __init input_apanel_init(void)
1097{
1098        void __iomem *bios;
1099        const void __iomem *p;
1100
1101        bios = ioremap(0xF0000, 0x10000); /* Can't fail */
1102        p = bios_signature(bios);
1103        if (p) {
1104                /* just use the first address */
1105                apanel_addr = readb(p + 8 + 3) >> 1;
1106        }
1107        iounmap(bios);
1108}
1109
1110struct dmi_onboard_device_info {
1111        const char *name;
1112        u8 type;
1113        unsigned short i2c_addr;
1114        const char *i2c_type;
1115};
1116
1117static const struct dmi_onboard_device_info dmi_devices[] = {
1118        { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
1119        { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
1120        { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
1121};
1122
1123static void dmi_check_onboard_device(u8 type, const char *name,
1124                                     struct i2c_adapter *adap)
1125{
1126        int i;
1127        struct i2c_board_info info;
1128
1129        for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
1130                /* & ~0x80, ignore enabled/disabled bit */
1131                if ((type & ~0x80) != dmi_devices[i].type)
1132                        continue;
1133                if (strcasecmp(name, dmi_devices[i].name))
1134                        continue;
1135
1136                memset(&info, 0, sizeof(struct i2c_board_info));
1137                info.addr = dmi_devices[i].i2c_addr;
1138                strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
1139                i2c_new_device(adap, &info);
1140                break;
1141        }
1142}
1143
1144/* We use our own function to check for onboard devices instead of
1145   dmi_find_device() as some buggy BIOS's have the devices we are interested
1146   in marked as disabled */
1147static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
1148{
1149        int i, count;
1150
1151        if (dm->type != 10)
1152                return;
1153
1154        count = (dm->length - sizeof(struct dmi_header)) / 2;
1155        for (i = 0; i < count; i++) {
1156                const u8 *d = (char *)(dm + 1) + (i * 2);
1157                const char *name = ((char *) dm) + dm->length;
1158                u8 type = d[0];
1159                u8 s = d[1];
1160
1161                if (!s)
1162                        continue;
1163                s--;
1164                while (s > 0 && name[0]) {
1165                        name += strlen(name) + 1;
1166                        s--;
1167                }
1168                if (name[0] == 0) /* Bogus string reference */
1169                        continue;
1170
1171                dmi_check_onboard_device(type, name, adap);
1172        }
1173}
1174
1175/* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */
1176static const char *const acpi_smo8800_ids[] = {
1177        "SMO8800",
1178        "SMO8801",
1179        "SMO8810",
1180        "SMO8811",
1181        "SMO8820",
1182        "SMO8821",
1183        "SMO8830",
1184        "SMO8831",
1185};
1186
1187static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle,
1188                                             u32 nesting_level,
1189                                             void *context,
1190                                             void **return_value)
1191{
1192        struct acpi_device_info *info;
1193        acpi_status status;
1194        char *hid;
1195        int i;
1196
1197        status = acpi_get_object_info(obj_handle, &info);
1198        if (ACPI_FAILURE(status))
1199                return AE_OK;
1200
1201        if (!(info->valid & ACPI_VALID_HID))
1202                goto smo88xx_not_found;
1203
1204        hid = info->hardware_id.string;
1205        if (!hid)
1206                goto smo88xx_not_found;
1207
1208        i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid);
1209        if (i < 0)
1210                goto smo88xx_not_found;
1211
1212        kfree(info);
1213
1214        *((bool *)return_value) = true;
1215        return AE_CTRL_TERMINATE;
1216
1217smo88xx_not_found:
1218        kfree(info);
1219        return AE_OK;
1220}
1221
1222static bool is_dell_system_with_lis3lv02d(void)
1223{
1224        bool found;
1225        const char *vendor;
1226
1227        vendor = dmi_get_system_info(DMI_SYS_VENDOR);
1228        if (!vendor || strcmp(vendor, "Dell Inc."))
1229                return false;
1230
1231        /*
1232         * Check that ACPI device SMO88xx is present and is functioning.
1233         * Function acpi_get_devices() already filters all ACPI devices
1234         * which are not present or are not functioning.
1235         * ACPI device SMO88xx represents our ST microelectronics lis3lv02d
1236         * accelerometer but unfortunately ACPI does not provide any other
1237         * information (like I2C address).
1238         */
1239        found = false;
1240        acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL,
1241                         (void **)&found);
1242
1243        return found;
1244}
1245
1246/*
1247 * Accelerometer's I2C address is not specified in DMI nor ACPI,
1248 * so it is needed to define mapping table based on DMI product names.
1249 */
1250static const struct {
1251        const char *dmi_product_name;
1252        unsigned short i2c_addr;
1253} dell_lis3lv02d_devices[] = {
1254        /*
1255         * Dell platform team told us that these Latitude devices have
1256         * ST microelectronics accelerometer at I2C address 0x29.
1257         */
1258        { "Latitude E5250",     0x29 },
1259        { "Latitude E5450",     0x29 },
1260        { "Latitude E5550",     0x29 },
1261        { "Latitude E6440",     0x29 },
1262        { "Latitude E6440 ATG", 0x29 },
1263        { "Latitude E6540",     0x29 },
1264        /*
1265         * Additional individual entries were added after verification.
1266         */
1267        { "Vostro V131",        0x1d },
1268};
1269
1270static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv)
1271{
1272        struct i2c_board_info info;
1273        const char *dmi_product_name;
1274        int i;
1275
1276        dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME);
1277        for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) {
1278                if (strcmp(dmi_product_name,
1279                           dell_lis3lv02d_devices[i].dmi_product_name) == 0)
1280                        break;
1281        }
1282
1283        if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) {
1284                dev_warn(&priv->pci_dev->dev,
1285                         "Accelerometer lis3lv02d is present on SMBus but its"
1286                         " address is unknown, skipping registration\n");
1287                return;
1288        }
1289
1290        memset(&info, 0, sizeof(struct i2c_board_info));
1291        info.addr = dell_lis3lv02d_devices[i].i2c_addr;
1292        strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE);
1293        i2c_new_device(&priv->adapter, &info);
1294}
1295
1296/* Register optional slaves */
1297static void i801_probe_optional_slaves(struct i801_priv *priv)
1298{
1299        /* Only register slaves on main SMBus channel */
1300        if (priv->features & FEATURE_IDF)
1301                return;
1302
1303        if (apanel_addr) {
1304                struct i2c_board_info info;
1305
1306                memset(&info, 0, sizeof(struct i2c_board_info));
1307                info.addr = apanel_addr;
1308                strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
1309                i2c_new_device(&priv->adapter, &info);
1310        }
1311
1312        if (dmi_name_in_vendors("FUJITSU"))
1313                dmi_walk(dmi_check_onboard_devices, &priv->adapter);
1314
1315        if (is_dell_system_with_lis3lv02d())
1316                register_dell_lis3lv02d_i2c_device(priv);
1317}
1318#else
1319static void __init input_apanel_init(void) {}
1320static void i801_probe_optional_slaves(struct i801_priv *priv) {}
1321#endif  /* CONFIG_X86 && CONFIG_DMI */
1322
1323#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI
1324static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
1325        .gpio_chip = "gpio_ich",
1326        .values = { 0x02, 0x03 },
1327        .n_values = 2,
1328        .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1329        .gpios = { 52, 53 },
1330        .n_gpios = 2,
1331};
1332
1333static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1334        .gpio_chip = "gpio_ich",
1335        .values = { 0x02, 0x03, 0x01 },
1336        .n_values = 3,
1337        .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1338        .gpios = { 52, 53 },
1339        .n_gpios = 2,
1340};
1341
1342static const struct dmi_system_id mux_dmi_table[] = {
1343        {
1344                .matches = {
1345                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1346                        DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1347                },
1348                .driver_data = &i801_mux_config_asus_z8_d12,
1349        },
1350        {
1351                .matches = {
1352                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1353                        DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1354                },
1355                .driver_data = &i801_mux_config_asus_z8_d12,
1356        },
1357        {
1358                .matches = {
1359                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1360                        DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1361                },
1362                .driver_data = &i801_mux_config_asus_z8_d12,
1363        },
1364        {
1365                .matches = {
1366                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1367                        DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1368                },
1369                .driver_data = &i801_mux_config_asus_z8_d12,
1370        },
1371        {
1372                .matches = {
1373                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1374                        DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1375                },
1376                .driver_data = &i801_mux_config_asus_z8_d12,
1377        },
1378        {
1379                .matches = {
1380                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1381                        DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1382                },
1383                .driver_data = &i801_mux_config_asus_z8_d12,
1384        },
1385        {
1386                .matches = {
1387                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1388                        DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1389                },
1390                .driver_data = &i801_mux_config_asus_z8_d18,
1391        },
1392        {
1393                .matches = {
1394                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1395                        DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1396                },
1397                .driver_data = &i801_mux_config_asus_z8_d18,
1398        },
1399        {
1400                .matches = {
1401                        DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1402                        DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1403                },
1404                .driver_data = &i801_mux_config_asus_z8_d12,
1405        },
1406        { }
1407};
1408
1409/* Setup multiplexing if needed */
1410static int i801_add_mux(struct i801_priv *priv)
1411{
1412        struct device *dev = &priv->adapter.dev;
1413        const struct i801_mux_config *mux_config;
1414        struct i2c_mux_gpio_platform_data gpio_data;
1415        struct gpiod_lookup_table *lookup;
1416        int err, i;
1417
1418        if (!priv->mux_drvdata)
1419                return 0;
1420        mux_config = priv->mux_drvdata;
1421
1422        /* Prepare the platform data */
1423        memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1424        gpio_data.parent = priv->adapter.nr;
1425        gpio_data.values = mux_config->values;
1426        gpio_data.n_values = mux_config->n_values;
1427        gpio_data.classes = mux_config->classes;
1428        gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1429
1430        /* Register GPIO descriptor lookup table */
1431        lookup = devm_kzalloc(dev,
1432                              struct_size(lookup, table, mux_config->n_gpios),
1433                              GFP_KERNEL);
1434        if (!lookup)
1435                return -ENOMEM;
1436        lookup->dev_id = "i2c-mux-gpio";
1437        for (i = 0; i < mux_config->n_gpios; i++) {
1438                lookup->table[i].chip_label = mux_config->gpio_chip;
1439                lookup->table[i].chip_hwnum = mux_config->gpios[i];
1440                lookup->table[i].con_id = "mux";
1441        }
1442        gpiod_add_lookup_table(lookup);
1443        priv->lookup = lookup;
1444
1445        /*
1446         * Register the mux device, we use PLATFORM_DEVID_NONE here
1447         * because since we are referring to the GPIO chip by name we are
1448         * anyways in deep trouble if there is more than one of these
1449         * devices, and there should likely only be one platform controller
1450         * hub.
1451         */
1452        priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1453                                PLATFORM_DEVID_NONE, &gpio_data,
1454                                sizeof(struct i2c_mux_gpio_platform_data));
1455        if (IS_ERR(priv->mux_pdev)) {
1456                err = PTR_ERR(priv->mux_pdev);
1457                gpiod_remove_lookup_table(lookup);
1458                priv->mux_pdev = NULL;
1459                dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1460                return err;
1461        }
1462
1463        return 0;
1464}
1465
1466static void i801_del_mux(struct i801_priv *priv)
1467{
1468        if (priv->mux_pdev)
1469                platform_device_unregister(priv->mux_pdev);
1470        if (priv->lookup)
1471                gpiod_remove_lookup_table(priv->lookup);
1472}
1473
1474static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1475{
1476        const struct dmi_system_id *id;
1477        const struct i801_mux_config *mux_config;
1478        unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1479        int i;
1480
1481        id = dmi_first_match(mux_dmi_table);
1482        if (id) {
1483                /* Remove branch classes from trunk */
1484                mux_config = id->driver_data;
1485                for (i = 0; i < mux_config->n_values; i++)
1486                        class &= ~mux_config->classes[i];
1487
1488                /* Remember for later */
1489                priv->mux_drvdata = mux_config;
1490        }
1491
1492        return class;
1493}
1494#else
1495static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1496static inline void i801_del_mux(struct i801_priv *priv) { }
1497
1498static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1499{
1500        return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1501}
1502#endif
1503
1504static const struct itco_wdt_platform_data spt_tco_platform_data = {
1505        .name = "Intel PCH",
1506        .version = 4,
1507};
1508
1509static DEFINE_SPINLOCK(p2sb_spinlock);
1510
1511static struct platform_device *
1512i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev,
1513                 struct resource *tco_res)
1514{
1515        struct resource *res;
1516        unsigned int devfn;
1517        u64 base64_addr;
1518        u32 base_addr;
1519        u8 hidden;
1520
1521        /*
1522         * We must access the NO_REBOOT bit over the Primary to Sideband
1523         * bridge (P2SB). The BIOS prevents the P2SB device from being
1524         * enumerated by the PCI subsystem, so we need to unhide/hide it
1525         * to lookup the P2SB BAR.
1526         */
1527        spin_lock(&p2sb_spinlock);
1528
1529        devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1530
1531        /* Unhide the P2SB device, if it is hidden */
1532        pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden);
1533        if (hidden)
1534                pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1535
1536        pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1537        base64_addr = base_addr & 0xfffffff0;
1538
1539        pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1540        base64_addr |= (u64)base_addr << 32;
1541
1542        /* Hide the P2SB device, if it was hidden before */
1543        if (hidden)
1544                pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden);
1545        spin_unlock(&p2sb_spinlock);
1546
1547        res = &tco_res[ICH_RES_MEM_OFF];
1548        if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS)
1549                res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV;
1550        else
1551                res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1552
1553        res->end = res->start + 3;
1554        res->flags = IORESOURCE_MEM;
1555
1556        return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1557                                        tco_res, 3, &spt_tco_platform_data,
1558                                        sizeof(spt_tco_platform_data));
1559}
1560
1561static const struct itco_wdt_platform_data cnl_tco_platform_data = {
1562        .name = "Intel PCH",
1563        .version = 6,
1564};
1565
1566static struct platform_device *
1567i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev,
1568                 struct resource *tco_res)
1569{
1570        return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1571                                        tco_res, 2, &cnl_tco_platform_data,
1572                                        sizeof(cnl_tco_platform_data));
1573}
1574
1575static void i801_add_tco(struct i801_priv *priv)
1576{
1577        u32 base_addr, tco_base, tco_ctl, ctrl_val;
1578        struct pci_dev *pci_dev = priv->pci_dev;
1579        struct resource tco_res[3], *res;
1580        unsigned int devfn;
1581
1582        /* If we have ACPI based watchdog use that instead */
1583        if (acpi_has_watchdog())
1584                return;
1585
1586        if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL)))
1587                return;
1588
1589        pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1590        pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1591        if (!(tco_ctl & TCOCTL_EN))
1592                return;
1593
1594        memset(tco_res, 0, sizeof(tco_res));
1595
1596        res = &tco_res[ICH_RES_IO_TCO];
1597        res->start = tco_base & ~1;
1598        res->end = res->start + 32 - 1;
1599        res->flags = IORESOURCE_IO;
1600
1601        /*
1602         * Power Management registers.
1603         */
1604        devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1605        pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1606
1607        res = &tco_res[ICH_RES_IO_SMI];
1608        res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1609        res->end = res->start + 3;
1610        res->flags = IORESOURCE_IO;
1611
1612        /*
1613         * Enable the ACPI I/O space.
1614         */
1615        pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1616        ctrl_val |= ACPICTRL_EN;
1617        pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1618
1619        if (priv->features & FEATURE_TCO_CNL)
1620                priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res);
1621        else
1622                priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res);
1623
1624        if (IS_ERR(priv->tco_pdev))
1625                dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1626}
1627
1628#ifdef CONFIG_ACPI
1629static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv,
1630                                      acpi_physical_address address)
1631{
1632        return address >= priv->smba &&
1633               address <= pci_resource_end(priv->pci_dev, SMBBAR);
1634}
1635
1636static acpi_status
1637i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits,
1638                     u64 *value, void *handler_context, void *region_context)
1639{
1640        struct i801_priv *priv = handler_context;
1641        struct pci_dev *pdev = priv->pci_dev;
1642        acpi_status status;
1643
1644        /*
1645         * Once BIOS AML code touches the OpRegion we warn and inhibit any
1646         * further access from the driver itself. This device is now owned
1647         * by the system firmware.
1648         */
1649        mutex_lock(&priv->acpi_lock);
1650
1651        if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) {
1652                priv->acpi_reserved = true;
1653
1654                dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n");
1655                dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n");
1656
1657                /*
1658                 * BIOS is accessing the host controller so prevent it from
1659                 * suspending automatically from now on.
1660                 */
1661                pm_runtime_get_sync(&pdev->dev);
1662        }
1663
1664        if ((function & ACPI_IO_MASK) == ACPI_READ)
1665                status = acpi_os_read_port(address, (u32 *)value, bits);
1666        else
1667                status = acpi_os_write_port(address, (u32)*value, bits);
1668
1669        mutex_unlock(&priv->acpi_lock);
1670
1671        return status;
1672}
1673
1674static int i801_acpi_probe(struct i801_priv *priv)
1675{
1676        struct acpi_device *adev;
1677        acpi_status status;
1678
1679        adev = ACPI_COMPANION(&priv->pci_dev->dev);
1680        if (adev) {
1681                status = acpi_install_address_space_handler(adev->handle,
1682                                ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler,
1683                                NULL, priv);
1684                if (ACPI_SUCCESS(status))
1685                        return 0;
1686        }
1687
1688        return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]);
1689}
1690
1691static void i801_acpi_remove(struct i801_priv *priv)
1692{
1693        struct acpi_device *adev;
1694
1695        adev = ACPI_COMPANION(&priv->pci_dev->dev);
1696        if (!adev)
1697                return;
1698
1699        acpi_remove_address_space_handler(adev->handle,
1700                ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler);
1701
1702        mutex_lock(&priv->acpi_lock);
1703        if (priv->acpi_reserved)
1704                pm_runtime_put(&priv->pci_dev->dev);
1705        mutex_unlock(&priv->acpi_lock);
1706}
1707#else
1708static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; }
1709static inline void i801_acpi_remove(struct i801_priv *priv) { }
1710#endif
1711
1712static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1713{
1714        unsigned char temp;
1715        int err, i;
1716        struct i801_priv *priv;
1717
1718        priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1719        if (!priv)
1720                return -ENOMEM;
1721
1722        i2c_set_adapdata(&priv->adapter, priv);
1723        priv->adapter.owner = THIS_MODULE;
1724        priv->adapter.class = i801_get_adapter_class(priv);
1725        priv->adapter.algo = &smbus_algorithm;
1726        priv->adapter.dev.parent = &dev->dev;
1727        ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev));
1728        priv->adapter.retries = 3;
1729        mutex_init(&priv->acpi_lock);
1730
1731        priv->pci_dev = dev;
1732        switch (dev->device) {
1733        case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1734        case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1735        case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS:
1736        case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS:
1737        case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1738        case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS:
1739                priv->features |= FEATURE_BLOCK_PROC;
1740                priv->features |= FEATURE_I2C_BLOCK_READ;
1741                priv->features |= FEATURE_IRQ;
1742                priv->features |= FEATURE_SMBUS_PEC;
1743                priv->features |= FEATURE_BLOCK_BUFFER;
1744                priv->features |= FEATURE_TCO_SPT;
1745                priv->features |= FEATURE_HOST_NOTIFY;
1746                break;
1747
1748        case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS:
1749        case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS:
1750        case PCI_DEVICE_ID_INTEL_CDF_SMBUS:
1751        case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS:
1752        case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS:
1753        case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS:
1754        case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS:
1755                priv->features |= FEATURE_BLOCK_PROC;
1756                priv->features |= FEATURE_I2C_BLOCK_READ;
1757                priv->features |= FEATURE_IRQ;
1758                priv->features |= FEATURE_SMBUS_PEC;
1759                priv->features |= FEATURE_BLOCK_BUFFER;
1760                priv->features |= FEATURE_TCO_CNL;
1761                priv->features |= FEATURE_HOST_NOTIFY;
1762                break;
1763
1764        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1765        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1766        case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1767        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1768        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1769        case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1770                priv->features |= FEATURE_IDF;
1771                /* fall through */
1772        default:
1773                priv->features |= FEATURE_BLOCK_PROC;
1774                priv->features |= FEATURE_I2C_BLOCK_READ;
1775                priv->features |= FEATURE_IRQ;
1776                /* fall through */
1777        case PCI_DEVICE_ID_INTEL_82801DB_3:
1778                priv->features |= FEATURE_SMBUS_PEC;
1779                priv->features |= FEATURE_BLOCK_BUFFER;
1780                /* fall through */
1781        case PCI_DEVICE_ID_INTEL_82801CA_3:
1782                priv->features |= FEATURE_HOST_NOTIFY;
1783                /* fall through */
1784        case PCI_DEVICE_ID_INTEL_82801BA_2:
1785        case PCI_DEVICE_ID_INTEL_82801AB_3:
1786        case PCI_DEVICE_ID_INTEL_82801AA_3:
1787                break;
1788        }
1789
1790        /* Disable features on user request */
1791        for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1792                if (priv->features & disable_features & (1 << i))
1793                        dev_notice(&dev->dev, "%s disabled by user\n",
1794                                   i801_feature_names[i]);
1795        }
1796        priv->features &= ~disable_features;
1797
1798        err = pcim_enable_device(dev);
1799        if (err) {
1800                dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1801                        err);
1802                return err;
1803        }
1804        pcim_pin_device(dev);
1805
1806        /* Determine the address of the SMBus area */
1807        priv->smba = pci_resource_start(dev, SMBBAR);
1808        if (!priv->smba) {
1809                dev_err(&dev->dev,
1810                        "SMBus base address uninitialized, upgrade BIOS\n");
1811                return -ENODEV;
1812        }
1813
1814        if (i801_acpi_probe(priv))
1815                return -ENODEV;
1816
1817        err = pcim_iomap_regions(dev, 1 << SMBBAR,
1818                                 dev_driver_string(&dev->dev));
1819        if (err) {
1820                dev_err(&dev->dev,
1821                        "Failed to request SMBus region 0x%lx-0x%Lx\n",
1822                        priv->smba,
1823                        (unsigned long long)pci_resource_end(dev, SMBBAR));
1824                i801_acpi_remove(priv);
1825                return err;
1826        }
1827
1828        pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1829        priv->original_hstcfg = temp;
1830        temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1831        if (!(temp & SMBHSTCFG_HST_EN)) {
1832                dev_info(&dev->dev, "Enabling SMBus device\n");
1833                temp |= SMBHSTCFG_HST_EN;
1834        }
1835        pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1836
1837        if (temp & SMBHSTCFG_SMB_SMI_EN) {
1838                dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1839                /* Disable SMBus interrupt feature if SMBus using SMI# */
1840                priv->features &= ~FEATURE_IRQ;
1841        }
1842        if (temp & SMBHSTCFG_SPD_WD)
1843                dev_info(&dev->dev, "SPD Write Disable is set\n");
1844
1845        /* Clear special mode bits */
1846        if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1847                outb_p(inb_p(SMBAUXCTL(priv)) &
1848                       ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1849
1850        /* Remember original Host Notify setting */
1851        if (priv->features & FEATURE_HOST_NOTIFY)
1852                priv->original_slvcmd = inb_p(SMBSLVCMD(priv));
1853
1854        /* Default timeout in interrupt mode: 200 ms */
1855        priv->adapter.timeout = HZ / 5;
1856
1857        if (dev->irq == IRQ_NOTCONNECTED)
1858                priv->features &= ~FEATURE_IRQ;
1859
1860        if (priv->features & FEATURE_IRQ) {
1861                u16 pcictl, pcists;
1862
1863                /* Complain if an interrupt is already pending */
1864                pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1865                if (pcists & SMBPCISTS_INTS)
1866                        dev_warn(&dev->dev, "An interrupt is pending!\n");
1867
1868                /* Check if interrupts have been disabled */
1869                pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1870                if (pcictl & SMBPCICTL_INTDIS) {
1871                        dev_info(&dev->dev, "Interrupts are disabled\n");
1872                        priv->features &= ~FEATURE_IRQ;
1873                }
1874        }
1875
1876        if (priv->features & FEATURE_IRQ) {
1877                init_waitqueue_head(&priv->waitq);
1878
1879                err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1880                                       IRQF_SHARED,
1881                                       dev_driver_string(&dev->dev), priv);
1882                if (err) {
1883                        dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1884                                dev->irq, err);
1885                        priv->features &= ~FEATURE_IRQ;
1886                }
1887        }
1888        dev_info(&dev->dev, "SMBus using %s\n",
1889                 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1890
1891        i801_add_tco(priv);
1892
1893        snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1894                "SMBus I801 adapter at %04lx", priv->smba);
1895        err = i2c_add_adapter(&priv->adapter);
1896        if (err) {
1897                i801_acpi_remove(priv);
1898                return err;
1899        }
1900
1901        i801_enable_host_notify(&priv->adapter);
1902
1903        i801_probe_optional_slaves(priv);
1904        /* We ignore errors - multiplexing is optional */
1905        i801_add_mux(priv);
1906
1907        pci_set_drvdata(dev, priv);
1908
1909        pm_runtime_set_autosuspend_delay(&dev->dev, 1000);
1910        pm_runtime_use_autosuspend(&dev->dev);
1911        pm_runtime_put_autosuspend(&dev->dev);
1912        pm_runtime_allow(&dev->dev);
1913
1914        return 0;
1915}
1916
1917static void i801_remove(struct pci_dev *dev)
1918{
1919        struct i801_priv *priv = pci_get_drvdata(dev);
1920
1921        pm_runtime_forbid(&dev->dev);
1922        pm_runtime_get_noresume(&dev->dev);
1923
1924        i801_disable_host_notify(priv);
1925        i801_del_mux(priv);
1926        i2c_del_adapter(&priv->adapter);
1927        i801_acpi_remove(priv);
1928        pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1929
1930        platform_device_unregister(priv->tco_pdev);
1931
1932        /*
1933         * do not call pci_disable_device(dev) since it can cause hard hangs on
1934         * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1935         */
1936}
1937
1938static void i801_shutdown(struct pci_dev *dev)
1939{
1940        struct i801_priv *priv = pci_get_drvdata(dev);
1941
1942        /* Restore config registers to avoid hard hang on some systems */
1943        i801_disable_host_notify(priv);
1944        pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1945}
1946
1947#ifdef CONFIG_PM_SLEEP
1948static int i801_suspend(struct device *dev)
1949{
1950        struct pci_dev *pci_dev = to_pci_dev(dev);
1951        struct i801_priv *priv = pci_get_drvdata(pci_dev);
1952
1953        pci_write_config_byte(pci_dev, SMBHSTCFG, priv->original_hstcfg);
1954        return 0;
1955}
1956
1957static int i801_resume(struct device *dev)
1958{
1959        struct i801_priv *priv = dev_get_drvdata(dev);
1960
1961        i801_enable_host_notify(&priv->adapter);
1962
1963        return 0;
1964}
1965#endif
1966
1967static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume);
1968
1969static struct pci_driver i801_driver = {
1970        .name           = "i801_smbus",
1971        .id_table       = i801_ids,
1972        .probe          = i801_probe,
1973        .remove         = i801_remove,
1974        .shutdown       = i801_shutdown,
1975        .driver         = {
1976                .pm     = &i801_pm_ops,
1977        },
1978};
1979
1980static int __init i2c_i801_init(void)
1981{
1982        if (dmi_name_in_vendors("FUJITSU"))
1983                input_apanel_init();
1984        return pci_register_driver(&i801_driver);
1985}
1986
1987static void __exit i2c_i801_exit(void)
1988{
1989        pci_unregister_driver(&i801_driver);
1990}
1991
1992MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1993MODULE_DESCRIPTION("I801 SMBus driver");
1994MODULE_LICENSE("GPL");
1995
1996module_init(i2c_i801_init);
1997module_exit(i2c_i801_exit);
1998