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12#include <linux/kernel.h>
13#include <linux/slab.h>
14#include <linux/module.h>
15#include <linux/spinlock.h>
16#include <linux/i2c.h>
17#include <linux/interrupt.h>
18#include <linux/mv643xx_i2c.h>
19#include <linux/platform_device.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/pm_runtime.h>
22#include <linux/reset.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/of_device.h>
26#include <linux/of_irq.h>
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/delay.h>
30
31#define MV64XXX_I2C_ADDR_ADDR(val) ((val & 0x7f) << 1)
32#define MV64XXX_I2C_BAUD_DIV_N(val) (val & 0x7)
33#define MV64XXX_I2C_BAUD_DIV_M(val) ((val & 0xf) << 3)
34
35#define MV64XXX_I2C_REG_CONTROL_ACK BIT(2)
36#define MV64XXX_I2C_REG_CONTROL_IFLG BIT(3)
37#define MV64XXX_I2C_REG_CONTROL_STOP BIT(4)
38#define MV64XXX_I2C_REG_CONTROL_START BIT(5)
39#define MV64XXX_I2C_REG_CONTROL_TWSIEN BIT(6)
40#define MV64XXX_I2C_REG_CONTROL_INTEN BIT(7)
41
42
43#define MV64XXX_I2C_STATUS_BUS_ERR 0x00
44#define MV64XXX_I2C_STATUS_MAST_START 0x08
45#define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
46#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
47#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
48#define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
49#define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
50#define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
51#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
52#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
53#define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
54#define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
55#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
56#define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
57#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
58#define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
59#define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
60
61
62#define MV64XXX_I2C_REG_TX_DATA_LO 0xc0
63#define MV64XXX_I2C_REG_TX_DATA_HI 0xc4
64#define MV64XXX_I2C_REG_RX_DATA_LO 0xc8
65#define MV64XXX_I2C_REG_RX_DATA_HI 0xcc
66#define MV64XXX_I2C_REG_BRIDGE_CONTROL 0xd0
67#define MV64XXX_I2C_REG_BRIDGE_STATUS 0xd4
68#define MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE 0xd8
69#define MV64XXX_I2C_REG_BRIDGE_INTR_MASK 0xdC
70#define MV64XXX_I2C_REG_BRIDGE_TIMING 0xe0
71
72
73#define MV64XXX_I2C_BRIDGE_CONTROL_WR BIT(0)
74#define MV64XXX_I2C_BRIDGE_CONTROL_RD BIT(1)
75#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT 2
76#define MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT BIT(12)
77#define MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT 13
78#define MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT 16
79#define MV64XXX_I2C_BRIDGE_CONTROL_ENABLE BIT(19)
80#define MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START BIT(20)
81
82
83#define MV64XXX_I2C_BRIDGE_STATUS_ERROR BIT(0)
84
85
86enum {
87 MV64XXX_I2C_STATE_INVALID,
88 MV64XXX_I2C_STATE_IDLE,
89 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
90 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
91 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
92 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
93 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
94 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
95};
96
97
98enum {
99 MV64XXX_I2C_ACTION_INVALID,
100 MV64XXX_I2C_ACTION_CONTINUE,
101 MV64XXX_I2C_ACTION_SEND_RESTART,
102 MV64XXX_I2C_ACTION_SEND_ADDR_1,
103 MV64XXX_I2C_ACTION_SEND_ADDR_2,
104 MV64XXX_I2C_ACTION_SEND_DATA,
105 MV64XXX_I2C_ACTION_RCV_DATA,
106 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
107 MV64XXX_I2C_ACTION_SEND_STOP,
108};
109
110struct mv64xxx_i2c_regs {
111 u8 addr;
112 u8 ext_addr;
113 u8 data;
114 u8 control;
115 u8 status;
116 u8 clock;
117 u8 soft_reset;
118};
119
120struct mv64xxx_i2c_data {
121 struct i2c_msg *msgs;
122 int num_msgs;
123 int irq;
124 u32 state;
125 u32 action;
126 u32 aborting;
127 u32 cntl_bits;
128 void __iomem *reg_base;
129 struct mv64xxx_i2c_regs reg_offsets;
130 u32 addr1;
131 u32 addr2;
132 u32 bytes_left;
133 u32 byte_posn;
134 u32 send_stop;
135 u32 block;
136 int rc;
137 u32 freq_m;
138 u32 freq_n;
139 struct clk *clk;
140 struct clk *reg_clk;
141 wait_queue_head_t waitq;
142 spinlock_t lock;
143 struct i2c_msg *msg;
144 struct i2c_adapter adapter;
145 bool offload_enabled;
146
147 bool errata_delay;
148 struct reset_control *rstc;
149 bool irq_clear_inverted;
150
151 bool clk_n_base_0;
152 struct i2c_bus_recovery_info rinfo;
153};
154
155static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_mv64xxx = {
156 .addr = 0x00,
157 .ext_addr = 0x10,
158 .data = 0x04,
159 .control = 0x08,
160 .status = 0x0c,
161 .clock = 0x0c,
162 .soft_reset = 0x1c,
163};
164
165static struct mv64xxx_i2c_regs mv64xxx_i2c_regs_sun4i = {
166 .addr = 0x00,
167 .ext_addr = 0x04,
168 .data = 0x08,
169 .control = 0x0c,
170 .status = 0x10,
171 .clock = 0x14,
172 .soft_reset = 0x18,
173};
174
175static void
176mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
177 struct i2c_msg *msg)
178{
179 u32 dir = 0;
180
181 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
182 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
183
184 if (msg->flags & I2C_M_RD)
185 dir = 1;
186
187 if (msg->flags & I2C_M_TEN) {
188 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
189 drv_data->addr2 = (u32)msg->addr & 0xff;
190 } else {
191 drv_data->addr1 = MV64XXX_I2C_ADDR_ADDR((u32)msg->addr) | dir;
192 drv_data->addr2 = 0;
193 }
194}
195
196
197
198
199
200
201
202
203
204
205static void
206mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
207{
208 if (drv_data->offload_enabled) {
209 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
210 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_TIMING);
211 writel(0, drv_data->reg_base +
212 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
213 writel(0, drv_data->reg_base +
214 MV64XXX_I2C_REG_BRIDGE_INTR_MASK);
215 }
216
217 writel(0, drv_data->reg_base + drv_data->reg_offsets.soft_reset);
218 writel(MV64XXX_I2C_BAUD_DIV_M(drv_data->freq_m) | MV64XXX_I2C_BAUD_DIV_N(drv_data->freq_n),
219 drv_data->reg_base + drv_data->reg_offsets.clock);
220 writel(0, drv_data->reg_base + drv_data->reg_offsets.addr);
221 writel(0, drv_data->reg_base + drv_data->reg_offsets.ext_addr);
222 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
223 drv_data->reg_base + drv_data->reg_offsets.control);
224
225 if (drv_data->errata_delay)
226 udelay(5);
227
228 drv_data->state = MV64XXX_I2C_STATE_IDLE;
229}
230
231static void
232mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
233{
234
235
236
237
238
239 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
240 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
241 return;
242 }
243
244
245 switch (status) {
246
247 case MV64XXX_I2C_STATUS_MAST_START:
248 case MV64XXX_I2C_STATUS_MAST_REPEAT_START:
249 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
250 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
251 break;
252
253
254 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK:
255 if (drv_data->msg->flags & I2C_M_TEN) {
256 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
257 drv_data->state =
258 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
259 break;
260 }
261 fallthrough;
262 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK:
263 case MV64XXX_I2C_STATUS_MAST_WR_ACK:
264 if ((drv_data->bytes_left == 0)
265 || (drv_data->aborting
266 && (drv_data->byte_posn != 0))) {
267 if (drv_data->send_stop || drv_data->aborting) {
268 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
269 drv_data->state = MV64XXX_I2C_STATE_IDLE;
270 } else {
271 drv_data->action =
272 MV64XXX_I2C_ACTION_SEND_RESTART;
273 drv_data->state =
274 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
275 }
276 } else {
277 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
278 drv_data->state =
279 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
280 drv_data->bytes_left--;
281 }
282 break;
283
284
285 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK:
286 if (drv_data->msg->flags & I2C_M_TEN) {
287 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
288 drv_data->state =
289 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
290 break;
291 }
292 fallthrough;
293 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK:
294 if (drv_data->bytes_left == 0) {
295 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
296 drv_data->state = MV64XXX_I2C_STATE_IDLE;
297 break;
298 }
299 fallthrough;
300 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK:
301 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
302 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
303 else {
304 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
305 drv_data->bytes_left--;
306 }
307 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
308
309 if ((drv_data->bytes_left == 1) || drv_data->aborting)
310 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
311 break;
312
313 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK:
314 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
315 drv_data->state = MV64XXX_I2C_STATE_IDLE;
316 break;
317
318 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK:
319 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK:
320 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK:
321
322 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
323 drv_data->state = MV64XXX_I2C_STATE_IDLE;
324 drv_data->rc = -ENXIO;
325 break;
326
327 default:
328 dev_err(&drv_data->adapter.dev,
329 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
330 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
331 drv_data->state, status, drv_data->msg->addr,
332 drv_data->msg->flags);
333 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
334 mv64xxx_i2c_hw_init(drv_data);
335 i2c_recover_bus(&drv_data->adapter);
336 drv_data->rc = -EAGAIN;
337 }
338}
339
340static void mv64xxx_i2c_send_start(struct mv64xxx_i2c_data *drv_data)
341{
342 drv_data->msg = drv_data->msgs;
343 drv_data->byte_posn = 0;
344 drv_data->bytes_left = drv_data->msg->len;
345 drv_data->aborting = 0;
346 drv_data->rc = 0;
347
348 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
349 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
350 drv_data->reg_base + drv_data->reg_offsets.control);
351}
352
353static void
354mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
355{
356 switch(drv_data->action) {
357 case MV64XXX_I2C_ACTION_SEND_RESTART:
358
359 BUG_ON(drv_data->num_msgs == 0);
360
361 drv_data->msgs++;
362 drv_data->num_msgs--;
363 mv64xxx_i2c_send_start(drv_data);
364
365 if (drv_data->errata_delay)
366 udelay(5);
367
368
369
370
371
372
373 drv_data->send_stop = drv_data->num_msgs == 1;
374 break;
375
376 case MV64XXX_I2C_ACTION_CONTINUE:
377 writel(drv_data->cntl_bits,
378 drv_data->reg_base + drv_data->reg_offsets.control);
379 break;
380
381 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
382 writel(drv_data->addr1,
383 drv_data->reg_base + drv_data->reg_offsets.data);
384 writel(drv_data->cntl_bits,
385 drv_data->reg_base + drv_data->reg_offsets.control);
386 break;
387
388 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
389 writel(drv_data->addr2,
390 drv_data->reg_base + drv_data->reg_offsets.data);
391 writel(drv_data->cntl_bits,
392 drv_data->reg_base + drv_data->reg_offsets.control);
393 break;
394
395 case MV64XXX_I2C_ACTION_SEND_DATA:
396 writel(drv_data->msg->buf[drv_data->byte_posn++],
397 drv_data->reg_base + drv_data->reg_offsets.data);
398 writel(drv_data->cntl_bits,
399 drv_data->reg_base + drv_data->reg_offsets.control);
400 break;
401
402 case MV64XXX_I2C_ACTION_RCV_DATA:
403 drv_data->msg->buf[drv_data->byte_posn++] =
404 readl(drv_data->reg_base + drv_data->reg_offsets.data);
405 writel(drv_data->cntl_bits,
406 drv_data->reg_base + drv_data->reg_offsets.control);
407 break;
408
409 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
410 drv_data->msg->buf[drv_data->byte_posn++] =
411 readl(drv_data->reg_base + drv_data->reg_offsets.data);
412 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
413 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
414 drv_data->reg_base + drv_data->reg_offsets.control);
415 drv_data->block = 0;
416 if (drv_data->errata_delay)
417 udelay(5);
418
419 wake_up(&drv_data->waitq);
420 break;
421
422 case MV64XXX_I2C_ACTION_INVALID:
423 default:
424 dev_err(&drv_data->adapter.dev,
425 "mv64xxx_i2c_do_action: Invalid action: %d\n",
426 drv_data->action);
427 drv_data->rc = -EIO;
428 fallthrough;
429 case MV64XXX_I2C_ACTION_SEND_STOP:
430 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
431 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
432 drv_data->reg_base + drv_data->reg_offsets.control);
433 drv_data->block = 0;
434 wake_up(&drv_data->waitq);
435 break;
436 }
437}
438
439static void
440mv64xxx_i2c_read_offload_rx_data(struct mv64xxx_i2c_data *drv_data,
441 struct i2c_msg *msg)
442{
443 u32 buf[2];
444
445 buf[0] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_LO);
446 buf[1] = readl(drv_data->reg_base + MV64XXX_I2C_REG_RX_DATA_HI);
447
448 memcpy(msg->buf, buf, msg->len);
449}
450
451static int
452mv64xxx_i2c_intr_offload(struct mv64xxx_i2c_data *drv_data)
453{
454 u32 cause, status;
455
456 cause = readl(drv_data->reg_base +
457 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
458 if (!cause)
459 return IRQ_NONE;
460
461 status = readl(drv_data->reg_base +
462 MV64XXX_I2C_REG_BRIDGE_STATUS);
463
464 if (status & MV64XXX_I2C_BRIDGE_STATUS_ERROR) {
465 drv_data->rc = -EIO;
466 goto out;
467 }
468
469 drv_data->rc = 0;
470
471
472
473
474
475 if (drv_data->num_msgs == 1 && drv_data->msgs[0].flags & I2C_M_RD) {
476 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs);
477 drv_data->msgs++;
478 drv_data->num_msgs--;
479 }
480
481
482
483
484 else if (drv_data->num_msgs == 2 &&
485 !(drv_data->msgs[0].flags & I2C_M_RD) &&
486 drv_data->msgs[1].flags & I2C_M_RD) {
487 mv64xxx_i2c_read_offload_rx_data(drv_data, drv_data->msgs + 1);
488 drv_data->msgs += 2;
489 drv_data->num_msgs -= 2;
490 }
491
492out:
493 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
494 writel(0, drv_data->reg_base +
495 MV64XXX_I2C_REG_BRIDGE_INTR_CAUSE);
496 drv_data->block = 0;
497
498 wake_up(&drv_data->waitq);
499
500 return IRQ_HANDLED;
501}
502
503static irqreturn_t
504mv64xxx_i2c_intr(int irq, void *dev_id)
505{
506 struct mv64xxx_i2c_data *drv_data = dev_id;
507 u32 status;
508 irqreturn_t rc = IRQ_NONE;
509
510 spin_lock(&drv_data->lock);
511
512 if (drv_data->offload_enabled)
513 rc = mv64xxx_i2c_intr_offload(drv_data);
514
515 while (readl(drv_data->reg_base + drv_data->reg_offsets.control) &
516 MV64XXX_I2C_REG_CONTROL_IFLG) {
517 status = readl(drv_data->reg_base + drv_data->reg_offsets.status);
518 mv64xxx_i2c_fsm(drv_data, status);
519 mv64xxx_i2c_do_action(drv_data);
520
521 if (drv_data->irq_clear_inverted)
522 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_IFLG,
523 drv_data->reg_base + drv_data->reg_offsets.control);
524
525 rc = IRQ_HANDLED;
526 }
527 spin_unlock(&drv_data->lock);
528
529 return rc;
530}
531
532
533
534
535
536
537
538
539static void
540mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
541{
542 long time_left;
543 unsigned long flags;
544 char abort = 0;
545
546 time_left = wait_event_timeout(drv_data->waitq,
547 !drv_data->block, drv_data->adapter.timeout);
548
549 spin_lock_irqsave(&drv_data->lock, flags);
550 if (!time_left) {
551 drv_data->rc = -ETIMEDOUT;
552 abort = 1;
553 } else if (time_left < 0) {
554 drv_data->rc = time_left;
555 abort = 1;
556 }
557
558 if (abort && drv_data->block) {
559 drv_data->aborting = 1;
560 spin_unlock_irqrestore(&drv_data->lock, flags);
561
562 time_left = wait_event_timeout(drv_data->waitq,
563 !drv_data->block, drv_data->adapter.timeout);
564
565 if ((time_left <= 0) && drv_data->block) {
566 drv_data->state = MV64XXX_I2C_STATE_IDLE;
567 dev_err(&drv_data->adapter.dev,
568 "mv64xxx: I2C bus locked, block: %d, "
569 "time_left: %d\n", drv_data->block,
570 (int)time_left);
571 mv64xxx_i2c_hw_init(drv_data);
572 i2c_recover_bus(&drv_data->adapter);
573 }
574 } else
575 spin_unlock_irqrestore(&drv_data->lock, flags);
576}
577
578static int
579mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
580 int is_last)
581{
582 unsigned long flags;
583
584 spin_lock_irqsave(&drv_data->lock, flags);
585
586 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
587
588 drv_data->send_stop = is_last;
589 drv_data->block = 1;
590 mv64xxx_i2c_send_start(drv_data);
591 spin_unlock_irqrestore(&drv_data->lock, flags);
592
593 mv64xxx_i2c_wait_for_completion(drv_data);
594 return drv_data->rc;
595}
596
597static void
598mv64xxx_i2c_prepare_tx(struct mv64xxx_i2c_data *drv_data)
599{
600 struct i2c_msg *msg = drv_data->msgs;
601 u32 buf[2];
602
603 memcpy(buf, msg->buf, msg->len);
604
605 writel(buf[0], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_LO);
606 writel(buf[1], drv_data->reg_base + MV64XXX_I2C_REG_TX_DATA_HI);
607}
608
609static int
610mv64xxx_i2c_offload_xfer(struct mv64xxx_i2c_data *drv_data)
611{
612 struct i2c_msg *msgs = drv_data->msgs;
613 int num = drv_data->num_msgs;
614 unsigned long ctrl_reg;
615 unsigned long flags;
616
617 spin_lock_irqsave(&drv_data->lock, flags);
618
619
620 ctrl_reg = MV64XXX_I2C_BRIDGE_CONTROL_ENABLE |
621 (msgs[0].addr << MV64XXX_I2C_BRIDGE_CONTROL_ADDR_SHIFT);
622
623 if (msgs[0].flags & I2C_M_TEN)
624 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_ADDR_EXT;
625
626
627 if (num == 1 && !(msgs[0].flags & I2C_M_RD)) {
628 size_t len = msgs[0].len - 1;
629
630 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_WR |
631 (len << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT);
632 mv64xxx_i2c_prepare_tx(drv_data);
633 }
634
635 else if (num == 1 && msgs[0].flags & I2C_M_RD) {
636 size_t len = msgs[0].len - 1;
637
638 ctrl_reg |= MV64XXX_I2C_BRIDGE_CONTROL_RD |
639 (len << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT);
640 }
641
642
643
644
645 else if (num == 2) {
646 size_t lentx = msgs[0].len - 1;
647 size_t lenrx = msgs[1].len - 1;
648
649 ctrl_reg |=
650 MV64XXX_I2C_BRIDGE_CONTROL_RD |
651 MV64XXX_I2C_BRIDGE_CONTROL_WR |
652 (lentx << MV64XXX_I2C_BRIDGE_CONTROL_TX_SIZE_SHIFT) |
653 (lenrx << MV64XXX_I2C_BRIDGE_CONTROL_RX_SIZE_SHIFT) |
654 MV64XXX_I2C_BRIDGE_CONTROL_REPEATED_START;
655 mv64xxx_i2c_prepare_tx(drv_data);
656 }
657
658
659 drv_data->block = 1;
660 writel(ctrl_reg, drv_data->reg_base + MV64XXX_I2C_REG_BRIDGE_CONTROL);
661 spin_unlock_irqrestore(&drv_data->lock, flags);
662
663 mv64xxx_i2c_wait_for_completion(drv_data);
664
665 return drv_data->rc;
666}
667
668static bool
669mv64xxx_i2c_valid_offload_sz(struct i2c_msg *msg)
670{
671 return msg->len <= 8 && msg->len >= 1;
672}
673
674static bool
675mv64xxx_i2c_can_offload(struct mv64xxx_i2c_data *drv_data)
676{
677 struct i2c_msg *msgs = drv_data->msgs;
678 int num = drv_data->num_msgs;
679
680 if (!drv_data->offload_enabled)
681 return false;
682
683
684
685
686
687
688 if (num == 1 && mv64xxx_i2c_valid_offload_sz(msgs))
689 return true;
690
691
692
693
694
695
696 if (num == 2 &&
697 mv64xxx_i2c_valid_offload_sz(msgs) &&
698 mv64xxx_i2c_valid_offload_sz(msgs + 1) &&
699 !(msgs[0].flags & I2C_M_RD) &&
700 msgs[1].flags & I2C_M_RD)
701 return true;
702
703 return false;
704}
705
706
707
708
709
710
711
712
713static u32
714mv64xxx_i2c_functionality(struct i2c_adapter *adap)
715{
716 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
717}
718
719static int
720mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
721{
722 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
723 int rc, ret = num;
724
725 rc = pm_runtime_resume_and_get(&adap->dev);
726 if (rc)
727 return rc;
728
729 BUG_ON(drv_data->msgs != NULL);
730 drv_data->msgs = msgs;
731 drv_data->num_msgs = num;
732
733 if (mv64xxx_i2c_can_offload(drv_data))
734 rc = mv64xxx_i2c_offload_xfer(drv_data);
735 else
736 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
737
738 if (rc < 0)
739 ret = rc;
740
741 drv_data->num_msgs = 0;
742 drv_data->msgs = NULL;
743
744 pm_runtime_mark_last_busy(&adap->dev);
745 pm_runtime_put_autosuspend(&adap->dev);
746
747 return ret;
748}
749
750static const struct i2c_algorithm mv64xxx_i2c_algo = {
751 .master_xfer = mv64xxx_i2c_xfer,
752 .functionality = mv64xxx_i2c_functionality,
753};
754
755
756
757
758
759
760
761
762static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
763 { .compatible = "allwinner,sun4i-a10-i2c", .data = &mv64xxx_i2c_regs_sun4i},
764 { .compatible = "allwinner,sun6i-a31-i2c", .data = &mv64xxx_i2c_regs_sun4i},
765 { .compatible = "marvell,mv64xxx-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
766 { .compatible = "marvell,mv78230-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
767 { .compatible = "marvell,mv78230-a0-i2c", .data = &mv64xxx_i2c_regs_mv64xxx},
768 {}
769};
770MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
771
772#ifdef CONFIG_OF
773static int
774mv64xxx_calc_freq(struct mv64xxx_i2c_data *drv_data,
775 const int tclk, const int n, const int m)
776{
777 if (drv_data->clk_n_base_0)
778 return tclk / (10 * (m + 1) * (1 << n));
779 else
780 return tclk / (10 * (m + 1) * (2 << n));
781}
782
783static bool
784mv64xxx_find_baud_factors(struct mv64xxx_i2c_data *drv_data,
785 const u32 req_freq, const u32 tclk)
786{
787 int freq, delta, best_delta = INT_MAX;
788 int m, n;
789
790 for (n = 0; n <= 7; n++)
791 for (m = 0; m <= 15; m++) {
792 freq = mv64xxx_calc_freq(drv_data, tclk, n, m);
793 delta = req_freq - freq;
794 if (delta >= 0 && delta < best_delta) {
795 drv_data->freq_m = m;
796 drv_data->freq_n = n;
797 best_delta = delta;
798 }
799 if (best_delta == 0)
800 return true;
801 }
802 if (best_delta == INT_MAX)
803 return false;
804 return true;
805}
806
807static int
808mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
809 struct device *dev)
810{
811 const struct of_device_id *device;
812 struct device_node *np = dev->of_node;
813 u32 bus_freq, tclk;
814 int rc = 0;
815
816
817
818
819
820 if (!drv_data->clk) {
821 rc = -ENODEV;
822 goto out;
823 }
824 tclk = clk_get_rate(drv_data->clk);
825
826 if (of_property_read_u32(np, "clock-frequency", &bus_freq))
827 bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
828
829 if (of_device_is_compatible(np, "allwinner,sun4i-a10-i2c") ||
830 of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
831 drv_data->clk_n_base_0 = true;
832
833 if (!mv64xxx_find_baud_factors(drv_data, bus_freq, tclk)) {
834 rc = -EINVAL;
835 goto out;
836 }
837
838 drv_data->rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
839 if (IS_ERR(drv_data->rstc)) {
840 rc = PTR_ERR(drv_data->rstc);
841 goto out;
842 }
843
844
845
846
847 drv_data->adapter.timeout = HZ;
848
849 device = of_match_device(mv64xxx_i2c_of_match_table, dev);
850 if (!device)
851 return -ENODEV;
852
853 memcpy(&drv_data->reg_offsets, device->data, sizeof(drv_data->reg_offsets));
854
855
856
857
858
859 if (of_device_is_compatible(np, "marvell,mv78230-i2c")) {
860 drv_data->offload_enabled = true;
861
862 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
863 drv_data->errata_delay = true;
864 }
865
866 if (of_device_is_compatible(np, "marvell,mv78230-a0-i2c")) {
867 drv_data->offload_enabled = false;
868
869 if (bus_freq <= I2C_MAX_STANDARD_MODE_FREQ)
870 drv_data->errata_delay = true;
871 }
872
873 if (of_device_is_compatible(np, "allwinner,sun6i-a31-i2c"))
874 drv_data->irq_clear_inverted = true;
875
876out:
877 return rc;
878}
879#else
880static int
881mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
882 struct device *dev)
883{
884 return -ENODEV;
885}
886#endif
887
888static int mv64xxx_i2c_init_recovery_info(struct mv64xxx_i2c_data *drv_data,
889 struct device *dev)
890{
891 struct i2c_bus_recovery_info *rinfo = &drv_data->rinfo;
892
893 rinfo->pinctrl = devm_pinctrl_get(dev);
894 if (IS_ERR(rinfo->pinctrl)) {
895 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
896 return -EPROBE_DEFER;
897 dev_info(dev, "can't get pinctrl, bus recovery not supported\n");
898 return PTR_ERR(rinfo->pinctrl);
899 } else if (!rinfo->pinctrl) {
900 return -ENODEV;
901 }
902
903 drv_data->adapter.bus_recovery_info = rinfo;
904 return 0;
905}
906
907static int
908mv64xxx_i2c_runtime_suspend(struct device *dev)
909{
910 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
911
912 reset_control_assert(drv_data->rstc);
913 clk_disable_unprepare(drv_data->reg_clk);
914 clk_disable_unprepare(drv_data->clk);
915
916 return 0;
917}
918
919static int
920mv64xxx_i2c_runtime_resume(struct device *dev)
921{
922 struct mv64xxx_i2c_data *drv_data = dev_get_drvdata(dev);
923
924 clk_prepare_enable(drv_data->clk);
925 clk_prepare_enable(drv_data->reg_clk);
926 reset_control_reset(drv_data->rstc);
927
928 mv64xxx_i2c_hw_init(drv_data);
929
930 return 0;
931}
932
933static int
934mv64xxx_i2c_probe(struct platform_device *pd)
935{
936 struct mv64xxx_i2c_data *drv_data;
937 struct mv64xxx_i2c_pdata *pdata = dev_get_platdata(&pd->dev);
938 int rc;
939
940 if ((!pdata && !pd->dev.of_node))
941 return -ENODEV;
942
943 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
944 GFP_KERNEL);
945 if (!drv_data)
946 return -ENOMEM;
947
948 drv_data->reg_base = devm_platform_ioremap_resource(pd, 0);
949 if (IS_ERR(drv_data->reg_base))
950 return PTR_ERR(drv_data->reg_base);
951
952 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
953 sizeof(drv_data->adapter.name));
954
955 init_waitqueue_head(&drv_data->waitq);
956 spin_lock_init(&drv_data->lock);
957
958
959 drv_data->clk = devm_clk_get(&pd->dev, NULL);
960 if (IS_ERR(drv_data->clk)) {
961 if (PTR_ERR(drv_data->clk) == -EPROBE_DEFER)
962 return -EPROBE_DEFER;
963 drv_data->clk = NULL;
964 }
965
966 drv_data->reg_clk = devm_clk_get(&pd->dev, "reg");
967 if (IS_ERR(drv_data->reg_clk)) {
968 if (PTR_ERR(drv_data->reg_clk) == -EPROBE_DEFER)
969 return -EPROBE_DEFER;
970 drv_data->reg_clk = NULL;
971 }
972
973 drv_data->irq = platform_get_irq(pd, 0);
974 if (drv_data->irq < 0)
975 return drv_data->irq;
976
977 if (pdata) {
978 drv_data->freq_m = pdata->freq_m;
979 drv_data->freq_n = pdata->freq_n;
980 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
981 drv_data->offload_enabled = false;
982 memcpy(&drv_data->reg_offsets, &mv64xxx_i2c_regs_mv64xxx, sizeof(drv_data->reg_offsets));
983 } else if (pd->dev.of_node) {
984 rc = mv64xxx_of_config(drv_data, &pd->dev);
985 if (rc)
986 return rc;
987 }
988
989 rc = mv64xxx_i2c_init_recovery_info(drv_data, &pd->dev);
990 if (rc == -EPROBE_DEFER)
991 return rc;
992
993 drv_data->adapter.dev.parent = &pd->dev;
994 drv_data->adapter.algo = &mv64xxx_i2c_algo;
995 drv_data->adapter.owner = THIS_MODULE;
996 drv_data->adapter.class = I2C_CLASS_DEPRECATED;
997 drv_data->adapter.nr = pd->id;
998 drv_data->adapter.dev.of_node = pd->dev.of_node;
999 platform_set_drvdata(pd, drv_data);
1000 i2c_set_adapdata(&drv_data->adapter, drv_data);
1001
1002 pm_runtime_set_autosuspend_delay(&pd->dev, MSEC_PER_SEC);
1003 pm_runtime_use_autosuspend(&pd->dev);
1004 pm_runtime_enable(&pd->dev);
1005 if (!pm_runtime_enabled(&pd->dev)) {
1006 rc = mv64xxx_i2c_runtime_resume(&pd->dev);
1007 if (rc)
1008 goto exit_disable_pm;
1009 }
1010
1011 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
1012 MV64XXX_I2C_CTLR_NAME, drv_data);
1013 if (rc) {
1014 dev_err(&drv_data->adapter.dev,
1015 "mv64xxx: Can't register intr handler irq%d: %d\n",
1016 drv_data->irq, rc);
1017 goto exit_disable_pm;
1018 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
1019 dev_err(&drv_data->adapter.dev,
1020 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
1021 goto exit_free_irq;
1022 }
1023
1024 return 0;
1025
1026exit_free_irq:
1027 free_irq(drv_data->irq, drv_data);
1028exit_disable_pm:
1029 pm_runtime_disable(&pd->dev);
1030 if (!pm_runtime_status_suspended(&pd->dev))
1031 mv64xxx_i2c_runtime_suspend(&pd->dev);
1032
1033 return rc;
1034}
1035
1036static int
1037mv64xxx_i2c_remove(struct platform_device *pd)
1038{
1039 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(pd);
1040
1041 i2c_del_adapter(&drv_data->adapter);
1042 free_irq(drv_data->irq, drv_data);
1043 pm_runtime_disable(&pd->dev);
1044 if (!pm_runtime_status_suspended(&pd->dev))
1045 mv64xxx_i2c_runtime_suspend(&pd->dev);
1046
1047 return 0;
1048}
1049
1050static void
1051mv64xxx_i2c_shutdown(struct platform_device *pd)
1052{
1053 pm_runtime_disable(&pd->dev);
1054 if (!pm_runtime_status_suspended(&pd->dev))
1055 mv64xxx_i2c_runtime_suspend(&pd->dev);
1056}
1057
1058static const struct dev_pm_ops mv64xxx_i2c_pm_ops = {
1059 SET_RUNTIME_PM_OPS(mv64xxx_i2c_runtime_suspend,
1060 mv64xxx_i2c_runtime_resume, NULL)
1061 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1062 pm_runtime_force_resume)
1063};
1064
1065static struct platform_driver mv64xxx_i2c_driver = {
1066 .probe = mv64xxx_i2c_probe,
1067 .remove = mv64xxx_i2c_remove,
1068 .shutdown = mv64xxx_i2c_shutdown,
1069 .driver = {
1070 .name = MV64XXX_I2C_CTLR_NAME,
1071 .pm = &mv64xxx_i2c_pm_ops,
1072 .of_match_table = mv64xxx_i2c_of_match_table,
1073 },
1074};
1075
1076module_platform_driver(mv64xxx_i2c_driver);
1077
1078MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
1079MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
1080MODULE_LICENSE("GPL");
1081
