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24#include <linux/module.h>
25#include <linux/moduleparam.h>
26#include <linux/pci.h>
27#include <linux/kernel.h>
28#include <linux/delay.h>
29#include <linux/stddef.h>
30#include <linux/ioport.h>
31#include <linux/i2c.h>
32#include <linux/slab.h>
33#include <linux/dmi.h>
34#include <linux/acpi.h>
35#include <linux/io.h>
36
37
38
39#define SMBHSTSTS (0 + piix4_smba)
40#define SMBHSLVSTS (1 + piix4_smba)
41#define SMBHSTCNT (2 + piix4_smba)
42#define SMBHSTCMD (3 + piix4_smba)
43#define SMBHSTADD (4 + piix4_smba)
44#define SMBHSTDAT0 (5 + piix4_smba)
45#define SMBHSTDAT1 (6 + piix4_smba)
46#define SMBBLKDAT (7 + piix4_smba)
47#define SMBSLVCNT (8 + piix4_smba)
48#define SMBSHDWCMD (9 + piix4_smba)
49#define SMBSLVEVT (0xA + piix4_smba)
50#define SMBSLVDAT (0xC + piix4_smba)
51
52
53#define SMBIOSIZE 9
54
55
56#define SMBBA 0x090
57#define SMBHSTCFG 0x0D2
58#define SMBSLVC 0x0D3
59#define SMBSHDW1 0x0D4
60#define SMBSHDW2 0x0D5
61#define SMBREV 0x0D6
62
63
64#define MAX_TIMEOUT 500
65#define ENABLE_INT9 0
66
67
68#define PIIX4_QUICK 0x00
69#define PIIX4_BYTE 0x04
70#define PIIX4_BYTE_DATA 0x08
71#define PIIX4_WORD_DATA 0x0C
72#define PIIX4_BLOCK_DATA 0x14
73
74
75#define PIIX4_MAX_ADAPTERS 4
76#define HUDSON2_MAIN_PORTS 2
77
78
79#define SB800_PIIX4_SMB_IDX 0xcd6
80
81#define KERNCZ_IMC_IDX 0x3e
82#define KERNCZ_IMC_DATA 0x3f
83
84
85
86
87
88
89#define SB800_PIIX4_PORT_IDX 0x2c
90#define SB800_PIIX4_PORT_IDX_ALT 0x2e
91#define SB800_PIIX4_PORT_IDX_SEL 0x2f
92#define SB800_PIIX4_PORT_IDX_MASK 0x06
93#define SB800_PIIX4_PORT_IDX_SHIFT 1
94
95
96#define SB800_PIIX4_PORT_IDX_KERNCZ 0x02
97#define SB800_PIIX4_PORT_IDX_MASK_KERNCZ 0x18
98#define SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ 3
99
100
101
102
103
104static int force;
105module_param (force, int, 0);
106MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
107
108
109
110static int force_addr;
111module_param_hw(force_addr, int, ioport, 0);
112MODULE_PARM_DESC(force_addr,
113 "Forcibly enable the PIIX4 at the given address. "
114 "EXTREMELY DANGEROUS!");
115
116static int srvrworks_csb5_delay;
117static struct pci_driver piix4_driver;
118
119static const struct dmi_system_id piix4_dmi_blacklist[] = {
120 {
121 .ident = "Sapphire AM2RD790",
122 .matches = {
123 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
124 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
125 },
126 },
127 {
128 .ident = "DFI Lanparty UT 790FX",
129 .matches = {
130 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
131 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
132 },
133 },
134 { }
135};
136
137
138
139static const struct dmi_system_id piix4_dmi_ibm[] = {
140 {
141 .ident = "IBM",
142 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
143 },
144 { },
145};
146
147
148
149
150static u8 piix4_port_sel_sb800;
151static u8 piix4_port_mask_sb800;
152static u8 piix4_port_shift_sb800;
153static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = {
154 " port 0", " port 2", " port 3", " port 4"
155};
156static const char *piix4_aux_port_name_sb800 = " port 1";
157
158struct i2c_piix4_adapdata {
159 unsigned short smba;
160
161
162 bool sb800_main;
163 bool notify_imc;
164 u8 port;
165};
166
167static int piix4_setup(struct pci_dev *PIIX4_dev,
168 const struct pci_device_id *id)
169{
170 unsigned char temp;
171 unsigned short piix4_smba;
172
173 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
174 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
175 srvrworks_csb5_delay = 1;
176
177
178
179 if (dmi_check_system(piix4_dmi_blacklist)) {
180 dev_err(&PIIX4_dev->dev,
181 "Accessing the SMBus on this system is unsafe!\n");
182 return -EPERM;
183 }
184
185
186 if (dmi_check_system(piix4_dmi_ibm) &&
187 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
188 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
189 "may corrupt your serial eeprom! Refusing to load "
190 "module!\n");
191 return -EPERM;
192 }
193
194
195 if (force_addr) {
196 piix4_smba = force_addr & 0xfff0;
197 force = 0;
198 } else {
199 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
200 piix4_smba &= 0xfff0;
201 if(piix4_smba == 0) {
202 dev_err(&PIIX4_dev->dev, "SMBus base address "
203 "uninitialized - upgrade BIOS or use "
204 "force_addr=0xaddr\n");
205 return -ENODEV;
206 }
207 }
208
209 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
210 return -ENODEV;
211
212 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
213 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
214 piix4_smba);
215 return -EBUSY;
216 }
217
218 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
219
220
221
222 if (force_addr) {
223 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
224 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
225 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
226 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
227 "new address %04x!\n", piix4_smba);
228 } else if ((temp & 1) == 0) {
229 if (force) {
230
231
232
233
234
235
236
237
238 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
239 temp | 1);
240 dev_notice(&PIIX4_dev->dev,
241 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n");
242 } else {
243 dev_err(&PIIX4_dev->dev,
244 "SMBus Host Controller not enabled!\n");
245 release_region(piix4_smba, SMBIOSIZE);
246 return -ENODEV;
247 }
248 }
249
250 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
251 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
252 else if ((temp & 0x0E) == 0)
253 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
254 else
255 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
256 "(or code out of date)!\n");
257
258 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
259 dev_info(&PIIX4_dev->dev,
260 "SMBus Host Controller at 0x%x, revision %d\n",
261 piix4_smba, temp);
262
263 return piix4_smba;
264}
265
266static int piix4_setup_sb800(struct pci_dev *PIIX4_dev,
267 const struct pci_device_id *id, u8 aux)
268{
269 unsigned short piix4_smba;
270 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel;
271 u8 i2ccfg, i2ccfg_offset = 0x10;
272
273
274 if (force || force_addr) {
275 dev_err(&PIIX4_dev->dev, "SMBus does not support "
276 "forcing address!\n");
277 return -EINVAL;
278 }
279
280
281 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
282 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
283 PIIX4_dev->revision >= 0x41) ||
284 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD &&
285 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS &&
286 PIIX4_dev->revision >= 0x49) ||
287 (PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON &&
288 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS))
289 smb_en = 0x00;
290 else
291 smb_en = (aux) ? 0x28 : 0x2c;
292
293 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb")) {
294 dev_err(&PIIX4_dev->dev,
295 "SMB base address index region 0x%x already in use.\n",
296 SB800_PIIX4_SMB_IDX);
297 return -EBUSY;
298 }
299
300 outb_p(smb_en, SB800_PIIX4_SMB_IDX);
301 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
302 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX);
303 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1);
304
305 release_region(SB800_PIIX4_SMB_IDX, 2);
306
307 if (!smb_en) {
308 smb_en_status = smba_en_lo & 0x10;
309 piix4_smba = smba_en_hi << 8;
310 if (aux)
311 piix4_smba |= 0x20;
312 } else {
313 smb_en_status = smba_en_lo & 0x01;
314 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
315 }
316
317 if (!smb_en_status) {
318 dev_err(&PIIX4_dev->dev,
319 "SMBus Host Controller not enabled!\n");
320 return -ENODEV;
321 }
322
323 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
324 return -ENODEV;
325
326 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
327 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
328 piix4_smba);
329 return -EBUSY;
330 }
331
332
333 if (aux) {
334 dev_info(&PIIX4_dev->dev,
335 "Auxiliary SMBus Host Controller at 0x%x\n",
336 piix4_smba);
337 return piix4_smba;
338 }
339
340
341 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
342 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
343 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
344 release_region(piix4_smba, SMBIOSIZE);
345 return -EBUSY;
346 }
347 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
348 release_region(piix4_smba + i2ccfg_offset, 1);
349
350 if (i2ccfg & 1)
351 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n");
352 else
353 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n");
354
355 dev_info(&PIIX4_dev->dev,
356 "SMBus Host Controller at 0x%x, revision %d\n",
357 piix4_smba, i2ccfg >> 4);
358
359
360 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD ||
361 PIIX4_dev->vendor == PCI_VENDOR_ID_HYGON) {
362 if (PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
363 (PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
364 PIIX4_dev->revision >= 0x1F)) {
365 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_KERNCZ;
366 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK_KERNCZ;
367 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT_KERNCZ;
368 } else {
369 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT;
370 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
371 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
372 }
373 } else {
374 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2,
375 "sb800_piix4_smb")) {
376 release_region(piix4_smba, SMBIOSIZE);
377 return -EBUSY;
378 }
379
380 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX);
381 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1);
382 piix4_port_sel_sb800 = (port_sel & 0x01) ?
383 SB800_PIIX4_PORT_IDX_ALT :
384 SB800_PIIX4_PORT_IDX;
385 piix4_port_mask_sb800 = SB800_PIIX4_PORT_IDX_MASK;
386 piix4_port_shift_sb800 = SB800_PIIX4_PORT_IDX_SHIFT;
387 release_region(SB800_PIIX4_SMB_IDX, 2);
388 }
389
390 dev_info(&PIIX4_dev->dev,
391 "Using register 0x%02x for SMBus port selection\n",
392 (unsigned int)piix4_port_sel_sb800);
393
394 return piix4_smba;
395}
396
397static int piix4_setup_aux(struct pci_dev *PIIX4_dev,
398 const struct pci_device_id *id,
399 unsigned short base_reg_addr)
400{
401
402
403
404 unsigned short piix4_smba;
405
406
407 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
408 if ((piix4_smba & 1) == 0) {
409 dev_dbg(&PIIX4_dev->dev,
410 "Auxiliary SMBus controller not enabled\n");
411 return -ENODEV;
412 }
413
414 piix4_smba &= 0xfff0;
415 if (piix4_smba == 0) {
416 dev_dbg(&PIIX4_dev->dev,
417 "Auxiliary SMBus base address uninitialized\n");
418 return -ENODEV;
419 }
420
421 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
422 return -ENODEV;
423
424 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
425 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
426 "already in use!\n", piix4_smba);
427 return -EBUSY;
428 }
429
430 dev_info(&PIIX4_dev->dev,
431 "Auxiliary SMBus Host Controller at 0x%x\n",
432 piix4_smba);
433
434 return piix4_smba;
435}
436
437static int piix4_transaction(struct i2c_adapter *piix4_adapter)
438{
439 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
440 unsigned short piix4_smba = adapdata->smba;
441 int temp;
442 int result = 0;
443 int timeout = 0;
444
445 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
446 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
447 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
448 inb_p(SMBHSTDAT1));
449
450
451 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
452 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
453 "Resetting...\n", temp);
454 outb_p(temp, SMBHSTSTS);
455 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
456 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
457 return -EBUSY;
458 } else {
459 dev_dbg(&piix4_adapter->dev, "Successful!\n");
460 }
461 }
462
463
464 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
465
466
467 if (srvrworks_csb5_delay)
468 usleep_range(2000, 2100);
469 else
470 usleep_range(250, 500);
471
472 while ((++timeout < MAX_TIMEOUT) &&
473 ((temp = inb_p(SMBHSTSTS)) & 0x01))
474 usleep_range(250, 500);
475
476
477 if (timeout == MAX_TIMEOUT) {
478 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
479 result = -ETIMEDOUT;
480 }
481
482 if (temp & 0x10) {
483 result = -EIO;
484 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
485 }
486
487 if (temp & 0x08) {
488 result = -EIO;
489 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
490 "locked until next hard reset. (sorry!)\n");
491
492 }
493
494 if (temp & 0x04) {
495 result = -ENXIO;
496 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
497 }
498
499 if (inb_p(SMBHSTSTS) != 0x00)
500 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
501
502 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
503 dev_err(&piix4_adapter->dev, "Failed reset at end of "
504 "transaction (%02x)\n", temp);
505 }
506 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
507 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
508 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
509 inb_p(SMBHSTDAT1));
510 return result;
511}
512
513
514static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
515 unsigned short flags, char read_write,
516 u8 command, int size, union i2c_smbus_data * data)
517{
518 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
519 unsigned short piix4_smba = adapdata->smba;
520 int i, len;
521 int status;
522
523 switch (size) {
524 case I2C_SMBUS_QUICK:
525 outb_p((addr << 1) | read_write,
526 SMBHSTADD);
527 size = PIIX4_QUICK;
528 break;
529 case I2C_SMBUS_BYTE:
530 outb_p((addr << 1) | read_write,
531 SMBHSTADD);
532 if (read_write == I2C_SMBUS_WRITE)
533 outb_p(command, SMBHSTCMD);
534 size = PIIX4_BYTE;
535 break;
536 case I2C_SMBUS_BYTE_DATA:
537 outb_p((addr << 1) | read_write,
538 SMBHSTADD);
539 outb_p(command, SMBHSTCMD);
540 if (read_write == I2C_SMBUS_WRITE)
541 outb_p(data->byte, SMBHSTDAT0);
542 size = PIIX4_BYTE_DATA;
543 break;
544 case I2C_SMBUS_WORD_DATA:
545 outb_p((addr << 1) | read_write,
546 SMBHSTADD);
547 outb_p(command, SMBHSTCMD);
548 if (read_write == I2C_SMBUS_WRITE) {
549 outb_p(data->word & 0xff, SMBHSTDAT0);
550 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
551 }
552 size = PIIX4_WORD_DATA;
553 break;
554 case I2C_SMBUS_BLOCK_DATA:
555 outb_p((addr << 1) | read_write,
556 SMBHSTADD);
557 outb_p(command, SMBHSTCMD);
558 if (read_write == I2C_SMBUS_WRITE) {
559 len = data->block[0];
560 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
561 return -EINVAL;
562 outb_p(len, SMBHSTDAT0);
563 inb_p(SMBHSTCNT);
564 for (i = 1; i <= len; i++)
565 outb_p(data->block[i], SMBBLKDAT);
566 }
567 size = PIIX4_BLOCK_DATA;
568 break;
569 default:
570 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
571 return -EOPNOTSUPP;
572 }
573
574 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
575
576 status = piix4_transaction(adap);
577 if (status)
578 return status;
579
580 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
581 return 0;
582
583
584 switch (size) {
585 case PIIX4_BYTE:
586 case PIIX4_BYTE_DATA:
587 data->byte = inb_p(SMBHSTDAT0);
588 break;
589 case PIIX4_WORD_DATA:
590 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
591 break;
592 case PIIX4_BLOCK_DATA:
593 data->block[0] = inb_p(SMBHSTDAT0);
594 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
595 return -EPROTO;
596 inb_p(SMBHSTCNT);
597 for (i = 1; i <= data->block[0]; i++)
598 data->block[i] = inb_p(SMBBLKDAT);
599 break;
600 }
601 return 0;
602}
603
604static uint8_t piix4_imc_read(uint8_t idx)
605{
606 outb_p(idx, KERNCZ_IMC_IDX);
607 return inb_p(KERNCZ_IMC_DATA);
608}
609
610static void piix4_imc_write(uint8_t idx, uint8_t value)
611{
612 outb_p(idx, KERNCZ_IMC_IDX);
613 outb_p(value, KERNCZ_IMC_DATA);
614}
615
616static int piix4_imc_sleep(void)
617{
618 int timeout = MAX_TIMEOUT;
619
620 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
621 return -EBUSY;
622
623
624 piix4_imc_write(0x82, 0x00);
625
626 piix4_imc_write(0x83, 0xB4);
627
628 piix4_imc_write(0x80, 0x96);
629
630 while (timeout--) {
631 if (piix4_imc_read(0x82) == 0xfa) {
632 release_region(KERNCZ_IMC_IDX, 2);
633 return 0;
634 }
635 usleep_range(1000, 2000);
636 }
637
638 release_region(KERNCZ_IMC_IDX, 2);
639 return -ETIMEDOUT;
640}
641
642static void piix4_imc_wakeup(void)
643{
644 int timeout = MAX_TIMEOUT;
645
646 if (!request_muxed_region(KERNCZ_IMC_IDX, 2, "smbus_kerncz_imc"))
647 return;
648
649
650 piix4_imc_write(0x82, 0x00);
651
652 piix4_imc_write(0x83, 0xB5);
653
654 piix4_imc_write(0x80, 0x96);
655
656 while (timeout--) {
657 if (piix4_imc_read(0x82) == 0xfa)
658 break;
659 usleep_range(1000, 2000);
660 }
661
662 release_region(KERNCZ_IMC_IDX, 2);
663}
664
665
666
667
668
669
670
671
672
673static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr,
674 unsigned short flags, char read_write,
675 u8 command, int size, union i2c_smbus_data *data)
676{
677 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
678 unsigned short piix4_smba = adapdata->smba;
679 int retries = MAX_TIMEOUT;
680 int smbslvcnt;
681 u8 smba_en_lo;
682 u8 port;
683 int retval;
684
685 if (!request_muxed_region(SB800_PIIX4_SMB_IDX, 2, "sb800_piix4_smb"))
686 return -EBUSY;
687
688
689 smbslvcnt = inb_p(SMBSLVCNT);
690 do {
691 outb_p(smbslvcnt | 0x10, SMBSLVCNT);
692
693
694 smbslvcnt = inb_p(SMBSLVCNT);
695 if (smbslvcnt & 0x10)
696 break;
697
698 usleep_range(1000, 2000);
699 } while (--retries);
700
701 if (!retries) {
702 retval = -EBUSY;
703 goto release;
704 }
705
706
707
708
709
710
711
712
713
714
715 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc) {
716 int ret;
717
718 ret = piix4_imc_sleep();
719 switch (ret) {
720 case -EBUSY:
721 dev_warn(&adap->dev,
722 "IMC base address index region 0x%x already in use.\n",
723 KERNCZ_IMC_IDX);
724 break;
725 case -ETIMEDOUT:
726 dev_warn(&adap->dev,
727 "Failed to communicate with the IMC.\n");
728 break;
729 default:
730 break;
731 }
732
733
734 if (ret) {
735 dev_warn(&adap->dev,
736 "Continuing without IMC notification.\n");
737 adapdata->notify_imc = false;
738 }
739 }
740
741 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX);
742 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1);
743
744 port = adapdata->port;
745 if ((smba_en_lo & piix4_port_mask_sb800) != port)
746 outb_p((smba_en_lo & ~piix4_port_mask_sb800) | port,
747 SB800_PIIX4_SMB_IDX + 1);
748
749 retval = piix4_access(adap, addr, flags, read_write,
750 command, size, data);
751
752 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1);
753
754
755 outb_p(smbslvcnt | 0x20, SMBSLVCNT);
756
757 if ((size == I2C_SMBUS_BLOCK_DATA) && adapdata->notify_imc)
758 piix4_imc_wakeup();
759
760release:
761 release_region(SB800_PIIX4_SMB_IDX, 2);
762 return retval;
763}
764
765static u32 piix4_func(struct i2c_adapter *adapter)
766{
767 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
768 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
769 I2C_FUNC_SMBUS_BLOCK_DATA;
770}
771
772static const struct i2c_algorithm smbus_algorithm = {
773 .smbus_xfer = piix4_access,
774 .functionality = piix4_func,
775};
776
777static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = {
778 .smbus_xfer = piix4_access_sb800,
779 .functionality = piix4_func,
780};
781
782static const struct pci_device_id piix4_ids[] = {
783 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
784 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
785 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
786 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
787 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
788 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
789 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
790 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
791 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
792 { PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) },
793 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
794 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
795 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
796 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
797 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
798 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
799 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
800 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
801 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
802 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
803 { 0, }
804};
805
806MODULE_DEVICE_TABLE (pci, piix4_ids);
807
808static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS];
809static struct i2c_adapter *piix4_aux_adapter;
810static int piix4_adapter_count;
811
812static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba,
813 bool sb800_main, u8 port, bool notify_imc,
814 u8 hw_port_nr, const char *name,
815 struct i2c_adapter **padap)
816{
817 struct i2c_adapter *adap;
818 struct i2c_piix4_adapdata *adapdata;
819 int retval;
820
821 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
822 if (adap == NULL) {
823 release_region(smba, SMBIOSIZE);
824 return -ENOMEM;
825 }
826
827 adap->owner = THIS_MODULE;
828 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
829 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800
830 : &smbus_algorithm;
831
832 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
833 if (adapdata == NULL) {
834 kfree(adap);
835 release_region(smba, SMBIOSIZE);
836 return -ENOMEM;
837 }
838
839 adapdata->smba = smba;
840 adapdata->sb800_main = sb800_main;
841 adapdata->port = port << piix4_port_shift_sb800;
842 adapdata->notify_imc = notify_imc;
843
844
845 adap->dev.parent = &dev->dev;
846
847 if (has_acpi_companion(&dev->dev)) {
848 acpi_preset_companion(&adap->dev,
849 ACPI_COMPANION(&dev->dev),
850 hw_port_nr);
851 }
852
853 snprintf(adap->name, sizeof(adap->name),
854 "SMBus PIIX4 adapter%s at %04x", name, smba);
855
856 i2c_set_adapdata(adap, adapdata);
857
858 retval = i2c_add_adapter(adap);
859 if (retval) {
860 kfree(adapdata);
861 kfree(adap);
862 release_region(smba, SMBIOSIZE);
863 return retval;
864 }
865
866 *padap = adap;
867 return 0;
868}
869
870static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba,
871 bool notify_imc)
872{
873 struct i2c_piix4_adapdata *adapdata;
874 int port;
875 int retval;
876
877 if (dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS ||
878 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS &&
879 dev->revision >= 0x1F)) {
880 piix4_adapter_count = HUDSON2_MAIN_PORTS;
881 } else {
882 piix4_adapter_count = PIIX4_MAX_ADAPTERS;
883 }
884
885 for (port = 0; port < piix4_adapter_count; port++) {
886 u8 hw_port_nr = port == 0 ? 0 : port + 1;
887
888 retval = piix4_add_adapter(dev, smba, true, port, notify_imc,
889 hw_port_nr,
890 piix4_main_port_names_sb800[port],
891 &piix4_main_adapters[port]);
892 if (retval < 0)
893 goto error;
894 }
895
896 return retval;
897
898error:
899 dev_err(&dev->dev,
900 "Error setting up SB800 adapters. Unregistering!\n");
901 while (--port >= 0) {
902 adapdata = i2c_get_adapdata(piix4_main_adapters[port]);
903 if (adapdata->smba) {
904 i2c_del_adapter(piix4_main_adapters[port]);
905 kfree(adapdata);
906 kfree(piix4_main_adapters[port]);
907 piix4_main_adapters[port] = NULL;
908 }
909 }
910
911 return retval;
912}
913
914static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id)
915{
916 int retval;
917 bool is_sb800 = false;
918
919 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
920 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
921 dev->revision >= 0x40) ||
922 dev->vendor == PCI_VENDOR_ID_AMD ||
923 dev->vendor == PCI_VENDOR_ID_HYGON) {
924 bool notify_imc = false;
925 is_sb800 = true;
926
927 if ((dev->vendor == PCI_VENDOR_ID_AMD ||
928 dev->vendor == PCI_VENDOR_ID_HYGON) &&
929 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) {
930 u8 imc;
931
932
933
934
935
936 pci_bus_read_config_byte(dev->bus, PCI_DEVFN(0x14, 3),
937 0x40, &imc);
938 if (imc & 0x80)
939 notify_imc = true;
940 }
941
942
943 retval = piix4_setup_sb800(dev, id, 0);
944 if (retval < 0)
945 return retval;
946
947
948
949
950
951 retval = piix4_add_adapters_sb800(dev, retval, notify_imc);
952 if (retval < 0)
953 return retval;
954 } else {
955 retval = piix4_setup(dev, id);
956 if (retval < 0)
957 return retval;
958
959
960 retval = piix4_add_adapter(dev, retval, false, 0, false, 0,
961 "", &piix4_main_adapters[0]);
962 if (retval < 0)
963 return retval;
964 }
965
966
967 retval = -ENODEV;
968
969 if (dev->vendor == PCI_VENDOR_ID_ATI &&
970 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) {
971 if (dev->revision < 0x40) {
972 retval = piix4_setup_aux(dev, id, 0x58);
973 } else {
974
975 retval = piix4_setup_sb800(dev, id, 1);
976 }
977 }
978
979 if (dev->vendor == PCI_VENDOR_ID_AMD &&
980 (dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS ||
981 dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS)) {
982 retval = piix4_setup_sb800(dev, id, 1);
983 }
984
985 if (retval > 0) {
986
987
988 piix4_add_adapter(dev, retval, false, 0, false, 1,
989 is_sb800 ? piix4_aux_port_name_sb800 : "",
990 &piix4_aux_adapter);
991 }
992
993 return 0;
994}
995
996static void piix4_adap_remove(struct i2c_adapter *adap)
997{
998 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
999
1000 if (adapdata->smba) {
1001 i2c_del_adapter(adap);
1002 if (adapdata->port == (0 << piix4_port_shift_sb800))
1003 release_region(adapdata->smba, SMBIOSIZE);
1004 kfree(adapdata);
1005 kfree(adap);
1006 }
1007}
1008
1009static void piix4_remove(struct pci_dev *dev)
1010{
1011 int port = piix4_adapter_count;
1012
1013 while (--port >= 0) {
1014 if (piix4_main_adapters[port]) {
1015 piix4_adap_remove(piix4_main_adapters[port]);
1016 piix4_main_adapters[port] = NULL;
1017 }
1018 }
1019
1020 if (piix4_aux_adapter) {
1021 piix4_adap_remove(piix4_aux_adapter);
1022 piix4_aux_adapter = NULL;
1023 }
1024}
1025
1026static struct pci_driver piix4_driver = {
1027 .name = "piix4_smbus",
1028 .id_table = piix4_ids,
1029 .probe = piix4_probe,
1030 .remove = piix4_remove,
1031};
1032
1033module_pci_driver(piix4_driver);
1034
1035MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl>");
1036MODULE_AUTHOR("Philip Edelbrock <phil@netroedge.com>");
1037MODULE_DESCRIPTION("PIIX4 SMBus driver");
1038MODULE_LICENSE("GPL");
1039
