1
2
3
4
5
6
7
8
9#include <linux/device.h>
10#include <linux/kernel.h>
11#include <linux/slab.h>
12#include <linux/sysfs.h>
13#include <linux/spi/spi.h>
14#include <linux/regulator/consumer.h>
15#include <linux/err.h>
16#include <linux/delay.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/trigger_consumer.h>
24#include <linux/iio/triggered_buffer.h>
25
26#define AD7923_WRITE_CR BIT(11)
27#define AD7923_RANGE BIT(1)
28#define AD7923_CODING BIT(0)
29#define AD7923_PM_MODE_AS (1)
30#define AD7923_PM_MODE_FS (2)
31#define AD7923_PM_MODE_OPS (3)
32#define AD7923_SEQUENCE_OFF (0)
33#define AD7923_SEQUENCE_PROTECT (2)
34#define AD7923_SEQUENCE_ON (3)
35
36
37#define AD7923_PM_MODE_WRITE(mode) ((mode) << 4)
38#define AD7923_CHANNEL_WRITE(channel) ((channel) << 6)
39#define AD7923_SEQUENCE_WRITE(sequence) ((((sequence) & 1) << 3) \
40 + (((sequence) & 2) << 9))
41
42
43#define AD7923_SHIFT_REGISTER 4
44
45
46#define EXTRACT(val, dec, bits) (((val) >> (dec)) & ((1 << (bits)) - 1))
47
48struct ad7923_state {
49 struct spi_device *spi;
50 struct spi_transfer ring_xfer[5];
51 struct spi_transfer scan_single_xfer[2];
52 struct spi_message ring_msg;
53 struct spi_message scan_single_msg;
54
55 struct regulator *reg;
56
57 unsigned int settings;
58
59
60
61
62
63
64
65 __be16 rx_buf[12] ____cacheline_aligned;
66 __be16 tx_buf[4];
67};
68
69struct ad7923_chip_info {
70 const struct iio_chan_spec *channels;
71 unsigned int num_channels;
72};
73
74enum ad7923_id {
75 AD7904,
76 AD7914,
77 AD7924,
78 AD7908,
79 AD7918,
80 AD7928
81};
82
83#define AD7923_V_CHAN(index, bits) \
84 { \
85 .type = IIO_VOLTAGE, \
86 .indexed = 1, \
87 .channel = index, \
88 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
89 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
90 .address = index, \
91 .scan_index = index, \
92 .scan_type = { \
93 .sign = 'u', \
94 .realbits = (bits), \
95 .storagebits = 16, \
96 .endianness = IIO_BE, \
97 }, \
98 }
99
100#define DECLARE_AD7923_CHANNELS(name, bits) \
101const struct iio_chan_spec name ## _channels[] = { \
102 AD7923_V_CHAN(0, bits), \
103 AD7923_V_CHAN(1, bits), \
104 AD7923_V_CHAN(2, bits), \
105 AD7923_V_CHAN(3, bits), \
106 IIO_CHAN_SOFT_TIMESTAMP(4), \
107}
108
109#define DECLARE_AD7908_CHANNELS(name, bits) \
110const struct iio_chan_spec name ## _channels[] = { \
111 AD7923_V_CHAN(0, bits), \
112 AD7923_V_CHAN(1, bits), \
113 AD7923_V_CHAN(2, bits), \
114 AD7923_V_CHAN(3, bits), \
115 AD7923_V_CHAN(4, bits), \
116 AD7923_V_CHAN(5, bits), \
117 AD7923_V_CHAN(6, bits), \
118 AD7923_V_CHAN(7, bits), \
119 IIO_CHAN_SOFT_TIMESTAMP(8), \
120}
121
122static DECLARE_AD7923_CHANNELS(ad7904, 8);
123static DECLARE_AD7923_CHANNELS(ad7914, 10);
124static DECLARE_AD7923_CHANNELS(ad7924, 12);
125static DECLARE_AD7908_CHANNELS(ad7908, 8);
126static DECLARE_AD7908_CHANNELS(ad7918, 10);
127static DECLARE_AD7908_CHANNELS(ad7928, 12);
128
129static const struct ad7923_chip_info ad7923_chip_info[] = {
130 [AD7904] = {
131 .channels = ad7904_channels,
132 .num_channels = ARRAY_SIZE(ad7904_channels),
133 },
134 [AD7914] = {
135 .channels = ad7914_channels,
136 .num_channels = ARRAY_SIZE(ad7914_channels),
137 },
138 [AD7924] = {
139 .channels = ad7924_channels,
140 .num_channels = ARRAY_SIZE(ad7924_channels),
141 },
142 [AD7908] = {
143 .channels = ad7908_channels,
144 .num_channels = ARRAY_SIZE(ad7908_channels),
145 },
146 [AD7918] = {
147 .channels = ad7918_channels,
148 .num_channels = ARRAY_SIZE(ad7918_channels),
149 },
150 [AD7928] = {
151 .channels = ad7928_channels,
152 .num_channels = ARRAY_SIZE(ad7928_channels),
153 },
154};
155
156
157
158
159static int ad7923_update_scan_mode(struct iio_dev *indio_dev,
160 const unsigned long *active_scan_mask)
161{
162 struct ad7923_state *st = iio_priv(indio_dev);
163 int i, cmd, len;
164
165 len = 0;
166
167
168
169
170 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels - 1) {
171 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(i) |
172 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
173 st->settings;
174 cmd <<= AD7923_SHIFT_REGISTER;
175 st->tx_buf[len++] = cpu_to_be16(cmd);
176 }
177
178 st->ring_xfer[0].tx_buf = &st->tx_buf[0];
179 st->ring_xfer[0].len = len;
180 st->ring_xfer[0].cs_change = 1;
181
182 spi_message_init(&st->ring_msg);
183 spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
184
185 for (i = 0; i < len; i++) {
186 st->ring_xfer[i + 1].rx_buf = &st->rx_buf[i];
187 st->ring_xfer[i + 1].len = 2;
188 st->ring_xfer[i + 1].cs_change = 1;
189 spi_message_add_tail(&st->ring_xfer[i + 1], &st->ring_msg);
190 }
191
192 st->ring_xfer[i + 1].cs_change = 0;
193
194 return 0;
195}
196
197static irqreturn_t ad7923_trigger_handler(int irq, void *p)
198{
199 struct iio_poll_func *pf = p;
200 struct iio_dev *indio_dev = pf->indio_dev;
201 struct ad7923_state *st = iio_priv(indio_dev);
202 int b_sent;
203
204 b_sent = spi_sync(st->spi, &st->ring_msg);
205 if (b_sent)
206 goto done;
207
208 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
209 iio_get_time_ns(indio_dev));
210
211done:
212 iio_trigger_notify_done(indio_dev->trig);
213
214 return IRQ_HANDLED;
215}
216
217static int ad7923_scan_direct(struct ad7923_state *st, unsigned int ch)
218{
219 int ret, cmd;
220
221 cmd = AD7923_WRITE_CR | AD7923_CHANNEL_WRITE(ch) |
222 AD7923_SEQUENCE_WRITE(AD7923_SEQUENCE_OFF) |
223 st->settings;
224 cmd <<= AD7923_SHIFT_REGISTER;
225 st->tx_buf[0] = cpu_to_be16(cmd);
226
227 ret = spi_sync(st->spi, &st->scan_single_msg);
228 if (ret)
229 return ret;
230
231 return be16_to_cpu(st->rx_buf[0]);
232}
233
234static int ad7923_get_range(struct ad7923_state *st)
235{
236 int vref;
237
238 vref = regulator_get_voltage(st->reg);
239 if (vref < 0)
240 return vref;
241
242 vref /= 1000;
243
244 if (!(st->settings & AD7923_RANGE))
245 vref *= 2;
246
247 return vref;
248}
249
250static int ad7923_read_raw(struct iio_dev *indio_dev,
251 struct iio_chan_spec const *chan,
252 int *val,
253 int *val2,
254 long m)
255{
256 int ret;
257 struct ad7923_state *st = iio_priv(indio_dev);
258
259 switch (m) {
260 case IIO_CHAN_INFO_RAW:
261 ret = iio_device_claim_direct_mode(indio_dev);
262 if (ret)
263 return ret;
264 ret = ad7923_scan_direct(st, chan->address);
265 iio_device_release_direct_mode(indio_dev);
266
267 if (ret < 0)
268 return ret;
269
270 if (chan->address == EXTRACT(ret, 12, 4))
271 *val = EXTRACT(ret, 0, 12);
272 else
273 return -EIO;
274
275 return IIO_VAL_INT;
276 case IIO_CHAN_INFO_SCALE:
277 ret = ad7923_get_range(st);
278 if (ret < 0)
279 return ret;
280 *val = ret;
281 *val2 = chan->scan_type.realbits;
282 return IIO_VAL_FRACTIONAL_LOG2;
283 }
284 return -EINVAL;
285}
286
287static const struct iio_info ad7923_info = {
288 .read_raw = &ad7923_read_raw,
289 .update_scan_mode = ad7923_update_scan_mode,
290};
291
292static void ad7923_regulator_disable(void *data)
293{
294 struct ad7923_state *st = data;
295
296 regulator_disable(st->reg);
297}
298
299static int ad7923_probe(struct spi_device *spi)
300{
301 struct ad7923_state *st;
302 struct iio_dev *indio_dev;
303 const struct ad7923_chip_info *info;
304 int ret;
305
306 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
307 if (!indio_dev)
308 return -ENOMEM;
309
310 st = iio_priv(indio_dev);
311
312 st->spi = spi;
313 st->settings = AD7923_CODING | AD7923_RANGE |
314 AD7923_PM_MODE_WRITE(AD7923_PM_MODE_OPS);
315
316 info = &ad7923_chip_info[spi_get_device_id(spi)->driver_data];
317
318 indio_dev->name = spi_get_device_id(spi)->name;
319 indio_dev->modes = INDIO_DIRECT_MODE;
320 indio_dev->channels = info->channels;
321 indio_dev->num_channels = info->num_channels;
322 indio_dev->info = &ad7923_info;
323
324
325
326 st->scan_single_xfer[0].tx_buf = &st->tx_buf[0];
327 st->scan_single_xfer[0].len = 2;
328 st->scan_single_xfer[0].cs_change = 1;
329 st->scan_single_xfer[1].rx_buf = &st->rx_buf[0];
330 st->scan_single_xfer[1].len = 2;
331
332 spi_message_init(&st->scan_single_msg);
333 spi_message_add_tail(&st->scan_single_xfer[0], &st->scan_single_msg);
334 spi_message_add_tail(&st->scan_single_xfer[1], &st->scan_single_msg);
335
336 st->reg = devm_regulator_get(&spi->dev, "refin");
337 if (IS_ERR(st->reg))
338 return PTR_ERR(st->reg);
339
340 ret = regulator_enable(st->reg);
341 if (ret)
342 return ret;
343
344 ret = devm_add_action_or_reset(&spi->dev, ad7923_regulator_disable, st);
345 if (ret)
346 return ret;
347
348 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
349 &ad7923_trigger_handler, NULL);
350 if (ret)
351 return ret;
352
353 return devm_iio_device_register(&spi->dev, indio_dev);
354}
355
356static const struct spi_device_id ad7923_id[] = {
357 {"ad7904", AD7904},
358 {"ad7914", AD7914},
359 {"ad7923", AD7924},
360 {"ad7924", AD7924},
361 {"ad7908", AD7908},
362 {"ad7918", AD7918},
363 {"ad7928", AD7928},
364 {}
365};
366MODULE_DEVICE_TABLE(spi, ad7923_id);
367
368static const struct of_device_id ad7923_of_match[] = {
369 { .compatible = "adi,ad7904", },
370 { .compatible = "adi,ad7914", },
371 { .compatible = "adi,ad7923", },
372 { .compatible = "adi,ad7924", },
373 { .compatible = "adi,ad7908", },
374 { .compatible = "adi,ad7918", },
375 { .compatible = "adi,ad7928", },
376 { },
377};
378MODULE_DEVICE_TABLE(of, ad7923_of_match);
379
380static struct spi_driver ad7923_driver = {
381 .driver = {
382 .name = "ad7923",
383 .of_match_table = ad7923_of_match,
384 },
385 .probe = ad7923_probe,
386 .id_table = ad7923_id,
387};
388module_spi_driver(ad7923_driver);
389
390MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
391MODULE_AUTHOR("Patrick Vasseur <patrick.vasseur@c-s.fr>");
392MODULE_DESCRIPTION("Analog Devices AD7923 and similar ADC");
393MODULE_LICENSE("GPL v2");
394
