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8#include <linux/clk.h>
9#include <linux/clk-provider.h>
10#include <linux/err.h>
11#include <linux/errno.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/of_platform.h>
15#include <linux/platform_device.h>
16#include <linux/reset.h>
17#include <linux/spinlock.h>
18#include <linux/types.h>
19
20#include <linux/iio/iio.h>
21#include <linux/iio/driver.h>
22#include <linux/iopoll.h>
23
24#define ASPEED_RESOLUTION_BITS 10
25#define ASPEED_CLOCKS_PER_SAMPLE 12
26
27#define ASPEED_REG_ENGINE_CONTROL 0x00
28#define ASPEED_REG_INTERRUPT_CONTROL 0x04
29#define ASPEED_REG_VGA_DETECT_CONTROL 0x08
30#define ASPEED_REG_CLOCK_CONTROL 0x0C
31#define ASPEED_REG_MAX 0xC0
32
33#define ASPEED_OPERATION_MODE_POWER_DOWN (0x0 << 1)
34#define ASPEED_OPERATION_MODE_STANDBY (0x1 << 1)
35#define ASPEED_OPERATION_MODE_NORMAL (0x7 << 1)
36
37#define ASPEED_ENGINE_ENABLE BIT(0)
38
39#define ASPEED_ADC_CTRL_INIT_RDY BIT(8)
40
41#define ASPEED_ADC_INIT_POLLING_TIME 500
42#define ASPEED_ADC_INIT_TIMEOUT 500000
43
44struct aspeed_adc_model_data {
45 const char *model_name;
46 unsigned int min_sampling_rate;
47 unsigned int max_sampling_rate;
48 unsigned int vref_voltage;
49 bool wait_init_sequence;
50};
51
52struct aspeed_adc_data {
53 struct device *dev;
54 void __iomem *base;
55 spinlock_t clk_lock;
56 struct clk_hw *clk_prescaler;
57 struct clk_hw *clk_scaler;
58 struct reset_control *rst;
59};
60
61#define ASPEED_CHAN(_idx, _data_reg_addr) { \
62 .type = IIO_VOLTAGE, \
63 .indexed = 1, \
64 .channel = (_idx), \
65 .address = (_data_reg_addr), \
66 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
67 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
68 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
69}
70
71static const struct iio_chan_spec aspeed_adc_iio_channels[] = {
72 ASPEED_CHAN(0, 0x10),
73 ASPEED_CHAN(1, 0x12),
74 ASPEED_CHAN(2, 0x14),
75 ASPEED_CHAN(3, 0x16),
76 ASPEED_CHAN(4, 0x18),
77 ASPEED_CHAN(5, 0x1A),
78 ASPEED_CHAN(6, 0x1C),
79 ASPEED_CHAN(7, 0x1E),
80 ASPEED_CHAN(8, 0x20),
81 ASPEED_CHAN(9, 0x22),
82 ASPEED_CHAN(10, 0x24),
83 ASPEED_CHAN(11, 0x26),
84 ASPEED_CHAN(12, 0x28),
85 ASPEED_CHAN(13, 0x2A),
86 ASPEED_CHAN(14, 0x2C),
87 ASPEED_CHAN(15, 0x2E),
88};
89
90static int aspeed_adc_read_raw(struct iio_dev *indio_dev,
91 struct iio_chan_spec const *chan,
92 int *val, int *val2, long mask)
93{
94 struct aspeed_adc_data *data = iio_priv(indio_dev);
95 const struct aspeed_adc_model_data *model_data =
96 of_device_get_match_data(data->dev);
97
98 switch (mask) {
99 case IIO_CHAN_INFO_RAW:
100 *val = readw(data->base + chan->address);
101 return IIO_VAL_INT;
102
103 case IIO_CHAN_INFO_SCALE:
104 *val = model_data->vref_voltage;
105 *val2 = ASPEED_RESOLUTION_BITS;
106 return IIO_VAL_FRACTIONAL_LOG2;
107
108 case IIO_CHAN_INFO_SAMP_FREQ:
109 *val = clk_get_rate(data->clk_scaler->clk) /
110 ASPEED_CLOCKS_PER_SAMPLE;
111 return IIO_VAL_INT;
112
113 default:
114 return -EINVAL;
115 }
116}
117
118static int aspeed_adc_write_raw(struct iio_dev *indio_dev,
119 struct iio_chan_spec const *chan,
120 int val, int val2, long mask)
121{
122 struct aspeed_adc_data *data = iio_priv(indio_dev);
123 const struct aspeed_adc_model_data *model_data =
124 of_device_get_match_data(data->dev);
125
126 switch (mask) {
127 case IIO_CHAN_INFO_SAMP_FREQ:
128 if (val < model_data->min_sampling_rate ||
129 val > model_data->max_sampling_rate)
130 return -EINVAL;
131
132 clk_set_rate(data->clk_scaler->clk,
133 val * ASPEED_CLOCKS_PER_SAMPLE);
134 return 0;
135
136 case IIO_CHAN_INFO_SCALE:
137 case IIO_CHAN_INFO_RAW:
138
139
140
141
142
143
144 return -EPERM;
145
146 default:
147 return -EINVAL;
148 }
149}
150
151static int aspeed_adc_reg_access(struct iio_dev *indio_dev,
152 unsigned int reg, unsigned int writeval,
153 unsigned int *readval)
154{
155 struct aspeed_adc_data *data = iio_priv(indio_dev);
156
157 if (!readval || reg % 4 || reg > ASPEED_REG_MAX)
158 return -EINVAL;
159
160 *readval = readl(data->base + reg);
161
162 return 0;
163}
164
165static const struct iio_info aspeed_adc_iio_info = {
166 .read_raw = aspeed_adc_read_raw,
167 .write_raw = aspeed_adc_write_raw,
168 .debugfs_reg_access = aspeed_adc_reg_access,
169};
170
171static int aspeed_adc_probe(struct platform_device *pdev)
172{
173 struct iio_dev *indio_dev;
174 struct aspeed_adc_data *data;
175 const struct aspeed_adc_model_data *model_data;
176 const char *clk_parent_name;
177 int ret;
178 u32 adc_engine_control_reg_val;
179
180 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data));
181 if (!indio_dev)
182 return -ENOMEM;
183
184 data = iio_priv(indio_dev);
185 data->dev = &pdev->dev;
186 platform_set_drvdata(pdev, indio_dev);
187
188 data->base = devm_platform_ioremap_resource(pdev, 0);
189 if (IS_ERR(data->base))
190 return PTR_ERR(data->base);
191
192
193 spin_lock_init(&data->clk_lock);
194 clk_parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
195
196 data->clk_prescaler = clk_hw_register_divider(
197 &pdev->dev, "prescaler", clk_parent_name, 0,
198 data->base + ASPEED_REG_CLOCK_CONTROL,
199 17, 15, 0, &data->clk_lock);
200 if (IS_ERR(data->clk_prescaler))
201 return PTR_ERR(data->clk_prescaler);
202
203
204
205
206
207 data->clk_scaler = clk_hw_register_divider(
208 &pdev->dev, "scaler", "prescaler",
209 CLK_SET_RATE_PARENT,
210 data->base + ASPEED_REG_CLOCK_CONTROL,
211 0, 10, 0, &data->clk_lock);
212 if (IS_ERR(data->clk_scaler)) {
213 ret = PTR_ERR(data->clk_scaler);
214 goto scaler_error;
215 }
216
217 data->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
218 if (IS_ERR(data->rst)) {
219 dev_err(&pdev->dev,
220 "invalid or missing reset controller device tree entry");
221 ret = PTR_ERR(data->rst);
222 goto reset_error;
223 }
224 reset_control_deassert(data->rst);
225
226 model_data = of_device_get_match_data(&pdev->dev);
227
228 if (model_data->wait_init_sequence) {
229
230 writel(ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE,
231 data->base + ASPEED_REG_ENGINE_CONTROL);
232
233
234 ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL,
235 adc_engine_control_reg_val,
236 adc_engine_control_reg_val &
237 ASPEED_ADC_CTRL_INIT_RDY,
238 ASPEED_ADC_INIT_POLLING_TIME,
239 ASPEED_ADC_INIT_TIMEOUT);
240 if (ret)
241 goto poll_timeout_error;
242 }
243
244
245 ret = clk_prepare_enable(data->clk_scaler->clk);
246 if (ret)
247 goto clk_enable_error;
248
249 adc_engine_control_reg_val = GENMASK(31, 16) |
250 ASPEED_OPERATION_MODE_NORMAL | ASPEED_ENGINE_ENABLE;
251 writel(adc_engine_control_reg_val,
252 data->base + ASPEED_REG_ENGINE_CONTROL);
253
254 model_data = of_device_get_match_data(&pdev->dev);
255 indio_dev->name = model_data->model_name;
256 indio_dev->info = &aspeed_adc_iio_info;
257 indio_dev->modes = INDIO_DIRECT_MODE;
258 indio_dev->channels = aspeed_adc_iio_channels;
259 indio_dev->num_channels = ARRAY_SIZE(aspeed_adc_iio_channels);
260
261 ret = iio_device_register(indio_dev);
262 if (ret)
263 goto iio_register_error;
264
265 return 0;
266
267iio_register_error:
268 writel(ASPEED_OPERATION_MODE_POWER_DOWN,
269 data->base + ASPEED_REG_ENGINE_CONTROL);
270 clk_disable_unprepare(data->clk_scaler->clk);
271clk_enable_error:
272poll_timeout_error:
273 reset_control_assert(data->rst);
274reset_error:
275 clk_hw_unregister_divider(data->clk_scaler);
276scaler_error:
277 clk_hw_unregister_divider(data->clk_prescaler);
278 return ret;
279}
280
281static int aspeed_adc_remove(struct platform_device *pdev)
282{
283 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
284 struct aspeed_adc_data *data = iio_priv(indio_dev);
285
286 iio_device_unregister(indio_dev);
287 writel(ASPEED_OPERATION_MODE_POWER_DOWN,
288 data->base + ASPEED_REG_ENGINE_CONTROL);
289 clk_disable_unprepare(data->clk_scaler->clk);
290 reset_control_assert(data->rst);
291 clk_hw_unregister_divider(data->clk_scaler);
292 clk_hw_unregister_divider(data->clk_prescaler);
293
294 return 0;
295}
296
297static const struct aspeed_adc_model_data ast2400_model_data = {
298 .model_name = "ast2400-adc",
299 .vref_voltage = 2500,
300 .min_sampling_rate = 10000,
301 .max_sampling_rate = 500000,
302};
303
304static const struct aspeed_adc_model_data ast2500_model_data = {
305 .model_name = "ast2500-adc",
306 .vref_voltage = 1800,
307 .min_sampling_rate = 1,
308 .max_sampling_rate = 1000000,
309 .wait_init_sequence = true,
310};
311
312static const struct of_device_id aspeed_adc_matches[] = {
313 { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data },
314 { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data },
315 {},
316};
317MODULE_DEVICE_TABLE(of, aspeed_adc_matches);
318
319static struct platform_driver aspeed_adc_driver = {
320 .probe = aspeed_adc_probe,
321 .remove = aspeed_adc_remove,
322 .driver = {
323 .name = KBUILD_MODNAME,
324 .of_match_table = aspeed_adc_matches,
325 }
326};
327
328module_platform_driver(aspeed_adc_driver);
329
330MODULE_AUTHOR("Rick Altherr <raltherr@google.com>");
331MODULE_DESCRIPTION("Aspeed AST2400/2500 ADC Driver");
332MODULE_LICENSE("GPL");
333
