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16#include <linux/err.h>
17#include <linux/i2c.h>
18#include <linux/module.h>
19#include <linux/mod_devicetable.h>
20#include <linux/delay.h>
21#include <linux/sysfs.h>
22#include <asm/unaligned.h>
23
24#include <linux/iio/iio.h>
25#include <linux/iio/sysfs.h>
26
27
28#define MCP3422_CHANNEL_MASK 0x60
29#define MCP3422_PGA_MASK 0x03
30#define MCP3422_SRATE_MASK 0x0C
31#define MCP3422_SRATE_240 0x0
32#define MCP3422_SRATE_60 0x1
33#define MCP3422_SRATE_15 0x2
34#define MCP3422_SRATE_3 0x3
35#define MCP3422_PGA_1 0
36#define MCP3422_PGA_2 1
37#define MCP3422_PGA_4 2
38#define MCP3422_PGA_8 3
39#define MCP3422_CONT_SAMPLING 0x10
40
41#define MCP3422_CHANNEL(config) (((config) & MCP3422_CHANNEL_MASK) >> 5)
42#define MCP3422_PGA(config) ((config) & MCP3422_PGA_MASK)
43#define MCP3422_SAMPLE_RATE(config) (((config) & MCP3422_SRATE_MASK) >> 2)
44
45#define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK)
46#define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK)
47#define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK)
48
49#define MCP3422_CHAN(_index) \
50 { \
51 .type = IIO_VOLTAGE, \
52 .indexed = 1, \
53 .channel = _index, \
54 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
55 | BIT(IIO_CHAN_INFO_SCALE), \
56 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
57 }
58
59static const int mcp3422_scales[4][4] = {
60 { 1000000, 500000, 250000, 125000 },
61 { 250000, 125000, 62500, 31250 },
62 { 62500, 31250, 15625, 7812 },
63 { 15625, 7812, 3906, 1953 } };
64
65
66static const int mcp3422_read_times[4] = {
67 [MCP3422_SRATE_240] = 1000 / 240,
68 [MCP3422_SRATE_60] = 1000 / 60,
69 [MCP3422_SRATE_15] = 1000 / 15,
70 [MCP3422_SRATE_3] = 1000 / 3 };
71
72
73static const int mcp3422_sample_rates[4] = {
74 [MCP3422_SRATE_240] = 240,
75 [MCP3422_SRATE_60] = 60,
76 [MCP3422_SRATE_15] = 15,
77 [MCP3422_SRATE_3] = 3 };
78
79
80static const int mcp3422_sign_extend[4] = {
81 [MCP3422_SRATE_240] = 11,
82 [MCP3422_SRATE_60] = 13,
83 [MCP3422_SRATE_15] = 15,
84 [MCP3422_SRATE_3] = 17 };
85
86
87struct mcp3422 {
88 struct i2c_client *i2c;
89 u8 id;
90 u8 config;
91 u8 pga[4];
92 struct mutex lock;
93};
94
95static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig)
96{
97 int ret;
98
99 ret = i2c_master_send(adc->i2c, &newconfig, 1);
100 if (ret > 0) {
101 adc->config = newconfig;
102 ret = 0;
103 }
104
105 return ret;
106}
107
108static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config)
109{
110 int ret = 0;
111 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
112 u8 buf[4] = {0, 0, 0, 0};
113 u32 temp;
114
115 if (sample_rate == MCP3422_SRATE_3) {
116 ret = i2c_master_recv(adc->i2c, buf, 4);
117 temp = get_unaligned_be24(&buf[0]);
118 *config = buf[3];
119 } else {
120 ret = i2c_master_recv(adc->i2c, buf, 3);
121 temp = get_unaligned_be16(&buf[0]);
122 *config = buf[2];
123 }
124
125 *value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]);
126
127 return ret;
128}
129
130static int mcp3422_read_channel(struct mcp3422 *adc,
131 struct iio_chan_spec const *channel, int *value)
132{
133 int ret;
134 u8 config;
135 u8 req_channel = channel->channel;
136
137 mutex_lock(&adc->lock);
138
139 if (req_channel != MCP3422_CHANNEL(adc->config)) {
140 config = adc->config;
141 config &= ~MCP3422_CHANNEL_MASK;
142 config |= MCP3422_CHANNEL_VALUE(req_channel);
143 config &= ~MCP3422_PGA_MASK;
144 config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
145 ret = mcp3422_update_config(adc, config);
146 if (ret < 0) {
147 mutex_unlock(&adc->lock);
148 return ret;
149 }
150 msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]);
151 }
152
153 ret = mcp3422_read(adc, value, &config);
154
155 mutex_unlock(&adc->lock);
156
157 return ret;
158}
159
160static int mcp3422_read_raw(struct iio_dev *iio,
161 struct iio_chan_spec const *channel, int *val1,
162 int *val2, long mask)
163{
164 struct mcp3422 *adc = iio_priv(iio);
165 int err;
166
167 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
168 u8 pga = MCP3422_PGA(adc->config);
169
170 switch (mask) {
171 case IIO_CHAN_INFO_RAW:
172 err = mcp3422_read_channel(adc, channel, val1);
173 if (err < 0)
174 return -EINVAL;
175 return IIO_VAL_INT;
176
177 case IIO_CHAN_INFO_SCALE:
178
179 *val1 = 0;
180 *val2 = mcp3422_scales[sample_rate][pga];
181 return IIO_VAL_INT_PLUS_NANO;
182
183 case IIO_CHAN_INFO_SAMP_FREQ:
184 *val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)];
185 return IIO_VAL_INT;
186
187 default:
188 break;
189 }
190
191 return -EINVAL;
192}
193
194static int mcp3422_write_raw(struct iio_dev *iio,
195 struct iio_chan_spec const *channel, int val1,
196 int val2, long mask)
197{
198 struct mcp3422 *adc = iio_priv(iio);
199 u8 temp;
200 u8 config = adc->config;
201 u8 req_channel = channel->channel;
202 u8 sample_rate = MCP3422_SAMPLE_RATE(config);
203 u8 i;
204
205 switch (mask) {
206 case IIO_CHAN_INFO_SCALE:
207 if (val1 != 0)
208 return -EINVAL;
209
210 for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) {
211 if (val2 == mcp3422_scales[sample_rate][i]) {
212 adc->pga[req_channel] = i;
213
214 config &= ~MCP3422_CHANNEL_MASK;
215 config |= MCP3422_CHANNEL_VALUE(req_channel);
216 config &= ~MCP3422_PGA_MASK;
217 config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
218
219 return mcp3422_update_config(adc, config);
220 }
221 }
222 return -EINVAL;
223
224 case IIO_CHAN_INFO_SAMP_FREQ:
225 switch (val1) {
226 case 240:
227 temp = MCP3422_SRATE_240;
228 break;
229 case 60:
230 temp = MCP3422_SRATE_60;
231 break;
232 case 15:
233 temp = MCP3422_SRATE_15;
234 break;
235 case 3:
236 if (adc->id > 4)
237 return -EINVAL;
238 temp = MCP3422_SRATE_3;
239 break;
240 default:
241 return -EINVAL;
242 }
243
244 config &= ~MCP3422_CHANNEL_MASK;
245 config |= MCP3422_CHANNEL_VALUE(req_channel);
246 config &= ~MCP3422_SRATE_MASK;
247 config |= MCP3422_SAMPLE_RATE_VALUE(temp);
248
249 return mcp3422_update_config(adc, config);
250
251 default:
252 break;
253 }
254
255 return -EINVAL;
256}
257
258static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev,
259 struct iio_chan_spec const *chan, long mask)
260{
261 switch (mask) {
262 case IIO_CHAN_INFO_SCALE:
263 return IIO_VAL_INT_PLUS_NANO;
264 case IIO_CHAN_INFO_SAMP_FREQ:
265 return IIO_VAL_INT_PLUS_MICRO;
266 default:
267 return -EINVAL;
268 }
269}
270
271static ssize_t mcp3422_show_samp_freqs(struct device *dev,
272 struct device_attribute *attr, char *buf)
273{
274 struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
275
276 if (adc->id > 4)
277 return sprintf(buf, "240 60 15\n");
278
279 return sprintf(buf, "240 60 15 3\n");
280}
281
282static ssize_t mcp3422_show_scales(struct device *dev,
283 struct device_attribute *attr, char *buf)
284{
285 struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
286 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
287
288 return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n",
289 mcp3422_scales[sample_rate][0],
290 mcp3422_scales[sample_rate][1],
291 mcp3422_scales[sample_rate][2],
292 mcp3422_scales[sample_rate][3]);
293}
294
295static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO,
296 mcp3422_show_samp_freqs, NULL, 0);
297static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
298 mcp3422_show_scales, NULL, 0);
299
300static struct attribute *mcp3422_attributes[] = {
301 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
302 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
303 NULL,
304};
305
306static const struct attribute_group mcp3422_attribute_group = {
307 .attrs = mcp3422_attributes,
308};
309
310static const struct iio_chan_spec mcp3421_channels[] = {
311 MCP3422_CHAN(0),
312};
313
314static const struct iio_chan_spec mcp3422_channels[] = {
315 MCP3422_CHAN(0),
316 MCP3422_CHAN(1),
317};
318
319static const struct iio_chan_spec mcp3424_channels[] = {
320 MCP3422_CHAN(0),
321 MCP3422_CHAN(1),
322 MCP3422_CHAN(2),
323 MCP3422_CHAN(3),
324};
325
326static const struct iio_info mcp3422_info = {
327 .read_raw = mcp3422_read_raw,
328 .write_raw = mcp3422_write_raw,
329 .write_raw_get_fmt = mcp3422_write_raw_get_fmt,
330 .attrs = &mcp3422_attribute_group,
331};
332
333static int mcp3422_probe(struct i2c_client *client,
334 const struct i2c_device_id *id)
335{
336 struct iio_dev *indio_dev;
337 struct mcp3422 *adc;
338 int err;
339 u8 config;
340
341 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
342 return -EOPNOTSUPP;
343
344 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc));
345 if (!indio_dev)
346 return -ENOMEM;
347
348 adc = iio_priv(indio_dev);
349 adc->i2c = client;
350 adc->id = (u8)(id->driver_data);
351
352 mutex_init(&adc->lock);
353
354 indio_dev->name = dev_name(&client->dev);
355 indio_dev->modes = INDIO_DIRECT_MODE;
356 indio_dev->info = &mcp3422_info;
357
358 switch (adc->id) {
359 case 1:
360 case 5:
361 indio_dev->channels = mcp3421_channels;
362 indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels);
363 break;
364 case 2:
365 case 3:
366 case 6:
367 case 7:
368 indio_dev->channels = mcp3422_channels;
369 indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels);
370 break;
371 case 4:
372 case 8:
373 indio_dev->channels = mcp3424_channels;
374 indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels);
375 break;
376 }
377
378
379 config = (MCP3422_CONT_SAMPLING
380 | MCP3422_CHANNEL_VALUE(0)
381 | MCP3422_PGA_VALUE(MCP3422_PGA_1)
382 | MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240));
383 err = mcp3422_update_config(adc, config);
384 if (err < 0)
385 return err;
386
387 err = devm_iio_device_register(&client->dev, indio_dev);
388 if (err < 0)
389 return err;
390
391 i2c_set_clientdata(client, indio_dev);
392
393 return 0;
394}
395
396static const struct i2c_device_id mcp3422_id[] = {
397 { "mcp3421", 1 },
398 { "mcp3422", 2 },
399 { "mcp3423", 3 },
400 { "mcp3424", 4 },
401 { "mcp3425", 5 },
402 { "mcp3426", 6 },
403 { "mcp3427", 7 },
404 { "mcp3428", 8 },
405 { }
406};
407MODULE_DEVICE_TABLE(i2c, mcp3422_id);
408
409static const struct of_device_id mcp3422_of_match[] = {
410 { .compatible = "mcp3422" },
411 { }
412};
413MODULE_DEVICE_TABLE(of, mcp3422_of_match);
414
415static struct i2c_driver mcp3422_driver = {
416 .driver = {
417 .name = "mcp3422",
418 .of_match_table = mcp3422_of_match,
419 },
420 .probe = mcp3422_probe,
421 .id_table = mcp3422_id,
422};
423module_i2c_driver(mcp3422_driver);
424
425MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>");
426MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver");
427MODULE_LICENSE("GPL v2");
428
