linux/drivers/iio/adc/sc27xx_adc.c
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   1// SPDX-License-Identifier: GPL-2.0
   2// Copyright (C) 2018 Spreadtrum Communications Inc.
   3
   4#include <linux/hwspinlock.h>
   5#include <linux/iio/iio.h>
   6#include <linux/module.h>
   7#include <linux/nvmem-consumer.h>
   8#include <linux/of.h>
   9#include <linux/of_device.h>
  10#include <linux/platform_device.h>
  11#include <linux/regmap.h>
  12#include <linux/slab.h>
  13
  14/* PMIC global registers definition */
  15#define SC27XX_MODULE_EN                0xc08
  16#define SC27XX_MODULE_ADC_EN            BIT(5)
  17#define SC27XX_ARM_CLK_EN               0xc10
  18#define SC27XX_CLK_ADC_EN               BIT(5)
  19#define SC27XX_CLK_ADC_CLK_EN           BIT(6)
  20
  21/* ADC controller registers definition */
  22#define SC27XX_ADC_CTL                  0x0
  23#define SC27XX_ADC_CH_CFG               0x4
  24#define SC27XX_ADC_DATA                 0x4c
  25#define SC27XX_ADC_INT_EN               0x50
  26#define SC27XX_ADC_INT_CLR              0x54
  27#define SC27XX_ADC_INT_STS              0x58
  28#define SC27XX_ADC_INT_RAW              0x5c
  29
  30/* Bits and mask definition for SC27XX_ADC_CTL register */
  31#define SC27XX_ADC_EN                   BIT(0)
  32#define SC27XX_ADC_CHN_RUN              BIT(1)
  33#define SC27XX_ADC_12BIT_MODE           BIT(2)
  34#define SC27XX_ADC_RUN_NUM_MASK         GENMASK(7, 4)
  35#define SC27XX_ADC_RUN_NUM_SHIFT        4
  36
  37/* Bits and mask definition for SC27XX_ADC_CH_CFG register */
  38#define SC27XX_ADC_CHN_ID_MASK          GENMASK(4, 0)
  39#define SC27XX_ADC_SCALE_MASK           GENMASK(10, 8)
  40#define SC27XX_ADC_SCALE_SHIFT          8
  41
  42/* Bits definitions for SC27XX_ADC_INT_EN registers */
  43#define SC27XX_ADC_IRQ_EN               BIT(0)
  44
  45/* Bits definitions for SC27XX_ADC_INT_CLR registers */
  46#define SC27XX_ADC_IRQ_CLR              BIT(0)
  47
  48/* Bits definitions for SC27XX_ADC_INT_RAW registers */
  49#define SC27XX_ADC_IRQ_RAW              BIT(0)
  50
  51/* Mask definition for SC27XX_ADC_DATA register */
  52#define SC27XX_ADC_DATA_MASK            GENMASK(11, 0)
  53
  54/* Timeout (ms) for the trylock of hardware spinlocks */
  55#define SC27XX_ADC_HWLOCK_TIMEOUT       5000
  56
  57/* Timeout (us) for ADC data conversion according to ADC datasheet */
  58#define SC27XX_ADC_RDY_TIMEOUT          1000000
  59#define SC27XX_ADC_POLL_RAW_STATUS      500
  60
  61/* Maximum ADC channel number */
  62#define SC27XX_ADC_CHANNEL_MAX          32
  63
  64/* ADC voltage ratio definition */
  65#define SC27XX_VOLT_RATIO(n, d)         \
  66        (((n) << SC27XX_RATIO_NUMERATOR_OFFSET) | (d))
  67#define SC27XX_RATIO_NUMERATOR_OFFSET   16
  68#define SC27XX_RATIO_DENOMINATOR_MASK   GENMASK(15, 0)
  69
  70struct sc27xx_adc_data {
  71        struct device *dev;
  72        struct regmap *regmap;
  73        /*
  74         * One hardware spinlock to synchronize between the multiple
  75         * subsystems which will access the unique ADC controller.
  76         */
  77        struct hwspinlock *hwlock;
  78        int channel_scale[SC27XX_ADC_CHANNEL_MAX];
  79        u32 base;
  80        int irq;
  81};
  82
  83struct sc27xx_adc_linear_graph {
  84        int volt0;
  85        int adc0;
  86        int volt1;
  87        int adc1;
  88};
  89
  90/*
  91 * According to the datasheet, we can convert one ADC value to one voltage value
  92 * through 2 points in the linear graph. If the voltage is less than 1.2v, we
  93 * should use the small-scale graph, and if more than 1.2v, we should use the
  94 * big-scale graph.
  95 */
  96static struct sc27xx_adc_linear_graph big_scale_graph = {
  97        4200, 3310,
  98        3600, 2832,
  99};
 100
 101static struct sc27xx_adc_linear_graph small_scale_graph = {
 102        1000, 3413,
 103        100, 341,
 104};
 105
 106static const struct sc27xx_adc_linear_graph big_scale_graph_calib = {
 107        4200, 856,
 108        3600, 733,
 109};
 110
 111static const struct sc27xx_adc_linear_graph small_scale_graph_calib = {
 112        1000, 833,
 113        100, 80,
 114};
 115
 116static int sc27xx_adc_get_calib_data(u32 calib_data, int calib_adc)
 117{
 118        return ((calib_data & 0xff) + calib_adc - 128) * 4;
 119}
 120
 121static int sc27xx_adc_scale_calibration(struct sc27xx_adc_data *data,
 122                                        bool big_scale)
 123{
 124        const struct sc27xx_adc_linear_graph *calib_graph;
 125        struct sc27xx_adc_linear_graph *graph;
 126        struct nvmem_cell *cell;
 127        const char *cell_name;
 128        u32 calib_data = 0;
 129        void *buf;
 130        size_t len;
 131
 132        if (big_scale) {
 133                calib_graph = &big_scale_graph_calib;
 134                graph = &big_scale_graph;
 135                cell_name = "big_scale_calib";
 136        } else {
 137                calib_graph = &small_scale_graph_calib;
 138                graph = &small_scale_graph;
 139                cell_name = "small_scale_calib";
 140        }
 141
 142        cell = nvmem_cell_get(data->dev, cell_name);
 143        if (IS_ERR(cell))
 144                return PTR_ERR(cell);
 145
 146        buf = nvmem_cell_read(cell, &len);
 147        nvmem_cell_put(cell);
 148
 149        if (IS_ERR(buf))
 150                return PTR_ERR(buf);
 151
 152        memcpy(&calib_data, buf, min(len, sizeof(u32)));
 153
 154        /* Only need to calibrate the adc values in the linear graph. */
 155        graph->adc0 = sc27xx_adc_get_calib_data(calib_data, calib_graph->adc0);
 156        graph->adc1 = sc27xx_adc_get_calib_data(calib_data >> 8,
 157                                                calib_graph->adc1);
 158
 159        kfree(buf);
 160        return 0;
 161}
 162
 163static int sc27xx_adc_get_ratio(int channel, int scale)
 164{
 165        switch (channel) {
 166        case 1:
 167        case 2:
 168        case 3:
 169        case 4:
 170                return scale ? SC27XX_VOLT_RATIO(400, 1025) :
 171                        SC27XX_VOLT_RATIO(1, 1);
 172        case 5:
 173                return SC27XX_VOLT_RATIO(7, 29);
 174        case 6:
 175                return SC27XX_VOLT_RATIO(375, 9000);
 176        case 7:
 177        case 8:
 178                return scale ? SC27XX_VOLT_RATIO(100, 125) :
 179                        SC27XX_VOLT_RATIO(1, 1);
 180        case 19:
 181                return SC27XX_VOLT_RATIO(1, 3);
 182        default:
 183                return SC27XX_VOLT_RATIO(1, 1);
 184        }
 185        return SC27XX_VOLT_RATIO(1, 1);
 186}
 187
 188static int sc27xx_adc_read(struct sc27xx_adc_data *data, int channel,
 189                           int scale, int *val)
 190{
 191        int ret;
 192        u32 tmp, value, status;
 193
 194        ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT);
 195        if (ret) {
 196                dev_err(data->dev, "timeout to get the hwspinlock\n");
 197                return ret;
 198        }
 199
 200        ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
 201                                 SC27XX_ADC_EN, SC27XX_ADC_EN);
 202        if (ret)
 203                goto unlock_adc;
 204
 205        ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR,
 206                                 SC27XX_ADC_IRQ_CLR, SC27XX_ADC_IRQ_CLR);
 207        if (ret)
 208                goto disable_adc;
 209
 210        /* Configure the channel id and scale */
 211        tmp = (scale << SC27XX_ADC_SCALE_SHIFT) & SC27XX_ADC_SCALE_MASK;
 212        tmp |= channel & SC27XX_ADC_CHN_ID_MASK;
 213        ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG,
 214                                 SC27XX_ADC_CHN_ID_MASK | SC27XX_ADC_SCALE_MASK,
 215                                 tmp);
 216        if (ret)
 217                goto disable_adc;
 218
 219        /* Select 12bit conversion mode, and only sample 1 time */
 220        tmp = SC27XX_ADC_12BIT_MODE;
 221        tmp |= (0 << SC27XX_ADC_RUN_NUM_SHIFT) & SC27XX_ADC_RUN_NUM_MASK;
 222        ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
 223                                 SC27XX_ADC_RUN_NUM_MASK | SC27XX_ADC_12BIT_MODE,
 224                                 tmp);
 225        if (ret)
 226                goto disable_adc;
 227
 228        ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
 229                                 SC27XX_ADC_CHN_RUN, SC27XX_ADC_CHN_RUN);
 230        if (ret)
 231                goto disable_adc;
 232
 233        ret = regmap_read_poll_timeout(data->regmap,
 234                                       data->base + SC27XX_ADC_INT_RAW,
 235                                       status, (status & SC27XX_ADC_IRQ_RAW),
 236                                       SC27XX_ADC_POLL_RAW_STATUS,
 237                                       SC27XX_ADC_RDY_TIMEOUT);
 238        if (ret) {
 239                dev_err(data->dev, "read adc timeout, status = 0x%x\n", status);
 240                goto disable_adc;
 241        }
 242
 243        ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, &value);
 244        if (ret)
 245                goto disable_adc;
 246
 247        value &= SC27XX_ADC_DATA_MASK;
 248
 249disable_adc:
 250        regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL,
 251                           SC27XX_ADC_EN, 0);
 252unlock_adc:
 253        hwspin_unlock_raw(data->hwlock);
 254
 255        if (!ret)
 256                *val = value;
 257
 258        return ret;
 259}
 260
 261static void sc27xx_adc_volt_ratio(struct sc27xx_adc_data *data,
 262                                  int channel, int scale,
 263                                  u32 *div_numerator, u32 *div_denominator)
 264{
 265        u32 ratio = sc27xx_adc_get_ratio(channel, scale);
 266
 267        *div_numerator = ratio >> SC27XX_RATIO_NUMERATOR_OFFSET;
 268        *div_denominator = ratio & SC27XX_RATIO_DENOMINATOR_MASK;
 269}
 270
 271static int sc27xx_adc_to_volt(struct sc27xx_adc_linear_graph *graph,
 272                              int raw_adc)
 273{
 274        int tmp;
 275
 276        tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1);
 277        tmp /= (graph->adc0 - graph->adc1);
 278        tmp += graph->volt1;
 279
 280        return tmp < 0 ? 0 : tmp;
 281}
 282
 283static int sc27xx_adc_convert_volt(struct sc27xx_adc_data *data, int channel,
 284                                   int scale, int raw_adc)
 285{
 286        u32 numerator, denominator;
 287        u32 volt;
 288
 289        /*
 290         * Convert ADC values to voltage values according to the linear graph,
 291         * and channel 5 and channel 1 has been calibrated, so we can just
 292         * return the voltage values calculated by the linear graph. But other
 293         * channels need be calculated to the real voltage values with the
 294         * voltage ratio.
 295         */
 296        switch (channel) {
 297        case 5:
 298                return sc27xx_adc_to_volt(&big_scale_graph, raw_adc);
 299
 300        case 1:
 301                return sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
 302
 303        default:
 304                volt = sc27xx_adc_to_volt(&small_scale_graph, raw_adc);
 305                break;
 306        }
 307
 308        sc27xx_adc_volt_ratio(data, channel, scale, &numerator, &denominator);
 309
 310        return DIV_ROUND_CLOSEST(volt * denominator, numerator);
 311}
 312
 313static int sc27xx_adc_read_processed(struct sc27xx_adc_data *data,
 314                                     int channel, int scale, int *val)
 315{
 316        int ret, raw_adc;
 317
 318        ret = sc27xx_adc_read(data, channel, scale, &raw_adc);
 319        if (ret)
 320                return ret;
 321
 322        *val = sc27xx_adc_convert_volt(data, channel, scale, raw_adc);
 323        return 0;
 324}
 325
 326static int sc27xx_adc_read_raw(struct iio_dev *indio_dev,
 327                               struct iio_chan_spec const *chan,
 328                               int *val, int *val2, long mask)
 329{
 330        struct sc27xx_adc_data *data = iio_priv(indio_dev);
 331        int scale = data->channel_scale[chan->channel];
 332        int ret, tmp;
 333
 334        switch (mask) {
 335        case IIO_CHAN_INFO_RAW:
 336                mutex_lock(&indio_dev->mlock);
 337                ret = sc27xx_adc_read(data, chan->channel, scale, &tmp);
 338                mutex_unlock(&indio_dev->mlock);
 339
 340                if (ret)
 341                        return ret;
 342
 343                *val = tmp;
 344                return IIO_VAL_INT;
 345
 346        case IIO_CHAN_INFO_PROCESSED:
 347                mutex_lock(&indio_dev->mlock);
 348                ret = sc27xx_adc_read_processed(data, chan->channel, scale,
 349                                                &tmp);
 350                mutex_unlock(&indio_dev->mlock);
 351
 352                if (ret)
 353                        return ret;
 354
 355                *val = tmp;
 356                return IIO_VAL_INT;
 357
 358        case IIO_CHAN_INFO_SCALE:
 359                *val = scale;
 360                return IIO_VAL_INT;
 361
 362        default:
 363                return -EINVAL;
 364        }
 365}
 366
 367static int sc27xx_adc_write_raw(struct iio_dev *indio_dev,
 368                                struct iio_chan_spec const *chan,
 369                                int val, int val2, long mask)
 370{
 371        struct sc27xx_adc_data *data = iio_priv(indio_dev);
 372
 373        switch (mask) {
 374        case IIO_CHAN_INFO_SCALE:
 375                data->channel_scale[chan->channel] = val;
 376                return IIO_VAL_INT;
 377
 378        default:
 379                return -EINVAL;
 380        }
 381}
 382
 383static const struct iio_info sc27xx_info = {
 384        .read_raw = &sc27xx_adc_read_raw,
 385        .write_raw = &sc27xx_adc_write_raw,
 386};
 387
 388#define SC27XX_ADC_CHANNEL(index, mask) {                       \
 389        .type = IIO_VOLTAGE,                                    \
 390        .channel = index,                                       \
 391        .info_mask_separate = mask | BIT(IIO_CHAN_INFO_SCALE),  \
 392        .datasheet_name = "CH##index",                          \
 393        .indexed = 1,                                           \
 394}
 395
 396static const struct iio_chan_spec sc27xx_channels[] = {
 397        SC27XX_ADC_CHANNEL(0, BIT(IIO_CHAN_INFO_PROCESSED)),
 398        SC27XX_ADC_CHANNEL(1, BIT(IIO_CHAN_INFO_PROCESSED)),
 399        SC27XX_ADC_CHANNEL(2, BIT(IIO_CHAN_INFO_PROCESSED)),
 400        SC27XX_ADC_CHANNEL(3, BIT(IIO_CHAN_INFO_PROCESSED)),
 401        SC27XX_ADC_CHANNEL(4, BIT(IIO_CHAN_INFO_PROCESSED)),
 402        SC27XX_ADC_CHANNEL(5, BIT(IIO_CHAN_INFO_PROCESSED)),
 403        SC27XX_ADC_CHANNEL(6, BIT(IIO_CHAN_INFO_PROCESSED)),
 404        SC27XX_ADC_CHANNEL(7, BIT(IIO_CHAN_INFO_PROCESSED)),
 405        SC27XX_ADC_CHANNEL(8, BIT(IIO_CHAN_INFO_PROCESSED)),
 406        SC27XX_ADC_CHANNEL(9, BIT(IIO_CHAN_INFO_PROCESSED)),
 407        SC27XX_ADC_CHANNEL(10, BIT(IIO_CHAN_INFO_PROCESSED)),
 408        SC27XX_ADC_CHANNEL(11, BIT(IIO_CHAN_INFO_PROCESSED)),
 409        SC27XX_ADC_CHANNEL(12, BIT(IIO_CHAN_INFO_PROCESSED)),
 410        SC27XX_ADC_CHANNEL(13, BIT(IIO_CHAN_INFO_PROCESSED)),
 411        SC27XX_ADC_CHANNEL(14, BIT(IIO_CHAN_INFO_PROCESSED)),
 412        SC27XX_ADC_CHANNEL(15, BIT(IIO_CHAN_INFO_PROCESSED)),
 413        SC27XX_ADC_CHANNEL(16, BIT(IIO_CHAN_INFO_PROCESSED)),
 414        SC27XX_ADC_CHANNEL(17, BIT(IIO_CHAN_INFO_PROCESSED)),
 415        SC27XX_ADC_CHANNEL(18, BIT(IIO_CHAN_INFO_PROCESSED)),
 416        SC27XX_ADC_CHANNEL(19, BIT(IIO_CHAN_INFO_PROCESSED)),
 417        SC27XX_ADC_CHANNEL(20, BIT(IIO_CHAN_INFO_RAW)),
 418        SC27XX_ADC_CHANNEL(21, BIT(IIO_CHAN_INFO_PROCESSED)),
 419        SC27XX_ADC_CHANNEL(22, BIT(IIO_CHAN_INFO_PROCESSED)),
 420        SC27XX_ADC_CHANNEL(23, BIT(IIO_CHAN_INFO_PROCESSED)),
 421        SC27XX_ADC_CHANNEL(24, BIT(IIO_CHAN_INFO_PROCESSED)),
 422        SC27XX_ADC_CHANNEL(25, BIT(IIO_CHAN_INFO_PROCESSED)),
 423        SC27XX_ADC_CHANNEL(26, BIT(IIO_CHAN_INFO_PROCESSED)),
 424        SC27XX_ADC_CHANNEL(27, BIT(IIO_CHAN_INFO_PROCESSED)),
 425        SC27XX_ADC_CHANNEL(28, BIT(IIO_CHAN_INFO_PROCESSED)),
 426        SC27XX_ADC_CHANNEL(29, BIT(IIO_CHAN_INFO_PROCESSED)),
 427        SC27XX_ADC_CHANNEL(30, BIT(IIO_CHAN_INFO_PROCESSED)),
 428        SC27XX_ADC_CHANNEL(31, BIT(IIO_CHAN_INFO_PROCESSED)),
 429};
 430
 431static int sc27xx_adc_enable(struct sc27xx_adc_data *data)
 432{
 433        int ret;
 434
 435        ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
 436                                 SC27XX_MODULE_ADC_EN, SC27XX_MODULE_ADC_EN);
 437        if (ret)
 438                return ret;
 439
 440        /* Enable ADC work clock and controller clock */
 441        ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
 442                                 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN,
 443                                 SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN);
 444        if (ret)
 445                goto disable_adc;
 446
 447        /* ADC channel scales' calibration from nvmem device */
 448        ret = sc27xx_adc_scale_calibration(data, true);
 449        if (ret)
 450                goto disable_clk;
 451
 452        ret = sc27xx_adc_scale_calibration(data, false);
 453        if (ret)
 454                goto disable_clk;
 455
 456        return 0;
 457
 458disable_clk:
 459        regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
 460                           SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
 461disable_adc:
 462        regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
 463                           SC27XX_MODULE_ADC_EN, 0);
 464
 465        return ret;
 466}
 467
 468static void sc27xx_adc_disable(void *_data)
 469{
 470        struct sc27xx_adc_data *data = _data;
 471
 472        /* Disable ADC work clock and controller clock */
 473        regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN,
 474                           SC27XX_CLK_ADC_EN | SC27XX_CLK_ADC_CLK_EN, 0);
 475
 476        regmap_update_bits(data->regmap, SC27XX_MODULE_EN,
 477                           SC27XX_MODULE_ADC_EN, 0);
 478}
 479
 480static int sc27xx_adc_probe(struct platform_device *pdev)
 481{
 482        struct device *dev = &pdev->dev;
 483        struct device_node *np = dev->of_node;
 484        struct sc27xx_adc_data *sc27xx_data;
 485        struct iio_dev *indio_dev;
 486        int ret;
 487
 488        indio_dev = devm_iio_device_alloc(dev, sizeof(*sc27xx_data));
 489        if (!indio_dev)
 490                return -ENOMEM;
 491
 492        sc27xx_data = iio_priv(indio_dev);
 493
 494        sc27xx_data->regmap = dev_get_regmap(dev->parent, NULL);
 495        if (!sc27xx_data->regmap) {
 496                dev_err(dev, "failed to get ADC regmap\n");
 497                return -ENODEV;
 498        }
 499
 500        ret = of_property_read_u32(np, "reg", &sc27xx_data->base);
 501        if (ret) {
 502                dev_err(dev, "failed to get ADC base address\n");
 503                return ret;
 504        }
 505
 506        sc27xx_data->irq = platform_get_irq(pdev, 0);
 507        if (sc27xx_data->irq < 0)
 508                return sc27xx_data->irq;
 509
 510        ret = of_hwspin_lock_get_id(np, 0);
 511        if (ret < 0) {
 512                dev_err(dev, "failed to get hwspinlock id\n");
 513                return ret;
 514        }
 515
 516        sc27xx_data->hwlock = devm_hwspin_lock_request_specific(dev, ret);
 517        if (!sc27xx_data->hwlock) {
 518                dev_err(dev, "failed to request hwspinlock\n");
 519                return -ENXIO;
 520        }
 521
 522        sc27xx_data->dev = dev;
 523
 524        ret = sc27xx_adc_enable(sc27xx_data);
 525        if (ret) {
 526                dev_err(dev, "failed to enable ADC module\n");
 527                return ret;
 528        }
 529
 530        ret = devm_add_action_or_reset(dev, sc27xx_adc_disable, sc27xx_data);
 531        if (ret) {
 532                dev_err(dev, "failed to add ADC disable action\n");
 533                return ret;
 534        }
 535
 536        indio_dev->name = dev_name(dev);
 537        indio_dev->modes = INDIO_DIRECT_MODE;
 538        indio_dev->info = &sc27xx_info;
 539        indio_dev->channels = sc27xx_channels;
 540        indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels);
 541        ret = devm_iio_device_register(dev, indio_dev);
 542        if (ret)
 543                dev_err(dev, "could not register iio (ADC)");
 544
 545        return ret;
 546}
 547
 548static const struct of_device_id sc27xx_adc_of_match[] = {
 549        { .compatible = "sprd,sc2731-adc", },
 550        { }
 551};
 552MODULE_DEVICE_TABLE(of, sc27xx_adc_of_match);
 553
 554static struct platform_driver sc27xx_adc_driver = {
 555        .probe = sc27xx_adc_probe,
 556        .driver = {
 557                .name = "sc27xx-adc",
 558                .of_match_table = sc27xx_adc_of_match,
 559        },
 560};
 561
 562module_platform_driver(sc27xx_adc_driver);
 563
 564MODULE_AUTHOR("Freeman Liu <freeman.liu@spreadtrum.com>");
 565MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");
 566MODULE_LICENSE("GPL v2");
 567
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.