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5
6#include <linux/err.h>
7#include <linux/delay.h>
8#include <linux/device.h>
9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_gpio.h>
13#include <linux/slab.h>
14#include <linux/sysfs.h>
15
16#include <linux/gpio/consumer.h>
17#include <linux/spi/spi.h>
18
19#include <linux/iio/iio.h>
20#include <linux/iio/buffer.h>
21#include <linux/iio/trigger_consumer.h>
22#include <linux/iio/triggered_buffer.h>
23#include <linux/iio/sysfs.h>
24
25#include <asm/unaligned.h>
26
27
28#define ADS124S08_CMD_NOP 0x00
29#define ADS124S08_CMD_WAKEUP 0x02
30#define ADS124S08_CMD_PWRDWN 0x04
31#define ADS124S08_CMD_RESET 0x06
32#define ADS124S08_CMD_START 0x08
33#define ADS124S08_CMD_STOP 0x0a
34#define ADS124S08_CMD_SYOCAL 0x16
35#define ADS124S08_CMD_SYGCAL 0x17
36#define ADS124S08_CMD_SFOCAL 0x19
37#define ADS124S08_CMD_RDATA 0x12
38#define ADS124S08_CMD_RREG 0x20
39#define ADS124S08_CMD_WREG 0x40
40
41
42#define ADS124S08_ID_REG 0x00
43#define ADS124S08_STATUS 0x01
44#define ADS124S08_INPUT_MUX 0x02
45#define ADS124S08_PGA 0x03
46#define ADS124S08_DATA_RATE 0x04
47#define ADS124S08_REF 0x05
48#define ADS124S08_IDACMAG 0x06
49#define ADS124S08_IDACMUX 0x07
50#define ADS124S08_VBIAS 0x08
51#define ADS124S08_SYS 0x09
52#define ADS124S08_OFCAL0 0x0a
53#define ADS124S08_OFCAL1 0x0b
54#define ADS124S08_OFCAL2 0x0c
55#define ADS124S08_FSCAL0 0x0d
56#define ADS124S08_FSCAL1 0x0e
57#define ADS124S08_FSCAL2 0x0f
58#define ADS124S08_GPIODAT 0x10
59#define ADS124S08_GPIOCON 0x11
60
61
62#define ADS124S08_AIN0 0x00
63#define ADS124S08_AIN1 0x01
64#define ADS124S08_AIN2 0x02
65#define ADS124S08_AIN3 0x03
66#define ADS124S08_AIN4 0x04
67#define ADS124S08_AIN5 0x05
68#define ADS124S08_AINCOM 0x0c
69
70#define ADS124S08_AIN6 0x06
71#define ADS124S08_AIN7 0x07
72#define ADS124S08_AIN8 0x08
73#define ADS124S08_AIN9 0x09
74#define ADS124S08_AIN10 0x0a
75#define ADS124S08_AIN11 0x0b
76#define ADS124S08_MAX_CHANNELS 12
77
78#define ADS124S08_POS_MUX_SHIFT 0x04
79#define ADS124S08_INT_REF 0x09
80
81#define ADS124S08_START_REG_MASK 0x1f
82#define ADS124S08_NUM_BYTES_MASK 0x1f
83
84#define ADS124S08_START_CONV 0x01
85#define ADS124S08_STOP_CONV 0x00
86
87enum ads124s_id {
88 ADS124S08_ID,
89 ADS124S06_ID,
90};
91
92struct ads124s_chip_info {
93 const struct iio_chan_spec *channels;
94 unsigned int num_channels;
95};
96
97struct ads124s_private {
98 const struct ads124s_chip_info *chip_info;
99 struct gpio_desc *reset_gpio;
100 struct spi_device *spi;
101 struct mutex lock;
102
103
104
105
106
107
108
109 u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8);
110 u8 data[5] ____cacheline_aligned;
111};
112
113#define ADS124S08_CHAN(index) \
114{ \
115 .type = IIO_VOLTAGE, \
116 .indexed = 1, \
117 .channel = index, \
118 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
119 .scan_index = index, \
120 .scan_type = { \
121 .sign = 'u', \
122 .realbits = 32, \
123 .storagebits = 32, \
124 }, \
125}
126
127static const struct iio_chan_spec ads124s06_channels[] = {
128 ADS124S08_CHAN(0),
129 ADS124S08_CHAN(1),
130 ADS124S08_CHAN(2),
131 ADS124S08_CHAN(3),
132 ADS124S08_CHAN(4),
133 ADS124S08_CHAN(5),
134};
135
136static const struct iio_chan_spec ads124s08_channels[] = {
137 ADS124S08_CHAN(0),
138 ADS124S08_CHAN(1),
139 ADS124S08_CHAN(2),
140 ADS124S08_CHAN(3),
141 ADS124S08_CHAN(4),
142 ADS124S08_CHAN(5),
143 ADS124S08_CHAN(6),
144 ADS124S08_CHAN(7),
145 ADS124S08_CHAN(8),
146 ADS124S08_CHAN(9),
147 ADS124S08_CHAN(10),
148 ADS124S08_CHAN(11),
149};
150
151static const struct ads124s_chip_info ads124s_chip_info_tbl[] = {
152 [ADS124S08_ID] = {
153 .channels = ads124s08_channels,
154 .num_channels = ARRAY_SIZE(ads124s08_channels),
155 },
156 [ADS124S06_ID] = {
157 .channels = ads124s06_channels,
158 .num_channels = ARRAY_SIZE(ads124s06_channels),
159 },
160};
161
162static int ads124s_write_cmd(struct iio_dev *indio_dev, u8 command)
163{
164 struct ads124s_private *priv = iio_priv(indio_dev);
165
166 priv->data[0] = command;
167
168 return spi_write(priv->spi, &priv->data[0], 1);
169}
170
171static int ads124s_write_reg(struct iio_dev *indio_dev, u8 reg, u8 data)
172{
173 struct ads124s_private *priv = iio_priv(indio_dev);
174
175 priv->data[0] = ADS124S08_CMD_WREG | reg;
176 priv->data[1] = 0x0;
177 priv->data[2] = data;
178
179 return spi_write(priv->spi, &priv->data[0], 3);
180}
181
182static int ads124s_reset(struct iio_dev *indio_dev)
183{
184 struct ads124s_private *priv = iio_priv(indio_dev);
185
186 if (priv->reset_gpio) {
187 gpiod_set_value(priv->reset_gpio, 0);
188 udelay(200);
189 gpiod_set_value(priv->reset_gpio, 1);
190 } else {
191 return ads124s_write_cmd(indio_dev, ADS124S08_CMD_RESET);
192 }
193
194 return 0;
195};
196
197static int ads124s_read(struct iio_dev *indio_dev, unsigned int chan)
198{
199 struct ads124s_private *priv = iio_priv(indio_dev);
200 int ret;
201 struct spi_transfer t[] = {
202 {
203 .tx_buf = &priv->data[0],
204 .len = 4,
205 .cs_change = 1,
206 }, {
207 .tx_buf = &priv->data[1],
208 .rx_buf = &priv->data[1],
209 .len = 4,
210 },
211 };
212
213 priv->data[0] = ADS124S08_CMD_RDATA;
214 memset(&priv->data[1], ADS124S08_CMD_NOP, sizeof(priv->data) - 1);
215
216 ret = spi_sync_transfer(priv->spi, t, ARRAY_SIZE(t));
217 if (ret < 0)
218 return ret;
219
220 return get_unaligned_be24(&priv->data[2]);
221}
222
223static int ads124s_read_raw(struct iio_dev *indio_dev,
224 struct iio_chan_spec const *chan,
225 int *val, int *val2, long m)
226{
227 struct ads124s_private *priv = iio_priv(indio_dev);
228 int ret;
229
230 mutex_lock(&priv->lock);
231 switch (m) {
232 case IIO_CHAN_INFO_RAW:
233 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
234 chan->channel);
235 if (ret) {
236 dev_err(&priv->spi->dev, "Set ADC CH failed\n");
237 goto out;
238 }
239
240 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
241 if (ret) {
242 dev_err(&priv->spi->dev, "Start conversions failed\n");
243 goto out;
244 }
245
246 ret = ads124s_read(indio_dev, chan->channel);
247 if (ret < 0) {
248 dev_err(&priv->spi->dev, "Read ADC failed\n");
249 goto out;
250 }
251
252 *val = ret;
253
254 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
255 if (ret) {
256 dev_err(&priv->spi->dev, "Stop conversions failed\n");
257 goto out;
258 }
259
260 ret = IIO_VAL_INT;
261 break;
262 default:
263 ret = -EINVAL;
264 break;
265 }
266out:
267 mutex_unlock(&priv->lock);
268 return ret;
269}
270
271static const struct iio_info ads124s_info = {
272 .read_raw = &ads124s_read_raw,
273};
274
275static irqreturn_t ads124s_trigger_handler(int irq, void *p)
276{
277 struct iio_poll_func *pf = p;
278 struct iio_dev *indio_dev = pf->indio_dev;
279 struct ads124s_private *priv = iio_priv(indio_dev);
280 int scan_index, j = 0;
281 int ret;
282
283 for_each_set_bit(scan_index, indio_dev->active_scan_mask,
284 indio_dev->masklength) {
285 ret = ads124s_write_reg(indio_dev, ADS124S08_INPUT_MUX,
286 scan_index);
287 if (ret)
288 dev_err(&priv->spi->dev, "Set ADC CH failed\n");
289
290 ret = ads124s_write_cmd(indio_dev, ADS124S08_START_CONV);
291 if (ret)
292 dev_err(&priv->spi->dev, "Start ADC conversions failed\n");
293
294 priv->buffer[j] = ads124s_read(indio_dev, scan_index);
295 ret = ads124s_write_cmd(indio_dev, ADS124S08_STOP_CONV);
296 if (ret)
297 dev_err(&priv->spi->dev, "Stop ADC conversions failed\n");
298
299 j++;
300 }
301
302 iio_push_to_buffers_with_timestamp(indio_dev, priv->buffer,
303 pf->timestamp);
304
305 iio_trigger_notify_done(indio_dev->trig);
306
307 return IRQ_HANDLED;
308}
309
310static int ads124s_probe(struct spi_device *spi)
311{
312 struct ads124s_private *ads124s_priv;
313 struct iio_dev *indio_dev;
314 const struct spi_device_id *spi_id = spi_get_device_id(spi);
315 int ret;
316
317 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*ads124s_priv));
318 if (indio_dev == NULL)
319 return -ENOMEM;
320
321 ads124s_priv = iio_priv(indio_dev);
322
323 ads124s_priv->reset_gpio = devm_gpiod_get_optional(&spi->dev,
324 "reset", GPIOD_OUT_LOW);
325 if (IS_ERR(ads124s_priv->reset_gpio))
326 dev_info(&spi->dev, "Reset GPIO not defined\n");
327
328 ads124s_priv->chip_info = &ads124s_chip_info_tbl[spi_id->driver_data];
329
330 ads124s_priv->spi = spi;
331
332 indio_dev->name = spi_id->name;
333 indio_dev->modes = INDIO_DIRECT_MODE;
334 indio_dev->channels = ads124s_priv->chip_info->channels;
335 indio_dev->num_channels = ads124s_priv->chip_info->num_channels;
336 indio_dev->info = &ads124s_info;
337
338 mutex_init(&ads124s_priv->lock);
339
340 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL,
341 ads124s_trigger_handler, NULL);
342 if (ret) {
343 dev_err(&spi->dev, "iio triggered buffer setup failed\n");
344 return ret;
345 }
346
347 ads124s_reset(indio_dev);
348
349 return devm_iio_device_register(&spi->dev, indio_dev);
350}
351
352static const struct spi_device_id ads124s_id[] = {
353 { "ads124s06", ADS124S06_ID },
354 { "ads124s08", ADS124S08_ID },
355 { }
356};
357MODULE_DEVICE_TABLE(spi, ads124s_id);
358
359static const struct of_device_id ads124s_of_table[] = {
360 { .compatible = "ti,ads124s06" },
361 { .compatible = "ti,ads124s08" },
362 { },
363};
364MODULE_DEVICE_TABLE(of, ads124s_of_table);
365
366static struct spi_driver ads124s_driver = {
367 .driver = {
368 .name = "ads124s08",
369 .of_match_table = ads124s_of_table,
370 },
371 .probe = ads124s_probe,
372 .id_table = ads124s_id,
373};
374module_spi_driver(ads124s_driver);
375
376MODULE_AUTHOR("Dan Murphy <dmuprhy@ti.com>");
377MODULE_DESCRIPTION("TI TI_ADS12S0X ADC");
378MODULE_LICENSE("GPL v2");
379
