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14#include <linux/clk.h>
15#include <linux/device.h>
16#include <linux/err.h>
17#include <linux/interrupt.h>
18#include <linux/io.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/overflow.h>
23#include <linux/platform_device.h>
24#include <linux/slab.h>
25#include <linux/sysfs.h>
26
27#include <linux/iio/buffer.h>
28#include <linux/iio/events.h>
29#include <linux/iio/iio.h>
30#include <linux/iio/sysfs.h>
31#include <linux/iio/trigger.h>
32#include <linux/iio/trigger_consumer.h>
33#include <linux/iio/triggered_buffer.h>
34
35#include "xilinx-xadc.h"
36
37static const unsigned int XADC_ZYNQ_UNMASK_TIMEOUT = 500;
38
39
40#define XADC_ZYNQ_REG_CFG 0x00
41#define XADC_ZYNQ_REG_INTSTS 0x04
42#define XADC_ZYNQ_REG_INTMSK 0x08
43#define XADC_ZYNQ_REG_STATUS 0x0c
44#define XADC_ZYNQ_REG_CFIFO 0x10
45#define XADC_ZYNQ_REG_DFIFO 0x14
46#define XADC_ZYNQ_REG_CTL 0x18
47
48#define XADC_ZYNQ_CFG_ENABLE BIT(31)
49#define XADC_ZYNQ_CFG_CFIFOTH_MASK (0xf << 20)
50#define XADC_ZYNQ_CFG_CFIFOTH_OFFSET 20
51#define XADC_ZYNQ_CFG_DFIFOTH_MASK (0xf << 16)
52#define XADC_ZYNQ_CFG_DFIFOTH_OFFSET 16
53#define XADC_ZYNQ_CFG_WEDGE BIT(13)
54#define XADC_ZYNQ_CFG_REDGE BIT(12)
55#define XADC_ZYNQ_CFG_TCKRATE_MASK (0x3 << 8)
56#define XADC_ZYNQ_CFG_TCKRATE_DIV2 (0x0 << 8)
57#define XADC_ZYNQ_CFG_TCKRATE_DIV4 (0x1 << 8)
58#define XADC_ZYNQ_CFG_TCKRATE_DIV8 (0x2 << 8)
59#define XADC_ZYNQ_CFG_TCKRATE_DIV16 (0x3 << 8)
60#define XADC_ZYNQ_CFG_IGAP_MASK 0x1f
61#define XADC_ZYNQ_CFG_IGAP(x) (x)
62
63#define XADC_ZYNQ_INT_CFIFO_LTH BIT(9)
64#define XADC_ZYNQ_INT_DFIFO_GTH BIT(8)
65#define XADC_ZYNQ_INT_ALARM_MASK 0xff
66#define XADC_ZYNQ_INT_ALARM_OFFSET 0
67
68#define XADC_ZYNQ_STATUS_CFIFO_LVL_MASK (0xf << 16)
69#define XADC_ZYNQ_STATUS_CFIFO_LVL_OFFSET 16
70#define XADC_ZYNQ_STATUS_DFIFO_LVL_MASK (0xf << 12)
71#define XADC_ZYNQ_STATUS_DFIFO_LVL_OFFSET 12
72#define XADC_ZYNQ_STATUS_CFIFOF BIT(11)
73#define XADC_ZYNQ_STATUS_CFIFOE BIT(10)
74#define XADC_ZYNQ_STATUS_DFIFOF BIT(9)
75#define XADC_ZYNQ_STATUS_DFIFOE BIT(8)
76#define XADC_ZYNQ_STATUS_OT BIT(7)
77#define XADC_ZYNQ_STATUS_ALM(x) BIT(x)
78
79#define XADC_ZYNQ_CTL_RESET BIT(4)
80
81#define XADC_ZYNQ_CMD_NOP 0x00
82#define XADC_ZYNQ_CMD_READ 0x01
83#define XADC_ZYNQ_CMD_WRITE 0x02
84
85#define XADC_ZYNQ_CMD(cmd, addr, data) (((cmd) << 26) | ((addr) << 16) | (data))
86
87
88#define XADC_AXI_REG_RESET 0x00
89#define XADC_AXI_REG_STATUS 0x04
90#define XADC_AXI_REG_ALARM_STATUS 0x08
91#define XADC_AXI_REG_CONVST 0x0c
92#define XADC_AXI_REG_XADC_RESET 0x10
93#define XADC_AXI_REG_GIER 0x5c
94#define XADC_AXI_REG_IPISR 0x60
95#define XADC_AXI_REG_IPIER 0x68
96
97
98#define XADC_7S_AXI_ADC_REG_OFFSET 0x200
99
100
101#define XADC_US_AXI_ADC_REG_OFFSET 0x400
102
103#define XADC_AXI_RESET_MAGIC 0xa
104#define XADC_AXI_GIER_ENABLE BIT(31)
105
106#define XADC_AXI_INT_EOS BIT(4)
107#define XADC_AXI_INT_ALARM_MASK 0x3c0f
108
109#define XADC_FLAGS_BUFFERED BIT(0)
110
111
112
113
114
115
116
117
118
119#define XADC_MAX_SAMPLERATE 150000
120
121static void xadc_write_reg(struct xadc *xadc, unsigned int reg,
122 uint32_t val)
123{
124 writel(val, xadc->base + reg);
125}
126
127static void xadc_read_reg(struct xadc *xadc, unsigned int reg,
128 uint32_t *val)
129{
130 *val = readl(xadc->base + reg);
131}
132
133
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139
140
141
142
143static void xadc_zynq_write_fifo(struct xadc *xadc, uint32_t *cmd,
144 unsigned int n)
145{
146 unsigned int i;
147
148 for (i = 0; i < n; i++)
149 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFIFO, cmd[i]);
150}
151
152static void xadc_zynq_drain_fifo(struct xadc *xadc)
153{
154 uint32_t status, tmp;
155
156 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
157
158 while (!(status & XADC_ZYNQ_STATUS_DFIFOE)) {
159 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
160 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &status);
161 }
162}
163
164static void xadc_zynq_update_intmsk(struct xadc *xadc, unsigned int mask,
165 unsigned int val)
166{
167 xadc->zynq_intmask &= ~mask;
168 xadc->zynq_intmask |= val;
169
170 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK,
171 xadc->zynq_intmask | xadc->zynq_masked_alarm);
172}
173
174static int xadc_zynq_write_adc_reg(struct xadc *xadc, unsigned int reg,
175 uint16_t val)
176{
177 uint32_t cmd[1];
178 uint32_t tmp;
179 int ret;
180
181 spin_lock_irq(&xadc->lock);
182 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
183 XADC_ZYNQ_INT_DFIFO_GTH);
184
185 reinit_completion(&xadc->completion);
186
187 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_WRITE, reg, val);
188 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
189 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
190 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
191 tmp |= 0 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
192 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
193
194 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
195 spin_unlock_irq(&xadc->lock);
196
197 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
198 if (ret == 0)
199 ret = -EIO;
200 else
201 ret = 0;
202
203 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &tmp);
204
205 return ret;
206}
207
208static int xadc_zynq_read_adc_reg(struct xadc *xadc, unsigned int reg,
209 uint16_t *val)
210{
211 uint32_t cmd[2];
212 uint32_t resp, tmp;
213 int ret;
214
215 cmd[0] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_READ, reg, 0);
216 cmd[1] = XADC_ZYNQ_CMD(XADC_ZYNQ_CMD_NOP, 0, 0);
217
218 spin_lock_irq(&xadc->lock);
219 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
220 XADC_ZYNQ_INT_DFIFO_GTH);
221 xadc_zynq_drain_fifo(xadc);
222 reinit_completion(&xadc->completion);
223
224 xadc_zynq_write_fifo(xadc, cmd, ARRAY_SIZE(cmd));
225 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &tmp);
226 tmp &= ~XADC_ZYNQ_CFG_DFIFOTH_MASK;
227 tmp |= 1 << XADC_ZYNQ_CFG_DFIFOTH_OFFSET;
228 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, tmp);
229
230 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH, 0);
231 spin_unlock_irq(&xadc->lock);
232 ret = wait_for_completion_interruptible_timeout(&xadc->completion, HZ);
233 if (ret == 0)
234 ret = -EIO;
235 if (ret < 0)
236 return ret;
237
238 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
239 xadc_read_reg(xadc, XADC_ZYNQ_REG_DFIFO, &resp);
240
241 *val = resp & 0xffff;
242
243 return 0;
244}
245
246static unsigned int xadc_zynq_transform_alarm(unsigned int alarm)
247{
248 return ((alarm & 0x80) >> 4) |
249 ((alarm & 0x78) << 1) |
250 (alarm & 0x07);
251}
252
253
254
255
256
257
258
259
260
261static void xadc_zynq_unmask_worker(struct work_struct *work)
262{
263 struct xadc *xadc = container_of(work, struct xadc, zynq_unmask_work.work);
264 unsigned int misc_sts, unmask;
265
266 xadc_read_reg(xadc, XADC_ZYNQ_REG_STATUS, &misc_sts);
267
268 misc_sts &= XADC_ZYNQ_INT_ALARM_MASK;
269
270 spin_lock_irq(&xadc->lock);
271
272
273 unmask = (xadc->zynq_masked_alarm ^ misc_sts) & xadc->zynq_masked_alarm;
274 xadc->zynq_masked_alarm &= misc_sts;
275
276
277 xadc->zynq_masked_alarm &= ~xadc->zynq_intmask;
278
279
280 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, unmask);
281
282 xadc_zynq_update_intmsk(xadc, 0, 0);
283
284 spin_unlock_irq(&xadc->lock);
285
286
287 if (xadc->zynq_masked_alarm) {
288 schedule_delayed_work(&xadc->zynq_unmask_work,
289 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
290 }
291
292}
293
294static irqreturn_t xadc_zynq_interrupt_handler(int irq, void *devid)
295{
296 struct iio_dev *indio_dev = devid;
297 struct xadc *xadc = iio_priv(indio_dev);
298 uint32_t status;
299
300 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
301
302 status &= ~(xadc->zynq_intmask | xadc->zynq_masked_alarm);
303
304 if (!status)
305 return IRQ_NONE;
306
307 spin_lock(&xadc->lock);
308
309 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status);
310
311 if (status & XADC_ZYNQ_INT_DFIFO_GTH) {
312 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_DFIFO_GTH,
313 XADC_ZYNQ_INT_DFIFO_GTH);
314 complete(&xadc->completion);
315 }
316
317 status &= XADC_ZYNQ_INT_ALARM_MASK;
318 if (status) {
319 xadc->zynq_masked_alarm |= status;
320
321
322
323
324 xadc_zynq_update_intmsk(xadc, 0, 0);
325
326 xadc_handle_events(indio_dev,
327 xadc_zynq_transform_alarm(status));
328
329
330 schedule_delayed_work(&xadc->zynq_unmask_work,
331 msecs_to_jiffies(XADC_ZYNQ_UNMASK_TIMEOUT));
332 }
333 spin_unlock(&xadc->lock);
334
335 return IRQ_HANDLED;
336}
337
338#define XADC_ZYNQ_TCK_RATE_MAX 50000000
339#define XADC_ZYNQ_IGAP_DEFAULT 20
340#define XADC_ZYNQ_PCAP_RATE_MAX 200000000
341
342static int xadc_zynq_setup(struct platform_device *pdev,
343 struct iio_dev *indio_dev, int irq)
344{
345 struct xadc *xadc = iio_priv(indio_dev);
346 unsigned long pcap_rate;
347 unsigned int tck_div;
348 unsigned int div;
349 unsigned int igap;
350 unsigned int tck_rate;
351 int ret;
352
353
354 igap = XADC_ZYNQ_IGAP_DEFAULT;
355 tck_rate = XADC_ZYNQ_TCK_RATE_MAX;
356
357 xadc->zynq_intmask = ~0;
358
359 pcap_rate = clk_get_rate(xadc->clk);
360 if (!pcap_rate)
361 return -EINVAL;
362
363 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
364 ret = clk_set_rate(xadc->clk,
365 (unsigned long)XADC_ZYNQ_PCAP_RATE_MAX);
366 if (ret)
367 return ret;
368 }
369
370 if (tck_rate > pcap_rate / 2) {
371 div = 2;
372 } else {
373 div = pcap_rate / tck_rate;
374 if (pcap_rate / div > XADC_ZYNQ_TCK_RATE_MAX)
375 div++;
376 }
377
378 if (div <= 3)
379 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV2;
380 else if (div <= 7)
381 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV4;
382 else if (div <= 15)
383 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV8;
384 else
385 tck_div = XADC_ZYNQ_CFG_TCKRATE_DIV16;
386
387 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, XADC_ZYNQ_CTL_RESET);
388 xadc_write_reg(xadc, XADC_ZYNQ_REG_CTL, 0);
389 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, ~0);
390 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTMSK, xadc->zynq_intmask);
391 xadc_write_reg(xadc, XADC_ZYNQ_REG_CFG, XADC_ZYNQ_CFG_ENABLE |
392 XADC_ZYNQ_CFG_REDGE | XADC_ZYNQ_CFG_WEDGE |
393 tck_div | XADC_ZYNQ_CFG_IGAP(igap));
394
395 if (pcap_rate > XADC_ZYNQ_PCAP_RATE_MAX) {
396 ret = clk_set_rate(xadc->clk, pcap_rate);
397 if (ret)
398 return ret;
399 }
400
401 return 0;
402}
403
404static unsigned long xadc_zynq_get_dclk_rate(struct xadc *xadc)
405{
406 unsigned int div;
407 uint32_t val;
408
409 xadc_read_reg(xadc, XADC_ZYNQ_REG_CFG, &val);
410
411 switch (val & XADC_ZYNQ_CFG_TCKRATE_MASK) {
412 case XADC_ZYNQ_CFG_TCKRATE_DIV4:
413 div = 4;
414 break;
415 case XADC_ZYNQ_CFG_TCKRATE_DIV8:
416 div = 8;
417 break;
418 case XADC_ZYNQ_CFG_TCKRATE_DIV16:
419 div = 16;
420 break;
421 default:
422 div = 2;
423 break;
424 }
425
426 return clk_get_rate(xadc->clk) / div;
427}
428
429static void xadc_zynq_update_alarm(struct xadc *xadc, unsigned int alarm)
430{
431 unsigned long flags;
432 uint32_t status;
433
434
435 alarm = ((alarm & 0x08) << 4) | ((alarm & 0xf0) >> 1) | (alarm & 0x07);
436
437 spin_lock_irqsave(&xadc->lock, flags);
438
439
440 xadc_read_reg(xadc, XADC_ZYNQ_REG_INTSTS, &status);
441 xadc_write_reg(xadc, XADC_ZYNQ_REG_INTSTS, status & alarm);
442
443 xadc_zynq_update_intmsk(xadc, XADC_ZYNQ_INT_ALARM_MASK,
444 ~alarm & XADC_ZYNQ_INT_ALARM_MASK);
445
446 spin_unlock_irqrestore(&xadc->lock, flags);
447}
448
449static const struct xadc_ops xadc_zynq_ops = {
450 .read = xadc_zynq_read_adc_reg,
451 .write = xadc_zynq_write_adc_reg,
452 .setup = xadc_zynq_setup,
453 .get_dclk_rate = xadc_zynq_get_dclk_rate,
454 .interrupt_handler = xadc_zynq_interrupt_handler,
455 .update_alarm = xadc_zynq_update_alarm,
456 .type = XADC_TYPE_S7,
457};
458
459static const unsigned int xadc_axi_reg_offsets[] = {
460 [XADC_TYPE_S7] = XADC_7S_AXI_ADC_REG_OFFSET,
461 [XADC_TYPE_US] = XADC_US_AXI_ADC_REG_OFFSET,
462};
463
464static int xadc_axi_read_adc_reg(struct xadc *xadc, unsigned int reg,
465 uint16_t *val)
466{
467 uint32_t val32;
468
469 xadc_read_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
470 &val32);
471 *val = val32 & 0xffff;
472
473 return 0;
474}
475
476static int xadc_axi_write_adc_reg(struct xadc *xadc, unsigned int reg,
477 uint16_t val)
478{
479 xadc_write_reg(xadc, xadc_axi_reg_offsets[xadc->ops->type] + reg * 4,
480 val);
481
482 return 0;
483}
484
485static int xadc_axi_setup(struct platform_device *pdev,
486 struct iio_dev *indio_dev, int irq)
487{
488 struct xadc *xadc = iio_priv(indio_dev);
489
490 xadc_write_reg(xadc, XADC_AXI_REG_RESET, XADC_AXI_RESET_MAGIC);
491 xadc_write_reg(xadc, XADC_AXI_REG_GIER, XADC_AXI_GIER_ENABLE);
492
493 return 0;
494}
495
496static irqreturn_t xadc_axi_interrupt_handler(int irq, void *devid)
497{
498 struct iio_dev *indio_dev = devid;
499 struct xadc *xadc = iio_priv(indio_dev);
500 uint32_t status, mask;
501 unsigned int events;
502
503 xadc_read_reg(xadc, XADC_AXI_REG_IPISR, &status);
504 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &mask);
505 status &= mask;
506
507 if (!status)
508 return IRQ_NONE;
509
510 if ((status & XADC_AXI_INT_EOS) && xadc->trigger)
511 iio_trigger_poll(xadc->trigger);
512
513 if (status & XADC_AXI_INT_ALARM_MASK) {
514
515
516
517
518
519
520 events = (status & 0x000e) >> 1;
521 events |= (status & 0x0001) << 3;
522 events |= (status & 0x3c00) >> 6;
523 xadc_handle_events(indio_dev, events);
524 }
525
526 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, status);
527
528 return IRQ_HANDLED;
529}
530
531static void xadc_axi_update_alarm(struct xadc *xadc, unsigned int alarm)
532{
533 uint32_t val;
534 unsigned long flags;
535
536
537
538
539
540
541
542 alarm = ((alarm & 0x07) << 1) | ((alarm & 0x08) >> 3) |
543 ((alarm & 0xf0) << 6);
544
545 spin_lock_irqsave(&xadc->lock, flags);
546 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
547 val &= ~XADC_AXI_INT_ALARM_MASK;
548 val |= alarm;
549 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
550 spin_unlock_irqrestore(&xadc->lock, flags);
551}
552
553static unsigned long xadc_axi_get_dclk(struct xadc *xadc)
554{
555 return clk_get_rate(xadc->clk);
556}
557
558static const struct xadc_ops xadc_7s_axi_ops = {
559 .read = xadc_axi_read_adc_reg,
560 .write = xadc_axi_write_adc_reg,
561 .setup = xadc_axi_setup,
562 .get_dclk_rate = xadc_axi_get_dclk,
563 .update_alarm = xadc_axi_update_alarm,
564 .interrupt_handler = xadc_axi_interrupt_handler,
565 .flags = XADC_FLAGS_BUFFERED,
566 .type = XADC_TYPE_S7,
567};
568
569static const struct xadc_ops xadc_us_axi_ops = {
570 .read = xadc_axi_read_adc_reg,
571 .write = xadc_axi_write_adc_reg,
572 .setup = xadc_axi_setup,
573 .get_dclk_rate = xadc_axi_get_dclk,
574 .update_alarm = xadc_axi_update_alarm,
575 .interrupt_handler = xadc_axi_interrupt_handler,
576 .flags = XADC_FLAGS_BUFFERED,
577 .type = XADC_TYPE_US,
578};
579
580static int _xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
581 uint16_t mask, uint16_t val)
582{
583 uint16_t tmp;
584 int ret;
585
586 ret = _xadc_read_adc_reg(xadc, reg, &tmp);
587 if (ret)
588 return ret;
589
590 return _xadc_write_adc_reg(xadc, reg, (tmp & ~mask) | val);
591}
592
593static int xadc_update_adc_reg(struct xadc *xadc, unsigned int reg,
594 uint16_t mask, uint16_t val)
595{
596 int ret;
597
598 mutex_lock(&xadc->mutex);
599 ret = _xadc_update_adc_reg(xadc, reg, mask, val);
600 mutex_unlock(&xadc->mutex);
601
602 return ret;
603}
604
605static unsigned long xadc_get_dclk_rate(struct xadc *xadc)
606{
607 return xadc->ops->get_dclk_rate(xadc);
608}
609
610static int xadc_update_scan_mode(struct iio_dev *indio_dev,
611 const unsigned long *mask)
612{
613 struct xadc *xadc = iio_priv(indio_dev);
614 size_t new_size, n;
615 void *data;
616
617 n = bitmap_weight(mask, indio_dev->masklength);
618
619 if (check_mul_overflow(n, sizeof(*xadc->data), &new_size))
620 return -ENOMEM;
621
622 data = devm_krealloc(indio_dev->dev.parent, xadc->data,
623 new_size, GFP_KERNEL);
624 if (!data)
625 return -ENOMEM;
626
627 memset(data, 0, new_size);
628 xadc->data = data;
629
630 return 0;
631}
632
633static unsigned int xadc_scan_index_to_channel(unsigned int scan_index)
634{
635 switch (scan_index) {
636 case 5:
637 return XADC_REG_VCCPINT;
638 case 6:
639 return XADC_REG_VCCPAUX;
640 case 7:
641 return XADC_REG_VCCO_DDR;
642 case 8:
643 return XADC_REG_TEMP;
644 case 9:
645 return XADC_REG_VCCINT;
646 case 10:
647 return XADC_REG_VCCAUX;
648 case 11:
649 return XADC_REG_VPVN;
650 case 12:
651 return XADC_REG_VREFP;
652 case 13:
653 return XADC_REG_VREFN;
654 case 14:
655 return XADC_REG_VCCBRAM;
656 default:
657 return XADC_REG_VAUX(scan_index - 16);
658 }
659}
660
661static irqreturn_t xadc_trigger_handler(int irq, void *p)
662{
663 struct iio_poll_func *pf = p;
664 struct iio_dev *indio_dev = pf->indio_dev;
665 struct xadc *xadc = iio_priv(indio_dev);
666 unsigned int chan;
667 int i, j;
668
669 if (!xadc->data)
670 goto out;
671
672 j = 0;
673 for_each_set_bit(i, indio_dev->active_scan_mask,
674 indio_dev->masklength) {
675 chan = xadc_scan_index_to_channel(i);
676 xadc_read_adc_reg(xadc, chan, &xadc->data[j]);
677 j++;
678 }
679
680 iio_push_to_buffers(indio_dev, xadc->data);
681
682out:
683 iio_trigger_notify_done(indio_dev->trig);
684
685 return IRQ_HANDLED;
686}
687
688static int xadc_trigger_set_state(struct iio_trigger *trigger, bool state)
689{
690 struct xadc *xadc = iio_trigger_get_drvdata(trigger);
691 unsigned long flags;
692 unsigned int convst;
693 unsigned int val;
694 int ret = 0;
695
696 mutex_lock(&xadc->mutex);
697
698 if (state) {
699
700 if (xadc->trigger != NULL) {
701 ret = -EBUSY;
702 goto err_out;
703 } else {
704 xadc->trigger = trigger;
705 if (trigger == xadc->convst_trigger)
706 convst = XADC_CONF0_EC;
707 else
708 convst = 0;
709 }
710 ret = _xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF0_EC,
711 convst);
712 if (ret)
713 goto err_out;
714 } else {
715 xadc->trigger = NULL;
716 }
717
718 spin_lock_irqsave(&xadc->lock, flags);
719 xadc_read_reg(xadc, XADC_AXI_REG_IPIER, &val);
720 xadc_write_reg(xadc, XADC_AXI_REG_IPISR, XADC_AXI_INT_EOS);
721 if (state)
722 val |= XADC_AXI_INT_EOS;
723 else
724 val &= ~XADC_AXI_INT_EOS;
725 xadc_write_reg(xadc, XADC_AXI_REG_IPIER, val);
726 spin_unlock_irqrestore(&xadc->lock, flags);
727
728err_out:
729 mutex_unlock(&xadc->mutex);
730
731 return ret;
732}
733
734static const struct iio_trigger_ops xadc_trigger_ops = {
735 .set_trigger_state = &xadc_trigger_set_state,
736};
737
738static struct iio_trigger *xadc_alloc_trigger(struct iio_dev *indio_dev,
739 const char *name)
740{
741 struct device *dev = indio_dev->dev.parent;
742 struct iio_trigger *trig;
743 int ret;
744
745 trig = devm_iio_trigger_alloc(dev, "%s%d-%s", indio_dev->name,
746 iio_device_id(indio_dev), name);
747 if (trig == NULL)
748 return ERR_PTR(-ENOMEM);
749
750 trig->ops = &xadc_trigger_ops;
751 iio_trigger_set_drvdata(trig, iio_priv(indio_dev));
752
753 ret = devm_iio_trigger_register(dev, trig);
754 if (ret)
755 return ERR_PTR(ret);
756
757 return trig;
758}
759
760static int xadc_power_adc_b(struct xadc *xadc, unsigned int seq_mode)
761{
762 uint16_t val;
763
764
765
766
767
768
769
770 if (xadc->ops->type == XADC_TYPE_US)
771 return 0;
772
773
774 switch (seq_mode) {
775 case XADC_CONF1_SEQ_SIMULTANEOUS:
776 case XADC_CONF1_SEQ_INDEPENDENT:
777 val = 0;
778 break;
779 default:
780 val = XADC_CONF2_PD_ADC_B;
781 break;
782 }
783
784 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_PD_MASK,
785 val);
786}
787
788static int xadc_get_seq_mode(struct xadc *xadc, unsigned long scan_mode)
789{
790 unsigned int aux_scan_mode = scan_mode >> 16;
791
792
793 if (xadc->ops->type == XADC_TYPE_US)
794 return XADC_CONF1_SEQ_CONTINUOUS;
795
796 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_DUAL)
797 return XADC_CONF1_SEQ_SIMULTANEOUS;
798
799 if ((aux_scan_mode & 0xff00) == 0 ||
800 (aux_scan_mode & 0x00ff) == 0)
801 return XADC_CONF1_SEQ_CONTINUOUS;
802
803 return XADC_CONF1_SEQ_SIMULTANEOUS;
804}
805
806static int xadc_postdisable(struct iio_dev *indio_dev)
807{
808 struct xadc *xadc = iio_priv(indio_dev);
809 unsigned long scan_mask;
810 int ret;
811 int i;
812
813 scan_mask = 1;
814 for (i = 0; i < indio_dev->num_channels; i++)
815 scan_mask |= BIT(indio_dev->channels[i].scan_index);
816
817
818 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
819 if (ret)
820 return ret;
821
822 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
823 if (ret)
824 return ret;
825
826 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
827 XADC_CONF1_SEQ_CONTINUOUS);
828 if (ret)
829 return ret;
830
831 return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
832}
833
834static int xadc_preenable(struct iio_dev *indio_dev)
835{
836 struct xadc *xadc = iio_priv(indio_dev);
837 unsigned long scan_mask;
838 int seq_mode;
839 int ret;
840
841 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
842 XADC_CONF1_SEQ_DEFAULT);
843 if (ret)
844 goto err;
845
846 scan_mask = *indio_dev->active_scan_mask;
847 seq_mode = xadc_get_seq_mode(xadc, scan_mask);
848
849 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
850 if (ret)
851 goto err;
852
853
854
855
856
857
858
859
860 if (seq_mode == XADC_CONF1_SEQ_SIMULTANEOUS)
861 scan_mask = ((scan_mask >> 8) | scan_mask) & 0xff0000;
862
863 ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(1), scan_mask >> 16);
864 if (ret)
865 goto err;
866
867 ret = xadc_power_adc_b(xadc, seq_mode);
868 if (ret)
869 goto err;
870
871 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
872 seq_mode);
873 if (ret)
874 goto err;
875
876 return 0;
877err:
878 xadc_postdisable(indio_dev);
879 return ret;
880}
881
882static const struct iio_buffer_setup_ops xadc_buffer_ops = {
883 .preenable = &xadc_preenable,
884 .postdisable = &xadc_postdisable,
885};
886
887static int xadc_read_samplerate(struct xadc *xadc)
888{
889 unsigned int div;
890 uint16_t val16;
891 int ret;
892
893 ret = xadc_read_adc_reg(xadc, XADC_REG_CONF2, &val16);
894 if (ret)
895 return ret;
896
897 div = (val16 & XADC_CONF2_DIV_MASK) >> XADC_CONF2_DIV_OFFSET;
898 if (div < 2)
899 div = 2;
900
901 return xadc_get_dclk_rate(xadc) / div / 26;
902}
903
904static int xadc_read_raw(struct iio_dev *indio_dev,
905 struct iio_chan_spec const *chan, int *val, int *val2, long info)
906{
907 struct xadc *xadc = iio_priv(indio_dev);
908 unsigned int bits = chan->scan_type.realbits;
909 uint16_t val16;
910 int ret;
911
912 switch (info) {
913 case IIO_CHAN_INFO_RAW:
914 if (iio_buffer_enabled(indio_dev))
915 return -EBUSY;
916 ret = xadc_read_adc_reg(xadc, chan->address, &val16);
917 if (ret < 0)
918 return ret;
919
920 val16 >>= chan->scan_type.shift;
921 if (chan->scan_type.sign == 'u')
922 *val = val16;
923 else
924 *val = sign_extend32(val16, bits - 1);
925
926 return IIO_VAL_INT;
927 case IIO_CHAN_INFO_SCALE:
928 switch (chan->type) {
929 case IIO_VOLTAGE:
930
931 switch (chan->address) {
932 case XADC_REG_VCCINT:
933 case XADC_REG_VCCAUX:
934 case XADC_REG_VREFP:
935 case XADC_REG_VREFN:
936 case XADC_REG_VCCBRAM:
937 case XADC_REG_VCCPINT:
938 case XADC_REG_VCCPAUX:
939 case XADC_REG_VCCO_DDR:
940 *val = 3000;
941 break;
942 default:
943 *val = 1000;
944 break;
945 }
946 *val2 = chan->scan_type.realbits;
947 return IIO_VAL_FRACTIONAL_LOG2;
948 case IIO_TEMP:
949
950 *val = 503975;
951 *val2 = bits;
952 return IIO_VAL_FRACTIONAL_LOG2;
953 default:
954 return -EINVAL;
955 }
956 case IIO_CHAN_INFO_OFFSET:
957
958 *val = -((273150 << bits) / 503975);
959 return IIO_VAL_INT;
960 case IIO_CHAN_INFO_SAMP_FREQ:
961 ret = xadc_read_samplerate(xadc);
962 if (ret < 0)
963 return ret;
964
965 *val = ret;
966 return IIO_VAL_INT;
967 default:
968 return -EINVAL;
969 }
970}
971
972static int xadc_write_samplerate(struct xadc *xadc, int val)
973{
974 unsigned long clk_rate = xadc_get_dclk_rate(xadc);
975 unsigned int div;
976
977 if (!clk_rate)
978 return -EINVAL;
979
980 if (val <= 0)
981 return -EINVAL;
982
983
984 if (val > XADC_MAX_SAMPLERATE)
985 val = XADC_MAX_SAMPLERATE;
986
987 val *= 26;
988
989
990 if (val < 1000000)
991 val = 1000000;
992
993
994
995
996
997 div = clk_rate / val;
998 if (clk_rate / div / 26 > XADC_MAX_SAMPLERATE)
999 div++;
1000 if (div < 2)
1001 div = 2;
1002 else if (div > 0xff)
1003 div = 0xff;
1004
1005 return xadc_update_adc_reg(xadc, XADC_REG_CONF2, XADC_CONF2_DIV_MASK,
1006 div << XADC_CONF2_DIV_OFFSET);
1007}
1008
1009static int xadc_write_raw(struct iio_dev *indio_dev,
1010 struct iio_chan_spec const *chan, int val, int val2, long info)
1011{
1012 struct xadc *xadc = iio_priv(indio_dev);
1013
1014 if (info != IIO_CHAN_INFO_SAMP_FREQ)
1015 return -EINVAL;
1016
1017 return xadc_write_samplerate(xadc, val);
1018}
1019
1020static const struct iio_event_spec xadc_temp_events[] = {
1021 {
1022 .type = IIO_EV_TYPE_THRESH,
1023 .dir = IIO_EV_DIR_RISING,
1024 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
1025 BIT(IIO_EV_INFO_VALUE) |
1026 BIT(IIO_EV_INFO_HYSTERESIS),
1027 },
1028};
1029
1030
1031static const struct iio_event_spec xadc_voltage_events[] = {
1032 {
1033 .type = IIO_EV_TYPE_THRESH,
1034 .dir = IIO_EV_DIR_RISING,
1035 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1036 }, {
1037 .type = IIO_EV_TYPE_THRESH,
1038 .dir = IIO_EV_DIR_FALLING,
1039 .mask_separate = BIT(IIO_EV_INFO_VALUE),
1040 }, {
1041 .type = IIO_EV_TYPE_THRESH,
1042 .dir = IIO_EV_DIR_EITHER,
1043 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1044 },
1045};
1046
1047#define XADC_CHAN_TEMP(_chan, _scan_index, _addr, _bits) { \
1048 .type = IIO_TEMP, \
1049 .indexed = 1, \
1050 .channel = (_chan), \
1051 .address = (_addr), \
1052 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1053 BIT(IIO_CHAN_INFO_SCALE) | \
1054 BIT(IIO_CHAN_INFO_OFFSET), \
1055 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1056 .event_spec = xadc_temp_events, \
1057 .num_event_specs = ARRAY_SIZE(xadc_temp_events), \
1058 .scan_index = (_scan_index), \
1059 .scan_type = { \
1060 .sign = 'u', \
1061 .realbits = (_bits), \
1062 .storagebits = 16, \
1063 .shift = 16 - (_bits), \
1064 .endianness = IIO_CPU, \
1065 }, \
1066}
1067
1068#define XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, _bits, _ext, _alarm) { \
1069 .type = IIO_VOLTAGE, \
1070 .indexed = 1, \
1071 .channel = (_chan), \
1072 .address = (_addr), \
1073 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1074 BIT(IIO_CHAN_INFO_SCALE), \
1075 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1076 .event_spec = (_alarm) ? xadc_voltage_events : NULL, \
1077 .num_event_specs = (_alarm) ? ARRAY_SIZE(xadc_voltage_events) : 0, \
1078 .scan_index = (_scan_index), \
1079 .scan_type = { \
1080 .sign = ((_addr) == XADC_REG_VREFN) ? 's' : 'u', \
1081 .realbits = (_bits), \
1082 .storagebits = 16, \
1083 .shift = 16 - (_bits), \
1084 .endianness = IIO_CPU, \
1085 }, \
1086 .extend_name = _ext, \
1087}
1088
1089
1090#define XADC_7S_CHAN_TEMP(_chan, _scan_index, _addr) \
1091 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 12)
1092#define XADC_7S_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1093 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 12, _ext, _alarm)
1094
1095static const struct iio_chan_spec xadc_7s_channels[] = {
1096 XADC_7S_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1097 XADC_7S_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1098 XADC_7S_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1099 XADC_7S_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1100 XADC_7S_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpint", true),
1101 XADC_7S_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpaux", true),
1102 XADC_7S_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccoddr", true),
1103 XADC_7S_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1104 XADC_7S_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1105 XADC_7S_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1106 XADC_7S_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1107 XADC_7S_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1108 XADC_7S_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1109 XADC_7S_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1110 XADC_7S_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1111 XADC_7S_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1112 XADC_7S_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1113 XADC_7S_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1114 XADC_7S_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1115 XADC_7S_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1116 XADC_7S_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1117 XADC_7S_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1118 XADC_7S_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1119 XADC_7S_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1120 XADC_7S_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1121 XADC_7S_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1122};
1123
1124
1125#define XADC_US_CHAN_TEMP(_chan, _scan_index, _addr) \
1126 XADC_CHAN_TEMP(_chan, _scan_index, _addr, 10)
1127#define XADC_US_CHAN_VOLTAGE(_chan, _scan_index, _addr, _ext, _alarm) \
1128 XADC_CHAN_VOLTAGE(_chan, _scan_index, _addr, 10, _ext, _alarm)
1129
1130static const struct iio_chan_spec xadc_us_channels[] = {
1131 XADC_US_CHAN_TEMP(0, 8, XADC_REG_TEMP),
1132 XADC_US_CHAN_VOLTAGE(0, 9, XADC_REG_VCCINT, "vccint", true),
1133 XADC_US_CHAN_VOLTAGE(1, 10, XADC_REG_VCCAUX, "vccaux", true),
1134 XADC_US_CHAN_VOLTAGE(2, 14, XADC_REG_VCCBRAM, "vccbram", true),
1135 XADC_US_CHAN_VOLTAGE(3, 5, XADC_REG_VCCPINT, "vccpsintlp", true),
1136 XADC_US_CHAN_VOLTAGE(4, 6, XADC_REG_VCCPAUX, "vccpsintfp", true),
1137 XADC_US_CHAN_VOLTAGE(5, 7, XADC_REG_VCCO_DDR, "vccpsaux", true),
1138 XADC_US_CHAN_VOLTAGE(6, 12, XADC_REG_VREFP, "vrefp", false),
1139 XADC_US_CHAN_VOLTAGE(7, 13, XADC_REG_VREFN, "vrefn", false),
1140 XADC_US_CHAN_VOLTAGE(8, 11, XADC_REG_VPVN, NULL, false),
1141 XADC_US_CHAN_VOLTAGE(9, 16, XADC_REG_VAUX(0), NULL, false),
1142 XADC_US_CHAN_VOLTAGE(10, 17, XADC_REG_VAUX(1), NULL, false),
1143 XADC_US_CHAN_VOLTAGE(11, 18, XADC_REG_VAUX(2), NULL, false),
1144 XADC_US_CHAN_VOLTAGE(12, 19, XADC_REG_VAUX(3), NULL, false),
1145 XADC_US_CHAN_VOLTAGE(13, 20, XADC_REG_VAUX(4), NULL, false),
1146 XADC_US_CHAN_VOLTAGE(14, 21, XADC_REG_VAUX(5), NULL, false),
1147 XADC_US_CHAN_VOLTAGE(15, 22, XADC_REG_VAUX(6), NULL, false),
1148 XADC_US_CHAN_VOLTAGE(16, 23, XADC_REG_VAUX(7), NULL, false),
1149 XADC_US_CHAN_VOLTAGE(17, 24, XADC_REG_VAUX(8), NULL, false),
1150 XADC_US_CHAN_VOLTAGE(18, 25, XADC_REG_VAUX(9), NULL, false),
1151 XADC_US_CHAN_VOLTAGE(19, 26, XADC_REG_VAUX(10), NULL, false),
1152 XADC_US_CHAN_VOLTAGE(20, 27, XADC_REG_VAUX(11), NULL, false),
1153 XADC_US_CHAN_VOLTAGE(21, 28, XADC_REG_VAUX(12), NULL, false),
1154 XADC_US_CHAN_VOLTAGE(22, 29, XADC_REG_VAUX(13), NULL, false),
1155 XADC_US_CHAN_VOLTAGE(23, 30, XADC_REG_VAUX(14), NULL, false),
1156 XADC_US_CHAN_VOLTAGE(24, 31, XADC_REG_VAUX(15), NULL, false),
1157};
1158
1159static const struct iio_info xadc_info = {
1160 .read_raw = &xadc_read_raw,
1161 .write_raw = &xadc_write_raw,
1162 .read_event_config = &xadc_read_event_config,
1163 .write_event_config = &xadc_write_event_config,
1164 .read_event_value = &xadc_read_event_value,
1165 .write_event_value = &xadc_write_event_value,
1166 .update_scan_mode = &xadc_update_scan_mode,
1167};
1168
1169static const struct of_device_id xadc_of_match_table[] = {
1170 {
1171 .compatible = "xlnx,zynq-xadc-1.00.a",
1172 .data = &xadc_zynq_ops
1173 }, {
1174 .compatible = "xlnx,axi-xadc-1.00.a",
1175 .data = &xadc_7s_axi_ops
1176 }, {
1177 .compatible = "xlnx,system-management-wiz-1.3",
1178 .data = &xadc_us_axi_ops
1179 },
1180 { },
1181};
1182MODULE_DEVICE_TABLE(of, xadc_of_match_table);
1183
1184static int xadc_parse_dt(struct iio_dev *indio_dev, struct device_node *np,
1185 unsigned int *conf)
1186{
1187 struct device *dev = indio_dev->dev.parent;
1188 struct xadc *xadc = iio_priv(indio_dev);
1189 const struct iio_chan_spec *channel_templates;
1190 struct iio_chan_spec *channels, *chan;
1191 struct device_node *chan_node, *child;
1192 unsigned int max_channels;
1193 unsigned int num_channels;
1194 const char *external_mux;
1195 u32 ext_mux_chan;
1196 u32 reg;
1197 int ret;
1198
1199 *conf = 0;
1200
1201 ret = of_property_read_string(np, "xlnx,external-mux", &external_mux);
1202 if (ret < 0 || strcasecmp(external_mux, "none") == 0)
1203 xadc->external_mux_mode = XADC_EXTERNAL_MUX_NONE;
1204 else if (strcasecmp(external_mux, "single") == 0)
1205 xadc->external_mux_mode = XADC_EXTERNAL_MUX_SINGLE;
1206 else if (strcasecmp(external_mux, "dual") == 0)
1207 xadc->external_mux_mode = XADC_EXTERNAL_MUX_DUAL;
1208 else
1209 return -EINVAL;
1210
1211 if (xadc->external_mux_mode != XADC_EXTERNAL_MUX_NONE) {
1212 ret = of_property_read_u32(np, "xlnx,external-mux-channel",
1213 &ext_mux_chan);
1214 if (ret < 0)
1215 return ret;
1216
1217 if (xadc->external_mux_mode == XADC_EXTERNAL_MUX_SINGLE) {
1218 if (ext_mux_chan == 0)
1219 ext_mux_chan = XADC_REG_VPVN;
1220 else if (ext_mux_chan <= 16)
1221 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1222 else
1223 return -EINVAL;
1224 } else {
1225 if (ext_mux_chan > 0 && ext_mux_chan <= 8)
1226 ext_mux_chan = XADC_REG_VAUX(ext_mux_chan - 1);
1227 else
1228 return -EINVAL;
1229 }
1230
1231 *conf |= XADC_CONF0_MUX | XADC_CONF0_CHAN(ext_mux_chan);
1232 }
1233 if (xadc->ops->type == XADC_TYPE_S7) {
1234 channel_templates = xadc_7s_channels;
1235 max_channels = ARRAY_SIZE(xadc_7s_channels);
1236 } else {
1237 channel_templates = xadc_us_channels;
1238 max_channels = ARRAY_SIZE(xadc_us_channels);
1239 }
1240 channels = devm_kmemdup(dev, channel_templates,
1241 sizeof(channels[0]) * max_channels, GFP_KERNEL);
1242 if (!channels)
1243 return -ENOMEM;
1244
1245 num_channels = 9;
1246 chan = &channels[9];
1247
1248 chan_node = of_get_child_by_name(np, "xlnx,channels");
1249 if (chan_node) {
1250 for_each_child_of_node(chan_node, child) {
1251 if (num_channels >= max_channels) {
1252 of_node_put(child);
1253 break;
1254 }
1255
1256 ret = of_property_read_u32(child, "reg", ®);
1257 if (ret || reg > 16)
1258 continue;
1259
1260 if (of_property_read_bool(child, "xlnx,bipolar"))
1261 chan->scan_type.sign = 's';
1262
1263 if (reg == 0) {
1264 chan->scan_index = 11;
1265 chan->address = XADC_REG_VPVN;
1266 } else {
1267 chan->scan_index = 15 + reg;
1268 chan->address = XADC_REG_VAUX(reg - 1);
1269 }
1270 num_channels++;
1271 chan++;
1272 }
1273 }
1274 of_node_put(chan_node);
1275
1276 indio_dev->num_channels = num_channels;
1277 indio_dev->channels = devm_krealloc(dev, channels,
1278 sizeof(*channels) * num_channels,
1279 GFP_KERNEL);
1280
1281 if (!indio_dev->channels)
1282 indio_dev->channels = channels;
1283
1284 return 0;
1285}
1286
1287static const char * const xadc_type_names[] = {
1288 [XADC_TYPE_S7] = "xadc",
1289 [XADC_TYPE_US] = "xilinx-system-monitor",
1290};
1291
1292static void xadc_clk_disable_unprepare(void *data)
1293{
1294 struct clk *clk = data;
1295
1296 clk_disable_unprepare(clk);
1297}
1298
1299static void xadc_cancel_delayed_work(void *data)
1300{
1301 struct delayed_work *work = data;
1302
1303 cancel_delayed_work_sync(work);
1304}
1305
1306static int xadc_probe(struct platform_device *pdev)
1307{
1308 struct device *dev = &pdev->dev;
1309 const struct of_device_id *id;
1310 struct iio_dev *indio_dev;
1311 unsigned int bipolar_mask;
1312 unsigned int conf0;
1313 struct xadc *xadc;
1314 int ret;
1315 int irq;
1316 int i;
1317
1318 if (!dev->of_node)
1319 return -ENODEV;
1320
1321 id = of_match_node(xadc_of_match_table, dev->of_node);
1322 if (!id)
1323 return -EINVAL;
1324
1325 irq = platform_get_irq(pdev, 0);
1326 if (irq <= 0)
1327 return -ENXIO;
1328
1329 indio_dev = devm_iio_device_alloc(dev, sizeof(*xadc));
1330 if (!indio_dev)
1331 return -ENOMEM;
1332
1333 xadc = iio_priv(indio_dev);
1334 xadc->ops = id->data;
1335 xadc->irq = irq;
1336 init_completion(&xadc->completion);
1337 mutex_init(&xadc->mutex);
1338 spin_lock_init(&xadc->lock);
1339 INIT_DELAYED_WORK(&xadc->zynq_unmask_work, xadc_zynq_unmask_worker);
1340
1341 xadc->base = devm_platform_ioremap_resource(pdev, 0);
1342 if (IS_ERR(xadc->base))
1343 return PTR_ERR(xadc->base);
1344
1345 indio_dev->name = xadc_type_names[xadc->ops->type];
1346 indio_dev->modes = INDIO_DIRECT_MODE;
1347 indio_dev->info = &xadc_info;
1348
1349 ret = xadc_parse_dt(indio_dev, dev->of_node, &conf0);
1350 if (ret)
1351 return ret;
1352
1353 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1354 ret = devm_iio_triggered_buffer_setup(dev, indio_dev,
1355 &iio_pollfunc_store_time,
1356 &xadc_trigger_handler,
1357 &xadc_buffer_ops);
1358 if (ret)
1359 return ret;
1360
1361 xadc->convst_trigger = xadc_alloc_trigger(indio_dev, "convst");
1362 if (IS_ERR(xadc->convst_trigger))
1363 return PTR_ERR(xadc->convst_trigger);
1364
1365 xadc->samplerate_trigger = xadc_alloc_trigger(indio_dev,
1366 "samplerate");
1367 if (IS_ERR(xadc->samplerate_trigger))
1368 return PTR_ERR(xadc->samplerate_trigger);
1369 }
1370
1371 xadc->clk = devm_clk_get(dev, NULL);
1372 if (IS_ERR(xadc->clk))
1373 return PTR_ERR(xadc->clk);
1374
1375 ret = clk_prepare_enable(xadc->clk);
1376 if (ret)
1377 return ret;
1378
1379 ret = devm_add_action_or_reset(dev,
1380 xadc_clk_disable_unprepare, xadc->clk);
1381 if (ret)
1382 return ret;
1383
1384
1385
1386
1387
1388 if (xadc->ops->flags & XADC_FLAGS_BUFFERED) {
1389 ret = xadc_read_samplerate(xadc);
1390 if (ret < 0)
1391 return ret;
1392
1393 if (ret > XADC_MAX_SAMPLERATE) {
1394 ret = xadc_write_samplerate(xadc, XADC_MAX_SAMPLERATE);
1395 if (ret < 0)
1396 return ret;
1397 }
1398 }
1399
1400 ret = devm_request_irq(dev, xadc->irq, xadc->ops->interrupt_handler, 0,
1401 dev_name(dev), indio_dev);
1402 if (ret)
1403 return ret;
1404
1405 ret = devm_add_action_or_reset(dev, xadc_cancel_delayed_work,
1406 &xadc->zynq_unmask_work);
1407 if (ret)
1408 return ret;
1409
1410 ret = xadc->ops->setup(pdev, indio_dev, xadc->irq);
1411 if (ret)
1412 return ret;
1413
1414 for (i = 0; i < 16; i++)
1415 xadc_read_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1416 &xadc->threshold[i]);
1417
1418 ret = xadc_write_adc_reg(xadc, XADC_REG_CONF0, conf0);
1419 if (ret)
1420 return ret;
1421
1422 bipolar_mask = 0;
1423 for (i = 0; i < indio_dev->num_channels; i++) {
1424 if (indio_dev->channels[i].scan_type.sign == 's')
1425 bipolar_mask |= BIT(indio_dev->channels[i].scan_index);
1426 }
1427
1428 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(0), bipolar_mask);
1429 if (ret)
1430 return ret;
1431
1432 ret = xadc_write_adc_reg(xadc, XADC_REG_INPUT_MODE(1),
1433 bipolar_mask >> 16);
1434 if (ret)
1435 return ret;
1436
1437
1438 ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_ALARM_MASK,
1439 XADC_CONF1_ALARM_MASK);
1440 if (ret)
1441 return ret;
1442
1443
1444 for (i = 0; i < 16; i++) {
1445
1446
1447
1448
1449 if (i % 8 < 4 || i == 7)
1450 xadc->threshold[i] = 0xffff;
1451 else
1452 xadc->threshold[i] = 0;
1453 ret = xadc_write_adc_reg(xadc, XADC_REG_THRESHOLD(i),
1454 xadc->threshold[i]);
1455 if (ret)
1456 return ret;
1457 }
1458
1459
1460 xadc_postdisable(indio_dev);
1461
1462 return devm_iio_device_register(dev, indio_dev);
1463}
1464
1465static struct platform_driver xadc_driver = {
1466 .probe = xadc_probe,
1467 .driver = {
1468 .name = "xadc",
1469 .of_match_table = xadc_of_match_table,
1470 },
1471};
1472module_platform_driver(xadc_driver);
1473
1474MODULE_LICENSE("GPL v2");
1475MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1476MODULE_DESCRIPTION("Xilinx XADC IIO driver");
1477
