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9#ifndef __IIO_XILINX_XADC__
10#define __IIO_XILINX_XADC__
11
12#include <linux/interrupt.h>
13#include <linux/mutex.h>
14#include <linux/spinlock.h>
15
16struct iio_dev;
17struct clk;
18struct xadc_ops;
19struct platform_device;
20
21void xadc_handle_events(struct iio_dev *indio_dev, unsigned long events);
22
23int xadc_read_event_config(struct iio_dev *indio_dev,
24 const struct iio_chan_spec *chan, enum iio_event_type type,
25 enum iio_event_direction dir);
26int xadc_write_event_config(struct iio_dev *indio_dev,
27 const struct iio_chan_spec *chan, enum iio_event_type type,
28 enum iio_event_direction dir, int state);
29int xadc_read_event_value(struct iio_dev *indio_dev,
30 const struct iio_chan_spec *chan, enum iio_event_type type,
31 enum iio_event_direction dir, enum iio_event_info info,
32 int *val, int *val2);
33int xadc_write_event_value(struct iio_dev *indio_dev,
34 const struct iio_chan_spec *chan, enum iio_event_type type,
35 enum iio_event_direction dir, enum iio_event_info info,
36 int val, int val2);
37
38enum xadc_external_mux_mode {
39 XADC_EXTERNAL_MUX_NONE,
40 XADC_EXTERNAL_MUX_SINGLE,
41 XADC_EXTERNAL_MUX_DUAL,
42};
43
44struct xadc {
45 void __iomem *base;
46 struct clk *clk;
47
48 const struct xadc_ops *ops;
49
50 uint16_t threshold[16];
51 uint16_t temp_hysteresis;
52 unsigned int alarm_mask;
53
54 uint16_t *data;
55
56 struct iio_trigger *trigger;
57 struct iio_trigger *convst_trigger;
58 struct iio_trigger *samplerate_trigger;
59
60 enum xadc_external_mux_mode external_mux_mode;
61
62 unsigned int zynq_masked_alarm;
63 unsigned int zynq_intmask;
64 struct delayed_work zynq_unmask_work;
65
66 struct mutex mutex;
67 spinlock_t lock;
68
69 struct completion completion;
70 int irq;
71};
72
73enum xadc_type {
74 XADC_TYPE_S7,
75 XADC_TYPE_US,
76};
77
78struct xadc_ops {
79 int (*read)(struct xadc *xadc, unsigned int reg, uint16_t *val);
80 int (*write)(struct xadc *xadc, unsigned int reg, uint16_t val);
81 int (*setup)(struct platform_device *pdev, struct iio_dev *indio_dev,
82 int irq);
83 void (*update_alarm)(struct xadc *xadc, unsigned int alarm);
84 unsigned long (*get_dclk_rate)(struct xadc *xadc);
85 irqreturn_t (*interrupt_handler)(int irq, void *devid);
86
87 unsigned int flags;
88 enum xadc_type type;
89};
90
91static inline int _xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
92 uint16_t *val)
93{
94 lockdep_assert_held(&xadc->mutex);
95 return xadc->ops->read(xadc, reg, val);
96}
97
98static inline int _xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
99 uint16_t val)
100{
101 lockdep_assert_held(&xadc->mutex);
102 return xadc->ops->write(xadc, reg, val);
103}
104
105static inline int xadc_read_adc_reg(struct xadc *xadc, unsigned int reg,
106 uint16_t *val)
107{
108 int ret;
109
110 mutex_lock(&xadc->mutex);
111 ret = _xadc_read_adc_reg(xadc, reg, val);
112 mutex_unlock(&xadc->mutex);
113 return ret;
114}
115
116static inline int xadc_write_adc_reg(struct xadc *xadc, unsigned int reg,
117 uint16_t val)
118{
119 int ret;
120
121 mutex_lock(&xadc->mutex);
122 ret = _xadc_write_adc_reg(xadc, reg, val);
123 mutex_unlock(&xadc->mutex);
124 return ret;
125}
126
127
128#define XADC_REG_TEMP 0x00
129#define XADC_REG_VCCINT 0x01
130#define XADC_REG_VCCAUX 0x02
131#define XADC_REG_VPVN 0x03
132#define XADC_REG_VREFP 0x04
133#define XADC_REG_VREFN 0x05
134#define XADC_REG_VCCBRAM 0x06
135
136#define XADC_REG_VCCPINT 0x0d
137#define XADC_REG_VCCPAUX 0x0e
138#define XADC_REG_VCCO_DDR 0x0f
139#define XADC_REG_VAUX(x) (0x10 + (x))
140
141#define XADC_REG_MAX_TEMP 0x20
142#define XADC_REG_MAX_VCCINT 0x21
143#define XADC_REG_MAX_VCCAUX 0x22
144#define XADC_REG_MAX_VCCBRAM 0x23
145#define XADC_REG_MIN_TEMP 0x24
146#define XADC_REG_MIN_VCCINT 0x25
147#define XADC_REG_MIN_VCCAUX 0x26
148#define XADC_REG_MIN_VCCBRAM 0x27
149#define XADC_REG_MAX_VCCPINT 0x28
150#define XADC_REG_MAX_VCCPAUX 0x29
151#define XADC_REG_MAX_VCCO_DDR 0x2a
152#define XADC_REG_MIN_VCCPINT 0x2c
153#define XADC_REG_MIN_VCCPAUX 0x2d
154#define XADC_REG_MIN_VCCO_DDR 0x2e
155
156#define XADC_REG_CONF0 0x40
157#define XADC_REG_CONF1 0x41
158#define XADC_REG_CONF2 0x42
159#define XADC_REG_SEQ(x) (0x48 + (x))
160#define XADC_REG_INPUT_MODE(x) (0x4c + (x))
161#define XADC_REG_THRESHOLD(x) (0x50 + (x))
162
163#define XADC_REG_FLAG 0x3f
164
165#define XADC_CONF0_EC BIT(9)
166#define XADC_CONF0_ACQ BIT(8)
167#define XADC_CONF0_MUX BIT(11)
168#define XADC_CONF0_CHAN(x) (x)
169
170#define XADC_CONF1_SEQ_MASK (0xf << 12)
171#define XADC_CONF1_SEQ_DEFAULT (0 << 12)
172#define XADC_CONF1_SEQ_SINGLE_PASS (1 << 12)
173#define XADC_CONF1_SEQ_CONTINUOUS (2 << 12)
174#define XADC_CONF1_SEQ_SINGLE_CHANNEL (3 << 12)
175#define XADC_CONF1_SEQ_SIMULTANEOUS (4 << 12)
176#define XADC_CONF1_SEQ_INDEPENDENT (8 << 12)
177#define XADC_CONF1_ALARM_MASK 0x0f0f
178
179#define XADC_CONF2_DIV_MASK 0xff00
180#define XADC_CONF2_DIV_OFFSET 8
181
182#define XADC_CONF2_PD_MASK (0x3 << 4)
183#define XADC_CONF2_PD_NONE (0x0 << 4)
184#define XADC_CONF2_PD_ADC_B (0x2 << 4)
185#define XADC_CONF2_PD_BOTH (0x3 << 4)
186
187#define XADC_ALARM_TEMP_MASK BIT(0)
188#define XADC_ALARM_VCCINT_MASK BIT(1)
189#define XADC_ALARM_VCCAUX_MASK BIT(2)
190#define XADC_ALARM_OT_MASK BIT(3)
191#define XADC_ALARM_VCCBRAM_MASK BIT(4)
192#define XADC_ALARM_VCCPINT_MASK BIT(5)
193#define XADC_ALARM_VCCPAUX_MASK BIT(6)
194#define XADC_ALARM_VCCODDR_MASK BIT(7)
195
196#define XADC_THRESHOLD_TEMP_MAX 0x0
197#define XADC_THRESHOLD_VCCINT_MAX 0x1
198#define XADC_THRESHOLD_VCCAUX_MAX 0x2
199#define XADC_THRESHOLD_OT_MAX 0x3
200#define XADC_THRESHOLD_TEMP_MIN 0x4
201#define XADC_THRESHOLD_VCCINT_MIN 0x5
202#define XADC_THRESHOLD_VCCAUX_MIN 0x6
203#define XADC_THRESHOLD_OT_MIN 0x7
204#define XADC_THRESHOLD_VCCBRAM_MAX 0x8
205#define XADC_THRESHOLD_VCCPINT_MAX 0x9
206#define XADC_THRESHOLD_VCCPAUX_MAX 0xa
207#define XADC_THRESHOLD_VCCODDR_MAX 0xb
208#define XADC_THRESHOLD_VCCBRAM_MIN 0xc
209#define XADC_THRESHOLD_VCCPINT_MIN 0xd
210#define XADC_THRESHOLD_VCCPAUX_MIN 0xe
211#define XADC_THRESHOLD_VCCODDR_MIN 0xf
212
213#endif
214
