1
2
3
4
5
6
7
8
9#include <linux/bitfield.h>
10#include <linux/delay.h>
11#include <linux/device.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/spi/spi.h>
15
16#include <linux/iio/buffer.h>
17#include <linux/iio/iio.h>
18#include <linux/iio/sysfs.h>
19#include <linux/iio/trigger.h>
20#include <linux/iio/triggered_buffer.h>
21#include <linux/iio/trigger_consumer.h>
22
23#define ADXRS290_ADI_ID 0xAD
24#define ADXRS290_MEMS_ID 0x1D
25#define ADXRS290_DEV_ID 0x92
26
27#define ADXRS290_REG_ADI_ID 0x00
28#define ADXRS290_REG_MEMS_ID 0x01
29#define ADXRS290_REG_DEV_ID 0x02
30#define ADXRS290_REG_REV_ID 0x03
31#define ADXRS290_REG_SN0 0x04
32#define ADXRS290_REG_DATAX0 0x08
33#define ADXRS290_REG_DATAY0 0x0A
34#define ADXRS290_REG_TEMP0 0x0C
35#define ADXRS290_REG_POWER_CTL 0x10
36#define ADXRS290_REG_FILTER 0x11
37#define ADXRS290_REG_DATA_RDY 0x12
38
39#define ADXRS290_READ BIT(7)
40#define ADXRS290_TSM BIT(0)
41#define ADXRS290_MEASUREMENT BIT(1)
42#define ADXRS290_DATA_RDY_OUT BIT(0)
43#define ADXRS290_SYNC_MASK GENMASK(1, 0)
44#define ADXRS290_SYNC(x) FIELD_PREP(ADXRS290_SYNC_MASK, x)
45#define ADXRS290_LPF_MASK GENMASK(2, 0)
46#define ADXRS290_LPF(x) FIELD_PREP(ADXRS290_LPF_MASK, x)
47#define ADXRS290_HPF_MASK GENMASK(7, 4)
48#define ADXRS290_HPF(x) FIELD_PREP(ADXRS290_HPF_MASK, x)
49
50#define ADXRS290_READ_REG(reg) (ADXRS290_READ | (reg))
51
52#define ADXRS290_MAX_TRANSITION_TIME_MS 100
53
54enum adxrs290_mode {
55 ADXRS290_MODE_STANDBY,
56 ADXRS290_MODE_MEASUREMENT,
57};
58
59enum adxrs290_scan_index {
60 ADXRS290_IDX_X,
61 ADXRS290_IDX_Y,
62 ADXRS290_IDX_TEMP,
63 ADXRS290_IDX_TS,
64};
65
66struct adxrs290_state {
67 struct spi_device *spi;
68
69 struct mutex lock;
70 enum adxrs290_mode mode;
71 unsigned int lpf_3db_freq_idx;
72 unsigned int hpf_3db_freq_idx;
73 struct iio_trigger *dready_trig;
74
75 struct {
76 s16 channels[3];
77 s64 ts __aligned(8);
78 } buffer;
79};
80
81
82
83
84
85static const int adxrs290_lpf_3db_freq_hz_table[][2] = {
86 [0] = {480, 0},
87 [1] = {320, 0},
88 [2] = {160, 0},
89 [3] = {80, 0},
90 [4] = {56, 600000},
91 [5] = {40, 0},
92 [6] = {28, 300000},
93 [7] = {20, 0},
94};
95
96
97
98
99
100static const int adxrs290_hpf_3db_freq_hz_table[][2] = {
101 [0] = {0, 0},
102 [1] = {0, 11000},
103 [2] = {0, 22000},
104 [3] = {0, 44000},
105 [4] = {0, 87000},
106 [5] = {0, 175000},
107 [6] = {0, 350000},
108 [7] = {0, 700000},
109 [8] = {1, 400000},
110 [9] = {2, 800000},
111 [10] = {11, 300000},
112};
113
114static int adxrs290_get_rate_data(struct iio_dev *indio_dev, const u8 cmd, int *val)
115{
116 struct adxrs290_state *st = iio_priv(indio_dev);
117 int ret = 0;
118 int temp;
119
120 mutex_lock(&st->lock);
121 temp = spi_w8r16(st->spi, cmd);
122 if (temp < 0) {
123 ret = temp;
124 goto err_unlock;
125 }
126
127 *val = temp;
128
129err_unlock:
130 mutex_unlock(&st->lock);
131 return ret;
132}
133
134static int adxrs290_get_temp_data(struct iio_dev *indio_dev, int *val)
135{
136 const u8 cmd = ADXRS290_READ_REG(ADXRS290_REG_TEMP0);
137 struct adxrs290_state *st = iio_priv(indio_dev);
138 int ret = 0;
139 int temp;
140
141 mutex_lock(&st->lock);
142 temp = spi_w8r16(st->spi, cmd);
143 if (temp < 0) {
144 ret = temp;
145 goto err_unlock;
146 }
147
148
149 *val = temp & 0x0FFF;
150
151err_unlock:
152 mutex_unlock(&st->lock);
153 return ret;
154}
155
156static int adxrs290_get_3db_freq(struct iio_dev *indio_dev, u8 *val, u8 *val2)
157{
158 const u8 cmd = ADXRS290_READ_REG(ADXRS290_REG_FILTER);
159 struct adxrs290_state *st = iio_priv(indio_dev);
160 int ret = 0;
161 short temp;
162
163 mutex_lock(&st->lock);
164 temp = spi_w8r8(st->spi, cmd);
165 if (temp < 0) {
166 ret = temp;
167 goto err_unlock;
168 }
169
170 *val = FIELD_GET(ADXRS290_LPF_MASK, temp);
171 *val2 = FIELD_GET(ADXRS290_HPF_MASK, temp);
172
173err_unlock:
174 mutex_unlock(&st->lock);
175 return ret;
176}
177
178static int adxrs290_spi_write_reg(struct spi_device *spi, const u8 reg,
179 const u8 val)
180{
181 u8 buf[2];
182
183 buf[0] = reg;
184 buf[1] = val;
185
186 return spi_write_then_read(spi, buf, ARRAY_SIZE(buf), NULL, 0);
187}
188
189static int adxrs290_find_match(const int (*freq_tbl)[2], const int n,
190 const int val, const int val2)
191{
192 int i;
193
194 for (i = 0; i < n; i++) {
195 if (freq_tbl[i][0] == val && freq_tbl[i][1] == val2)
196 return i;
197 }
198
199 return -EINVAL;
200}
201
202static int adxrs290_set_filter_freq(struct iio_dev *indio_dev,
203 const unsigned int lpf_idx,
204 const unsigned int hpf_idx)
205{
206 struct adxrs290_state *st = iio_priv(indio_dev);
207 u8 val;
208
209 val = ADXRS290_HPF(hpf_idx) | ADXRS290_LPF(lpf_idx);
210
211 return adxrs290_spi_write_reg(st->spi, ADXRS290_REG_FILTER, val);
212}
213
214static int adxrs290_set_mode(struct iio_dev *indio_dev, enum adxrs290_mode mode)
215{
216 struct adxrs290_state *st = iio_priv(indio_dev);
217 int val, ret;
218
219 if (st->mode == mode)
220 return 0;
221
222 mutex_lock(&st->lock);
223
224 ret = spi_w8r8(st->spi, ADXRS290_READ_REG(ADXRS290_REG_POWER_CTL));
225 if (ret < 0)
226 goto out_unlock;
227
228 val = ret;
229
230 switch (mode) {
231 case ADXRS290_MODE_STANDBY:
232 val &= ~ADXRS290_MEASUREMENT;
233 break;
234 case ADXRS290_MODE_MEASUREMENT:
235 val |= ADXRS290_MEASUREMENT;
236 break;
237 default:
238 ret = -EINVAL;
239 goto out_unlock;
240 }
241
242 ret = adxrs290_spi_write_reg(st->spi, ADXRS290_REG_POWER_CTL, val);
243 if (ret < 0) {
244 dev_err(&st->spi->dev, "unable to set mode: %d\n", ret);
245 goto out_unlock;
246 }
247
248
249 st->mode = mode;
250
251out_unlock:
252 mutex_unlock(&st->lock);
253 return ret;
254}
255
256static void adxrs290_chip_off_action(void *data)
257{
258 struct iio_dev *indio_dev = data;
259
260 adxrs290_set_mode(indio_dev, ADXRS290_MODE_STANDBY);
261}
262
263static int adxrs290_initial_setup(struct iio_dev *indio_dev)
264{
265 struct adxrs290_state *st = iio_priv(indio_dev);
266 struct spi_device *spi = st->spi;
267 int ret;
268
269 ret = adxrs290_spi_write_reg(spi, ADXRS290_REG_POWER_CTL,
270 ADXRS290_MEASUREMENT | ADXRS290_TSM);
271 if (ret < 0)
272 return ret;
273
274 st->mode = ADXRS290_MODE_MEASUREMENT;
275
276 return devm_add_action_or_reset(&spi->dev, adxrs290_chip_off_action,
277 indio_dev);
278}
279
280static int adxrs290_read_raw(struct iio_dev *indio_dev,
281 struct iio_chan_spec const *chan,
282 int *val,
283 int *val2,
284 long mask)
285{
286 struct adxrs290_state *st = iio_priv(indio_dev);
287 unsigned int t;
288 int ret;
289
290 switch (mask) {
291 case IIO_CHAN_INFO_RAW:
292 ret = iio_device_claim_direct_mode(indio_dev);
293 if (ret)
294 return ret;
295
296 switch (chan->type) {
297 case IIO_ANGL_VEL:
298 ret = adxrs290_get_rate_data(indio_dev,
299 ADXRS290_READ_REG(chan->address),
300 val);
301 if (ret < 0)
302 break;
303
304 ret = IIO_VAL_INT;
305 break;
306 case IIO_TEMP:
307 ret = adxrs290_get_temp_data(indio_dev, val);
308 if (ret < 0)
309 break;
310
311 ret = IIO_VAL_INT;
312 break;
313 default:
314 ret = -EINVAL;
315 break;
316 }
317
318 iio_device_release_direct_mode(indio_dev);
319 return ret;
320 case IIO_CHAN_INFO_SCALE:
321 switch (chan->type) {
322 case IIO_ANGL_VEL:
323
324 *val = 0;
325 *val2 = 87266;
326 return IIO_VAL_INT_PLUS_NANO;
327 case IIO_TEMP:
328
329 *val = 100;
330 return IIO_VAL_INT;
331 default:
332 return -EINVAL;
333 }
334 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
335 switch (chan->type) {
336 case IIO_ANGL_VEL:
337 t = st->lpf_3db_freq_idx;
338 *val = adxrs290_lpf_3db_freq_hz_table[t][0];
339 *val2 = adxrs290_lpf_3db_freq_hz_table[t][1];
340 return IIO_VAL_INT_PLUS_MICRO;
341 default:
342 return -EINVAL;
343 }
344 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
345 switch (chan->type) {
346 case IIO_ANGL_VEL:
347 t = st->hpf_3db_freq_idx;
348 *val = adxrs290_hpf_3db_freq_hz_table[t][0];
349 *val2 = adxrs290_hpf_3db_freq_hz_table[t][1];
350 return IIO_VAL_INT_PLUS_MICRO;
351 default:
352 return -EINVAL;
353 }
354 }
355
356 return -EINVAL;
357}
358
359static int adxrs290_write_raw(struct iio_dev *indio_dev,
360 struct iio_chan_spec const *chan,
361 int val,
362 int val2,
363 long mask)
364{
365 struct adxrs290_state *st = iio_priv(indio_dev);
366 int ret, lpf_idx, hpf_idx;
367
368 ret = iio_device_claim_direct_mode(indio_dev);
369 if (ret)
370 return ret;
371
372 switch (mask) {
373 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
374 lpf_idx = adxrs290_find_match(adxrs290_lpf_3db_freq_hz_table,
375 ARRAY_SIZE(adxrs290_lpf_3db_freq_hz_table),
376 val, val2);
377 if (lpf_idx < 0) {
378 ret = -EINVAL;
379 break;
380 }
381
382
383 st->lpf_3db_freq_idx = lpf_idx;
384
385 hpf_idx = st->hpf_3db_freq_idx;
386 ret = adxrs290_set_filter_freq(indio_dev, lpf_idx, hpf_idx);
387 break;
388
389 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
390 hpf_idx = adxrs290_find_match(adxrs290_hpf_3db_freq_hz_table,
391 ARRAY_SIZE(adxrs290_hpf_3db_freq_hz_table),
392 val, val2);
393 if (hpf_idx < 0) {
394 ret = -EINVAL;
395 break;
396 }
397
398
399 st->hpf_3db_freq_idx = hpf_idx;
400
401 lpf_idx = st->lpf_3db_freq_idx;
402 ret = adxrs290_set_filter_freq(indio_dev, lpf_idx, hpf_idx);
403 break;
404
405 default:
406 ret = -EINVAL;
407 break;
408 }
409
410 iio_device_release_direct_mode(indio_dev);
411 return ret;
412}
413
414static int adxrs290_read_avail(struct iio_dev *indio_dev,
415 struct iio_chan_spec const *chan,
416 const int **vals, int *type, int *length,
417 long mask)
418{
419 switch (mask) {
420 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
421 *vals = (const int *)adxrs290_lpf_3db_freq_hz_table;
422 *type = IIO_VAL_INT_PLUS_MICRO;
423
424 *length = ARRAY_SIZE(adxrs290_lpf_3db_freq_hz_table) * 2;
425
426 return IIO_AVAIL_LIST;
427 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
428 *vals = (const int *)adxrs290_hpf_3db_freq_hz_table;
429 *type = IIO_VAL_INT_PLUS_MICRO;
430
431 *length = ARRAY_SIZE(adxrs290_hpf_3db_freq_hz_table) * 2;
432
433 return IIO_AVAIL_LIST;
434 default:
435 return -EINVAL;
436 }
437}
438
439static int adxrs290_reg_access_rw(struct spi_device *spi, unsigned int reg,
440 unsigned int *readval)
441{
442 int ret;
443
444 ret = spi_w8r8(spi, ADXRS290_READ_REG(reg));
445 if (ret < 0)
446 return ret;
447
448 *readval = ret;
449
450 return 0;
451}
452
453static int adxrs290_reg_access(struct iio_dev *indio_dev, unsigned int reg,
454 unsigned int writeval, unsigned int *readval)
455{
456 struct adxrs290_state *st = iio_priv(indio_dev);
457
458 if (readval)
459 return adxrs290_reg_access_rw(st->spi, reg, readval);
460 else
461 return adxrs290_spi_write_reg(st->spi, reg, writeval);
462}
463
464static int adxrs290_data_rdy_trigger_set_state(struct iio_trigger *trig,
465 bool state)
466{
467 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
468 struct adxrs290_state *st = iio_priv(indio_dev);
469 int ret;
470 u8 val;
471
472 val = state ? ADXRS290_SYNC(ADXRS290_DATA_RDY_OUT) : 0;
473
474 ret = adxrs290_spi_write_reg(st->spi, ADXRS290_REG_DATA_RDY, val);
475 if (ret < 0)
476 dev_err(&st->spi->dev, "failed to start data rdy interrupt\n");
477
478 return ret;
479}
480
481static void adxrs290_reset_trig(struct iio_trigger *trig)
482{
483 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
484 int val;
485
486
487
488
489
490
491
492 adxrs290_get_rate_data(indio_dev,
493 ADXRS290_READ_REG(ADXRS290_REG_DATAY0), &val);
494}
495
496static const struct iio_trigger_ops adxrs290_trigger_ops = {
497 .set_trigger_state = &adxrs290_data_rdy_trigger_set_state,
498 .validate_device = &iio_trigger_validate_own_device,
499 .reenable = &adxrs290_reset_trig,
500};
501
502static irqreturn_t adxrs290_trigger_handler(int irq, void *p)
503{
504 struct iio_poll_func *pf = p;
505 struct iio_dev *indio_dev = pf->indio_dev;
506 struct adxrs290_state *st = iio_priv(indio_dev);
507 u8 tx = ADXRS290_READ_REG(ADXRS290_REG_DATAX0);
508 int ret;
509
510 mutex_lock(&st->lock);
511
512
513 ret = spi_write_then_read(st->spi, &tx, sizeof(tx), st->buffer.channels,
514 sizeof(st->buffer.channels));
515 if (ret < 0)
516 goto out_unlock_notify;
517
518 iio_push_to_buffers_with_timestamp(indio_dev, &st->buffer,
519 pf->timestamp);
520
521out_unlock_notify:
522 mutex_unlock(&st->lock);
523 iio_trigger_notify_done(indio_dev->trig);
524
525 return IRQ_HANDLED;
526}
527
528#define ADXRS290_ANGL_VEL_CHANNEL(reg, axis) { \
529 .type = IIO_ANGL_VEL, \
530 .address = reg, \
531 .modified = 1, \
532 .channel2 = IIO_MOD_##axis, \
533 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
534 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
535 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
536 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
537 .info_mask_shared_by_type_available = \
538 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY) | \
539 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \
540 .scan_index = ADXRS290_IDX_##axis, \
541 .scan_type = { \
542 .sign = 's', \
543 .realbits = 16, \
544 .storagebits = 16, \
545 .endianness = IIO_LE, \
546 }, \
547}
548
549static const struct iio_chan_spec adxrs290_channels[] = {
550 ADXRS290_ANGL_VEL_CHANNEL(ADXRS290_REG_DATAX0, X),
551 ADXRS290_ANGL_VEL_CHANNEL(ADXRS290_REG_DATAY0, Y),
552 {
553 .type = IIO_TEMP,
554 .address = ADXRS290_REG_TEMP0,
555 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
556 BIT(IIO_CHAN_INFO_SCALE),
557 .scan_index = ADXRS290_IDX_TEMP,
558 .scan_type = {
559 .sign = 's',
560 .realbits = 12,
561 .storagebits = 16,
562 .endianness = IIO_LE,
563 },
564 },
565 IIO_CHAN_SOFT_TIMESTAMP(ADXRS290_IDX_TS),
566};
567
568static const unsigned long adxrs290_avail_scan_masks[] = {
569 BIT(ADXRS290_IDX_X) | BIT(ADXRS290_IDX_Y) | BIT(ADXRS290_IDX_TEMP),
570 0
571};
572
573static const struct iio_info adxrs290_info = {
574 .read_raw = &adxrs290_read_raw,
575 .write_raw = &adxrs290_write_raw,
576 .read_avail = &adxrs290_read_avail,
577 .debugfs_reg_access = &adxrs290_reg_access,
578};
579
580static int adxrs290_probe_trigger(struct iio_dev *indio_dev)
581{
582 struct adxrs290_state *st = iio_priv(indio_dev);
583 int ret;
584
585 if (!st->spi->irq) {
586 dev_info(&st->spi->dev, "no irq, using polling\n");
587 return 0;
588 }
589
590 st->dready_trig = devm_iio_trigger_alloc(&st->spi->dev, "%s-dev%d",
591 indio_dev->name,
592 iio_device_id(indio_dev));
593 if (!st->dready_trig)
594 return -ENOMEM;
595
596 st->dready_trig->ops = &adxrs290_trigger_ops;
597 iio_trigger_set_drvdata(st->dready_trig, indio_dev);
598
599 ret = devm_request_irq(&st->spi->dev, st->spi->irq,
600 &iio_trigger_generic_data_rdy_poll,
601 IRQF_ONESHOT, "adxrs290_irq", st->dready_trig);
602 if (ret < 0)
603 return dev_err_probe(&st->spi->dev, ret,
604 "request irq %d failed\n", st->spi->irq);
605
606 ret = devm_iio_trigger_register(&st->spi->dev, st->dready_trig);
607 if (ret) {
608 dev_err(&st->spi->dev, "iio trigger register failed\n");
609 return ret;
610 }
611
612 indio_dev->trig = iio_trigger_get(st->dready_trig);
613
614 return 0;
615}
616
617static int adxrs290_probe(struct spi_device *spi)
618{
619 struct iio_dev *indio_dev;
620 struct adxrs290_state *st;
621 u8 val, val2;
622 int ret;
623
624 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
625 if (!indio_dev)
626 return -ENOMEM;
627
628 st = iio_priv(indio_dev);
629 st->spi = spi;
630
631 indio_dev->name = "adxrs290";
632 indio_dev->modes = INDIO_DIRECT_MODE;
633 indio_dev->channels = adxrs290_channels;
634 indio_dev->num_channels = ARRAY_SIZE(adxrs290_channels);
635 indio_dev->info = &adxrs290_info;
636 indio_dev->available_scan_masks = adxrs290_avail_scan_masks;
637
638 mutex_init(&st->lock);
639
640 val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_ADI_ID));
641 if (val != ADXRS290_ADI_ID) {
642 dev_err(&spi->dev, "Wrong ADI ID 0x%02x\n", val);
643 return -ENODEV;
644 }
645
646 val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_MEMS_ID));
647 if (val != ADXRS290_MEMS_ID) {
648 dev_err(&spi->dev, "Wrong MEMS ID 0x%02x\n", val);
649 return -ENODEV;
650 }
651
652 val = spi_w8r8(spi, ADXRS290_READ_REG(ADXRS290_REG_DEV_ID));
653 if (val != ADXRS290_DEV_ID) {
654 dev_err(&spi->dev, "Wrong DEV ID 0x%02x\n", val);
655 return -ENODEV;
656 }
657
658
659 st->mode = ADXRS290_MODE_STANDBY;
660
661
662 ret = adxrs290_initial_setup(indio_dev);
663 if (ret < 0)
664 return ret;
665
666
667 msleep(ADXRS290_MAX_TRANSITION_TIME_MS);
668
669 ret = adxrs290_get_3db_freq(indio_dev, &val, &val2);
670 if (ret < 0)
671 return ret;
672
673 st->lpf_3db_freq_idx = val;
674 st->hpf_3db_freq_idx = val2;
675
676 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
677 &iio_pollfunc_store_time,
678 &adxrs290_trigger_handler, NULL);
679 if (ret < 0)
680 return dev_err_probe(&spi->dev, ret,
681 "iio triggered buffer setup failed\n");
682
683 ret = adxrs290_probe_trigger(indio_dev);
684 if (ret < 0)
685 return ret;
686
687 return devm_iio_device_register(&spi->dev, indio_dev);
688}
689
690static const struct of_device_id adxrs290_of_match[] = {
691 { .compatible = "adi,adxrs290" },
692 { }
693};
694MODULE_DEVICE_TABLE(of, adxrs290_of_match);
695
696static struct spi_driver adxrs290_driver = {
697 .driver = {
698 .name = "adxrs290",
699 .of_match_table = adxrs290_of_match,
700 },
701 .probe = adxrs290_probe,
702};
703module_spi_driver(adxrs290_driver);
704
705MODULE_AUTHOR("Nishant Malpani <nish.malpani25@gmail.com>");
706MODULE_DESCRIPTION("Analog Devices ADXRS290 Gyroscope SPI driver");
707MODULE_LICENSE("GPL");
708
