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9#include <linux/device.h>
10#include <linux/err.h>
11#include <linux/interrupt.h>
12#include <linux/kernel.h>
13#include <linux/module.h>
14#include <linux/regmap.h>
15#include <linux/spi/spi.h>
16#include <linux/sysfs.h>
17#include <linux/regulator/consumer.h>
18
19#include <linux/iio/iio.h>
20#include <linux/iio/sysfs.h>
21#include <linux/iio/buffer.h>
22#include <linux/iio/trigger.h>
23#include <linux/iio/triggered_buffer.h>
24#include <linux/iio/trigger_consumer.h>
25
26#include <asm/unaligned.h>
27
28#include "afe440x.h"
29
30#define AFE4403_DRIVER_NAME "afe4403"
31
32
33#define AFE4403_TIAGAIN 0x20
34#define AFE4403_TIA_AMB_GAIN 0x21
35
36enum afe4403_fields {
37
38 F_RF_LED1, F_CF_LED1,
39 F_RF_LED, F_CF_LED,
40
41
42 F_ILED1, F_ILED2,
43
44
45 F_MAX_FIELDS
46};
47
48static const struct reg_field afe4403_reg_fields[] = {
49
50 [F_RF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 0, 2),
51 [F_CF_LED1] = REG_FIELD(AFE4403_TIAGAIN, 3, 7),
52 [F_RF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 0, 2),
53 [F_CF_LED] = REG_FIELD(AFE4403_TIA_AMB_GAIN, 3, 7),
54
55 [F_ILED1] = REG_FIELD(AFE440X_LEDCNTRL, 0, 7),
56 [F_ILED2] = REG_FIELD(AFE440X_LEDCNTRL, 8, 15),
57};
58
59
60
61
62
63
64
65
66
67
68
69
70struct afe4403_data {
71 struct device *dev;
72 struct spi_device *spi;
73 struct regmap *regmap;
74 struct regmap_field *fields[F_MAX_FIELDS];
75 struct regulator *regulator;
76 struct iio_trigger *trig;
77 int irq;
78
79 s32 buffer[8] __aligned(8);
80};
81
82enum afe4403_chan_id {
83 LED2 = 1,
84 ALED2,
85 LED1,
86 ALED1,
87 LED2_ALED2,
88 LED1_ALED1,
89};
90
91static const unsigned int afe4403_channel_values[] = {
92 [LED2] = AFE440X_LED2VAL,
93 [ALED2] = AFE440X_ALED2VAL,
94 [LED1] = AFE440X_LED1VAL,
95 [ALED1] = AFE440X_ALED1VAL,
96 [LED2_ALED2] = AFE440X_LED2_ALED2VAL,
97 [LED1_ALED1] = AFE440X_LED1_ALED1VAL,
98};
99
100static const unsigned int afe4403_channel_leds[] = {
101 [LED2] = F_ILED2,
102 [LED1] = F_ILED1,
103};
104
105static const struct iio_chan_spec afe4403_channels[] = {
106
107 AFE440X_INTENSITY_CHAN(LED2, 0),
108 AFE440X_INTENSITY_CHAN(ALED2, 0),
109 AFE440X_INTENSITY_CHAN(LED1, 0),
110 AFE440X_INTENSITY_CHAN(ALED1, 0),
111 AFE440X_INTENSITY_CHAN(LED2_ALED2, 0),
112 AFE440X_INTENSITY_CHAN(LED1_ALED1, 0),
113
114 AFE440X_CURRENT_CHAN(LED2),
115 AFE440X_CURRENT_CHAN(LED1),
116};
117
118static const struct afe440x_val_table afe4403_res_table[] = {
119 { 500000 }, { 250000 }, { 100000 }, { 50000 },
120 { 25000 }, { 10000 }, { 1000000 }, { 0 },
121};
122AFE440X_TABLE_ATTR(in_intensity_resistance_available, afe4403_res_table);
123
124static const struct afe440x_val_table afe4403_cap_table[] = {
125 { 0, 5000 }, { 0, 10000 }, { 0, 20000 }, { 0, 25000 },
126 { 0, 30000 }, { 0, 35000 }, { 0, 45000 }, { 0, 50000 },
127 { 0, 55000 }, { 0, 60000 }, { 0, 70000 }, { 0, 75000 },
128 { 0, 80000 }, { 0, 85000 }, { 0, 95000 }, { 0, 100000 },
129 { 0, 155000 }, { 0, 160000 }, { 0, 170000 }, { 0, 175000 },
130 { 0, 180000 }, { 0, 185000 }, { 0, 195000 }, { 0, 200000 },
131 { 0, 205000 }, { 0, 210000 }, { 0, 220000 }, { 0, 225000 },
132 { 0, 230000 }, { 0, 235000 }, { 0, 245000 }, { 0, 250000 },
133};
134AFE440X_TABLE_ATTR(in_intensity_capacitance_available, afe4403_cap_table);
135
136static ssize_t afe440x_show_register(struct device *dev,
137 struct device_attribute *attr,
138 char *buf)
139{
140 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
141 struct afe4403_data *afe = iio_priv(indio_dev);
142 struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
143 unsigned int reg_val;
144 int vals[2];
145 int ret;
146
147 ret = regmap_field_read(afe->fields[afe440x_attr->field], ®_val);
148 if (ret)
149 return ret;
150
151 if (reg_val >= afe440x_attr->table_size)
152 return -EINVAL;
153
154 vals[0] = afe440x_attr->val_table[reg_val].integer;
155 vals[1] = afe440x_attr->val_table[reg_val].fract;
156
157 return iio_format_value(buf, IIO_VAL_INT_PLUS_MICRO, 2, vals);
158}
159
160static ssize_t afe440x_store_register(struct device *dev,
161 struct device_attribute *attr,
162 const char *buf, size_t count)
163{
164 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
165 struct afe4403_data *afe = iio_priv(indio_dev);
166 struct afe440x_attr *afe440x_attr = to_afe440x_attr(attr);
167 int val, integer, fract, ret;
168
169 ret = iio_str_to_fixpoint(buf, 100000, &integer, &fract);
170 if (ret)
171 return ret;
172
173 for (val = 0; val < afe440x_attr->table_size; val++)
174 if (afe440x_attr->val_table[val].integer == integer &&
175 afe440x_attr->val_table[val].fract == fract)
176 break;
177 if (val == afe440x_attr->table_size)
178 return -EINVAL;
179
180 ret = regmap_field_write(afe->fields[afe440x_attr->field], val);
181 if (ret)
182 return ret;
183
184 return count;
185}
186
187static AFE440X_ATTR(in_intensity1_resistance, F_RF_LED, afe4403_res_table);
188static AFE440X_ATTR(in_intensity1_capacitance, F_CF_LED, afe4403_cap_table);
189
190static AFE440X_ATTR(in_intensity2_resistance, F_RF_LED, afe4403_res_table);
191static AFE440X_ATTR(in_intensity2_capacitance, F_CF_LED, afe4403_cap_table);
192
193static AFE440X_ATTR(in_intensity3_resistance, F_RF_LED1, afe4403_res_table);
194static AFE440X_ATTR(in_intensity3_capacitance, F_CF_LED1, afe4403_cap_table);
195
196static AFE440X_ATTR(in_intensity4_resistance, F_RF_LED1, afe4403_res_table);
197static AFE440X_ATTR(in_intensity4_capacitance, F_CF_LED1, afe4403_cap_table);
198
199static struct attribute *afe440x_attributes[] = {
200 &dev_attr_in_intensity_resistance_available.attr,
201 &dev_attr_in_intensity_capacitance_available.attr,
202 &afe440x_attr_in_intensity1_resistance.dev_attr.attr,
203 &afe440x_attr_in_intensity1_capacitance.dev_attr.attr,
204 &afe440x_attr_in_intensity2_resistance.dev_attr.attr,
205 &afe440x_attr_in_intensity2_capacitance.dev_attr.attr,
206 &afe440x_attr_in_intensity3_resistance.dev_attr.attr,
207 &afe440x_attr_in_intensity3_capacitance.dev_attr.attr,
208 &afe440x_attr_in_intensity4_resistance.dev_attr.attr,
209 &afe440x_attr_in_intensity4_capacitance.dev_attr.attr,
210 NULL
211};
212
213static const struct attribute_group afe440x_attribute_group = {
214 .attrs = afe440x_attributes
215};
216
217static int afe4403_read(struct afe4403_data *afe, unsigned int reg, u32 *val)
218{
219 u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
220 u8 rx[3];
221 int ret;
222
223
224 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
225 if (ret)
226 return ret;
227
228 ret = spi_write_then_read(afe->spi, ®, 1, rx, sizeof(rx));
229 if (ret)
230 return ret;
231
232 *val = get_unaligned_be24(&rx[0]);
233
234
235 tx[3] = AFE440X_CONTROL0_WRITE;
236 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
237 if (ret)
238 return ret;
239
240 return 0;
241}
242
243static int afe4403_read_raw(struct iio_dev *indio_dev,
244 struct iio_chan_spec const *chan,
245 int *val, int *val2, long mask)
246{
247 struct afe4403_data *afe = iio_priv(indio_dev);
248 unsigned int reg = afe4403_channel_values[chan->address];
249 unsigned int field = afe4403_channel_leds[chan->address];
250 int ret;
251
252 switch (chan->type) {
253 case IIO_INTENSITY:
254 switch (mask) {
255 case IIO_CHAN_INFO_RAW:
256 ret = afe4403_read(afe, reg, val);
257 if (ret)
258 return ret;
259 return IIO_VAL_INT;
260 }
261 break;
262 case IIO_CURRENT:
263 switch (mask) {
264 case IIO_CHAN_INFO_RAW:
265 ret = regmap_field_read(afe->fields[field], val);
266 if (ret)
267 return ret;
268 return IIO_VAL_INT;
269 case IIO_CHAN_INFO_SCALE:
270 *val = 0;
271 *val2 = 800000;
272 return IIO_VAL_INT_PLUS_MICRO;
273 }
274 break;
275 default:
276 break;
277 }
278
279 return -EINVAL;
280}
281
282static int afe4403_write_raw(struct iio_dev *indio_dev,
283 struct iio_chan_spec const *chan,
284 int val, int val2, long mask)
285{
286 struct afe4403_data *afe = iio_priv(indio_dev);
287 unsigned int field = afe4403_channel_leds[chan->address];
288
289 switch (chan->type) {
290 case IIO_CURRENT:
291 switch (mask) {
292 case IIO_CHAN_INFO_RAW:
293 return regmap_field_write(afe->fields[field], val);
294 }
295 break;
296 default:
297 break;
298 }
299
300 return -EINVAL;
301}
302
303static const struct iio_info afe4403_iio_info = {
304 .attrs = &afe440x_attribute_group,
305 .read_raw = afe4403_read_raw,
306 .write_raw = afe4403_write_raw,
307};
308
309static irqreturn_t afe4403_trigger_handler(int irq, void *private)
310{
311 struct iio_poll_func *pf = private;
312 struct iio_dev *indio_dev = pf->indio_dev;
313 struct afe4403_data *afe = iio_priv(indio_dev);
314 int ret, bit, i = 0;
315 u8 tx[4] = {AFE440X_CONTROL0, 0x0, 0x0, AFE440X_CONTROL0_READ};
316 u8 rx[3];
317
318
319 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
320 if (ret)
321 goto err;
322
323 for_each_set_bit(bit, indio_dev->active_scan_mask,
324 indio_dev->masklength) {
325 ret = spi_write_then_read(afe->spi,
326 &afe4403_channel_values[bit], 1,
327 rx, sizeof(rx));
328 if (ret)
329 goto err;
330
331 afe->buffer[i++] = get_unaligned_be24(&rx[0]);
332 }
333
334
335 tx[3] = AFE440X_CONTROL0_WRITE;
336 ret = spi_write_then_read(afe->spi, tx, 4, NULL, 0);
337 if (ret)
338 goto err;
339
340 iio_push_to_buffers_with_timestamp(indio_dev, afe->buffer,
341 pf->timestamp);
342err:
343 iio_trigger_notify_done(indio_dev->trig);
344
345 return IRQ_HANDLED;
346}
347
348static const struct iio_trigger_ops afe4403_trigger_ops = {
349};
350
351#define AFE4403_TIMING_PAIRS \
352 { AFE440X_LED2STC, 0x000050 }, \
353 { AFE440X_LED2ENDC, 0x0003e7 }, \
354 { AFE440X_LED1LEDSTC, 0x0007d0 }, \
355 { AFE440X_LED1LEDENDC, 0x000bb7 }, \
356 { AFE440X_ALED2STC, 0x000438 }, \
357 { AFE440X_ALED2ENDC, 0x0007cf }, \
358 { AFE440X_LED1STC, 0x000820 }, \
359 { AFE440X_LED1ENDC, 0x000bb7 }, \
360 { AFE440X_LED2LEDSTC, 0x000000 }, \
361 { AFE440X_LED2LEDENDC, 0x0003e7 }, \
362 { AFE440X_ALED1STC, 0x000c08 }, \
363 { AFE440X_ALED1ENDC, 0x000f9f }, \
364 { AFE440X_LED2CONVST, 0x0003ef }, \
365 { AFE440X_LED2CONVEND, 0x0007cf }, \
366 { AFE440X_ALED2CONVST, 0x0007d7 }, \
367 { AFE440X_ALED2CONVEND, 0x000bb7 }, \
368 { AFE440X_LED1CONVST, 0x000bbf }, \
369 { AFE440X_LED1CONVEND, 0x009c3f }, \
370 { AFE440X_ALED1CONVST, 0x000fa7 }, \
371 { AFE440X_ALED1CONVEND, 0x001387 }, \
372 { AFE440X_ADCRSTSTCT0, 0x0003e8 }, \
373 { AFE440X_ADCRSTENDCT0, 0x0003eb }, \
374 { AFE440X_ADCRSTSTCT1, 0x0007d0 }, \
375 { AFE440X_ADCRSTENDCT1, 0x0007d3 }, \
376 { AFE440X_ADCRSTSTCT2, 0x000bb8 }, \
377 { AFE440X_ADCRSTENDCT2, 0x000bbb }, \
378 { AFE440X_ADCRSTSTCT3, 0x000fa0 }, \
379 { AFE440X_ADCRSTENDCT3, 0x000fa3 }, \
380 { AFE440X_PRPCOUNT, 0x009c3f }, \
381 { AFE440X_PDNCYCLESTC, 0x001518 }, \
382 { AFE440X_PDNCYCLEENDC, 0x00991f }
383
384static const struct reg_sequence afe4403_reg_sequences[] = {
385 AFE4403_TIMING_PAIRS,
386 { AFE440X_CONTROL1, AFE440X_CONTROL1_TIMEREN },
387 { AFE4403_TIAGAIN, AFE440X_TIAGAIN_ENSEPGAIN },
388};
389
390static const struct regmap_range afe4403_yes_ranges[] = {
391 regmap_reg_range(AFE440X_LED2VAL, AFE440X_LED1_ALED1VAL),
392};
393
394static const struct regmap_access_table afe4403_volatile_table = {
395 .yes_ranges = afe4403_yes_ranges,
396 .n_yes_ranges = ARRAY_SIZE(afe4403_yes_ranges),
397};
398
399static const struct regmap_config afe4403_regmap_config = {
400 .reg_bits = 8,
401 .val_bits = 24,
402
403 .max_register = AFE440X_PDNCYCLEENDC,
404 .cache_type = REGCACHE_RBTREE,
405 .volatile_table = &afe4403_volatile_table,
406};
407
408static const struct of_device_id afe4403_of_match[] = {
409 { .compatible = "ti,afe4403", },
410 { }
411};
412MODULE_DEVICE_TABLE(of, afe4403_of_match);
413
414static int __maybe_unused afe4403_suspend(struct device *dev)
415{
416 struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
417 struct afe4403_data *afe = iio_priv(indio_dev);
418 int ret;
419
420 ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
421 AFE440X_CONTROL2_PDN_AFE,
422 AFE440X_CONTROL2_PDN_AFE);
423 if (ret)
424 return ret;
425
426 ret = regulator_disable(afe->regulator);
427 if (ret) {
428 dev_err(dev, "Unable to disable regulator\n");
429 return ret;
430 }
431
432 return 0;
433}
434
435static int __maybe_unused afe4403_resume(struct device *dev)
436{
437 struct iio_dev *indio_dev = spi_get_drvdata(to_spi_device(dev));
438 struct afe4403_data *afe = iio_priv(indio_dev);
439 int ret;
440
441 ret = regulator_enable(afe->regulator);
442 if (ret) {
443 dev_err(dev, "Unable to enable regulator\n");
444 return ret;
445 }
446
447 ret = regmap_update_bits(afe->regmap, AFE440X_CONTROL2,
448 AFE440X_CONTROL2_PDN_AFE, 0);
449 if (ret)
450 return ret;
451
452 return 0;
453}
454
455static SIMPLE_DEV_PM_OPS(afe4403_pm_ops, afe4403_suspend, afe4403_resume);
456
457static int afe4403_probe(struct spi_device *spi)
458{
459 struct iio_dev *indio_dev;
460 struct afe4403_data *afe;
461 int i, ret;
462
463 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*afe));
464 if (!indio_dev)
465 return -ENOMEM;
466
467 afe = iio_priv(indio_dev);
468 spi_set_drvdata(spi, indio_dev);
469
470 afe->dev = &spi->dev;
471 afe->spi = spi;
472 afe->irq = spi->irq;
473
474 afe->regmap = devm_regmap_init_spi(spi, &afe4403_regmap_config);
475 if (IS_ERR(afe->regmap)) {
476 dev_err(afe->dev, "Unable to allocate register map\n");
477 return PTR_ERR(afe->regmap);
478 }
479
480 for (i = 0; i < F_MAX_FIELDS; i++) {
481 afe->fields[i] = devm_regmap_field_alloc(afe->dev, afe->regmap,
482 afe4403_reg_fields[i]);
483 if (IS_ERR(afe->fields[i])) {
484 dev_err(afe->dev, "Unable to allocate regmap fields\n");
485 return PTR_ERR(afe->fields[i]);
486 }
487 }
488
489 afe->regulator = devm_regulator_get(afe->dev, "tx_sup");
490 if (IS_ERR(afe->regulator)) {
491 dev_err(afe->dev, "Unable to get regulator\n");
492 return PTR_ERR(afe->regulator);
493 }
494 ret = regulator_enable(afe->regulator);
495 if (ret) {
496 dev_err(afe->dev, "Unable to enable regulator\n");
497 return ret;
498 }
499
500 ret = regmap_write(afe->regmap, AFE440X_CONTROL0,
501 AFE440X_CONTROL0_SW_RESET);
502 if (ret) {
503 dev_err(afe->dev, "Unable to reset device\n");
504 goto err_disable_reg;
505 }
506
507 ret = regmap_multi_reg_write(afe->regmap, afe4403_reg_sequences,
508 ARRAY_SIZE(afe4403_reg_sequences));
509 if (ret) {
510 dev_err(afe->dev, "Unable to set register defaults\n");
511 goto err_disable_reg;
512 }
513
514 indio_dev->modes = INDIO_DIRECT_MODE;
515 indio_dev->channels = afe4403_channels;
516 indio_dev->num_channels = ARRAY_SIZE(afe4403_channels);
517 indio_dev->name = AFE4403_DRIVER_NAME;
518 indio_dev->info = &afe4403_iio_info;
519
520 if (afe->irq > 0) {
521 afe->trig = devm_iio_trigger_alloc(afe->dev,
522 "%s-dev%d",
523 indio_dev->name,
524 iio_device_id(indio_dev));
525 if (!afe->trig) {
526 dev_err(afe->dev, "Unable to allocate IIO trigger\n");
527 ret = -ENOMEM;
528 goto err_disable_reg;
529 }
530
531 iio_trigger_set_drvdata(afe->trig, indio_dev);
532
533 afe->trig->ops = &afe4403_trigger_ops;
534
535 ret = iio_trigger_register(afe->trig);
536 if (ret) {
537 dev_err(afe->dev, "Unable to register IIO trigger\n");
538 goto err_disable_reg;
539 }
540
541 ret = devm_request_threaded_irq(afe->dev, afe->irq,
542 iio_trigger_generic_data_rdy_poll,
543 NULL, IRQF_ONESHOT,
544 AFE4403_DRIVER_NAME,
545 afe->trig);
546 if (ret) {
547 dev_err(afe->dev, "Unable to request IRQ\n");
548 goto err_trig;
549 }
550 }
551
552 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
553 afe4403_trigger_handler, NULL);
554 if (ret) {
555 dev_err(afe->dev, "Unable to setup buffer\n");
556 goto err_trig;
557 }
558
559 ret = iio_device_register(indio_dev);
560 if (ret) {
561 dev_err(afe->dev, "Unable to register IIO device\n");
562 goto err_buff;
563 }
564
565 return 0;
566
567err_buff:
568 iio_triggered_buffer_cleanup(indio_dev);
569err_trig:
570 if (afe->irq > 0)
571 iio_trigger_unregister(afe->trig);
572err_disable_reg:
573 regulator_disable(afe->regulator);
574
575 return ret;
576}
577
578static int afe4403_remove(struct spi_device *spi)
579{
580 struct iio_dev *indio_dev = spi_get_drvdata(spi);
581 struct afe4403_data *afe = iio_priv(indio_dev);
582 int ret;
583
584 iio_device_unregister(indio_dev);
585
586 iio_triggered_buffer_cleanup(indio_dev);
587
588 if (afe->irq > 0)
589 iio_trigger_unregister(afe->trig);
590
591 ret = regulator_disable(afe->regulator);
592 if (ret) {
593 dev_err(afe->dev, "Unable to disable regulator\n");
594 return ret;
595 }
596
597 return 0;
598}
599
600static const struct spi_device_id afe4403_ids[] = {
601 { "afe4403", 0 },
602 { }
603};
604MODULE_DEVICE_TABLE(spi, afe4403_ids);
605
606static struct spi_driver afe4403_spi_driver = {
607 .driver = {
608 .name = AFE4403_DRIVER_NAME,
609 .of_match_table = afe4403_of_match,
610 .pm = &afe4403_pm_ops,
611 },
612 .probe = afe4403_probe,
613 .remove = afe4403_remove,
614 .id_table = afe4403_ids,
615};
616module_spi_driver(afe4403_spi_driver);
617
618MODULE_AUTHOR("Andrew F. Davis <afd@ti.com>");
619MODULE_DESCRIPTION("TI AFE4403 Heart Rate Monitor and Pulse Oximeter AFE");
620MODULE_LICENSE("GPL v2");
621
