LXR linux/drivers/iio/imu/inv_mpu6050/inv_mpu

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3* Copyright (C) 2012 Invensense, Inc.
   4*/
   5
   6#ifndef INV_MPU_IIO_H_
   7#define INV_MPU_IIO_H_
   8
   9#include <linux/i2c.h>
  10#include <linux/i2c-mux.h>
  11#include <linux/mutex.h>
  12#include <linux/iio/iio.h>
  13#include <linux/iio/buffer.h>
  14#include <linux/regmap.h>
  15#include <linux/iio/sysfs.h>
  16#include <linux/iio/kfifo_buf.h>
  17#include <linux/iio/trigger.h>
  18#include <linux/iio/triggered_buffer.h>
  19#include <linux/iio/trigger_consumer.h>
  20#include <linux/platform_data/invensense_mpu6050.h>
  21
  22/**
  23 *  struct inv_mpu6050_reg_map - Notable registers.
  24 *  @sample_rate_div:   Divider applied to gyro output rate.
  25 *  @lpf:               Configures internal low pass filter.
  26 *  @accel_lpf:         Configures accelerometer low pass filter.
  27 *  @user_ctrl:         Enables/resets the FIFO.
  28 *  @fifo_en:           Determines which data will appear in FIFO.
  29 *  @gyro_config:       gyro config register.
  30 *  @accl_config:       accel config register
  31 *  @fifo_count_h:      Upper byte of FIFO count.
  32 *  @fifo_r_w:          FIFO register.
  33 *  @raw_gyro:          Address of first gyro register.
  34 *  @raw_accl:          Address of first accel register.
  35 *  @temperature:       temperature register
  36 *  @int_enable:        Interrupt enable register.
  37 *  @int_status:        Interrupt status register.
  38 *  @pwr_mgmt_1:        Controls chip's power state and clock source.
  39 *  @pwr_mgmt_2:        Controls power state of individual sensors.
  40 *  @int_pin_cfg;       Controls interrupt pin configuration.
  41 *  @accl_offset:       Controls the accelerometer calibration offset.
  42 *  @gyro_offset:       Controls the gyroscope calibration offset.
  43 *  @i2c_if:            Controls the i2c interface
  44 */
  45struct inv_mpu6050_reg_map {
  46        u8 sample_rate_div;
  47        u8 lpf;
  48        u8 accel_lpf;
  49        u8 user_ctrl;
  50        u8 fifo_en;
  51        u8 gyro_config;
  52        u8 accl_config;
  53        u8 fifo_count_h;
  54        u8 fifo_r_w;
  55        u8 raw_gyro;
  56        u8 raw_accl;
  57        u8 temperature;
  58        u8 int_enable;
  59        u8 int_status;
  60        u8 pwr_mgmt_1;
  61        u8 pwr_mgmt_2;
  62        u8 int_pin_cfg;
  63        u8 accl_offset;
  64        u8 gyro_offset;
  65        u8 i2c_if;
  66};
  67
  68/*device enum */
  69enum inv_devices {
  70        INV_MPU6050,
  71        INV_MPU6500,
  72        INV_MPU6515,
  73        INV_MPU6880,
  74        INV_MPU6000,
  75        INV_MPU9150,
  76        INV_MPU9250,
  77        INV_MPU9255,
  78        INV_ICM20608,
  79        INV_ICM20609,
  80        INV_ICM20689,
  81        INV_ICM20602,
  82        INV_ICM20690,
  83        INV_IAM20680,
  84        INV_NUM_PARTS
  85};
  86
  87/* chip sensors mask: accelerometer, gyroscope, temperature, magnetometer */
  88#define INV_MPU6050_SENSOR_ACCL         BIT(0)
  89#define INV_MPU6050_SENSOR_GYRO         BIT(1)
  90#define INV_MPU6050_SENSOR_TEMP         BIT(2)
  91#define INV_MPU6050_SENSOR_MAGN         BIT(3)
  92
  93/**
  94 *  struct inv_mpu6050_chip_config - Cached chip configuration data.
  95 *  @clk:               selected chip clock
  96 *  @fsr:               Full scale range.
  97 *  @lpf:               Digital low pass filter frequency.
  98 *  @accl_fs:           accel full scale range.
  99 *  @accl_en:           accel engine enabled
 100 *  @gyro_en:           gyro engine enabled
 101 *  @temp_en:           temperature sensor enabled
 102 *  @magn_en:           magn engine (i2c master) enabled
 103 *  @accl_fifo_enable:  enable accel data output
 104 *  @gyro_fifo_enable:  enable gyro data output
 105 *  @temp_fifo_enable:  enable temp data output
 106 *  @magn_fifo_enable:  enable magn data output
 107 *  @divider:           chip sample rate divider (sample rate divider - 1)
 108 */
 109struct inv_mpu6050_chip_config {
 110        unsigned int clk:3;
 111        unsigned int fsr:2;
 112        unsigned int lpf:3;
 113        unsigned int accl_fs:2;
 114        unsigned int accl_en:1;
 115        unsigned int gyro_en:1;
 116        unsigned int temp_en:1;
 117        unsigned int magn_en:1;
 118        unsigned int accl_fifo_enable:1;
 119        unsigned int gyro_fifo_enable:1;
 120        unsigned int temp_fifo_enable:1;
 121        unsigned int magn_fifo_enable:1;
 122        u8 divider;
 123        u8 user_ctrl;
 124};
 125
 126/*
 127 * Maximum of 6 + 6 + 2 + 7 (for MPU9x50) = 21 round up to 24 and plus 8.
 128 * May be less if fewer channels are enabled, as long as the timestamp
 129 * remains 8 byte aligned
 130 */
 131#define INV_MPU6050_OUTPUT_DATA_SIZE         32
 132
 133/**
 134 *  struct inv_mpu6050_hw - Other important hardware information.
 135 *  @whoami:    Self identification byte from WHO_AM_I register
 136 *  @name:      name of the chip.
 137 *  @reg:   register map of the chip.
 138 *  @config:    configuration of the chip.
 139 *  @fifo_size: size of the FIFO in bytes.
 140 *  @temp:      offset and scale to apply to raw temperature.
 141 */
 142struct inv_mpu6050_hw {
 143        u8 whoami;
 144        u8 *name;
 145        const struct inv_mpu6050_reg_map *reg;
 146        const struct inv_mpu6050_chip_config *config;
 147        size_t fifo_size;
 148        struct {
 149                int offset;
 150                int scale;
 151        } temp;
 152        struct {
 153                unsigned int accel;
 154                unsigned int gyro;
 155        } startup_time;
 156};
 157
 158/*
 159 *  struct inv_mpu6050_state - Driver state variables.
 160 *  @lock:              Chip access lock.
 161 *  @trig:              IIO trigger.
 162 *  @chip_config:       Cached attribute information.
 163 *  @reg:               Map of important registers.
 164 *  @hw:                Other hardware-specific information.
 165 *  @chip_type:         chip type.
 166 *  @plat_data:         platform data (deprecated in favor of @orientation).
 167 *  @orientation:       sensor chip orientation relative to main hardware.
 168 *  @map                regmap pointer.
 169 *  @irq                interrupt number.
 170 *  @irq_mask           the int_pin_cfg mask to configure interrupt type.
 171 *  @chip_period:       chip internal period estimation (~1kHz).
 172 *  @it_timestamp:      timestamp from previous interrupt.
 173 *  @data_timestamp:    timestamp for next data sample.
 174 *  @vdd_supply:        VDD voltage regulator for the chip.
 175 *  @vddio_supply       I/O voltage regulator for the chip.
 176 *  @magn_disabled:     magnetometer disabled for backward compatibility reason.
 177 *  @magn_raw_to_gauss: coefficient to convert mag raw value to Gauss.
 178 *  @magn_orient:       magnetometer sensor chip orientation if available.
 179 *  @suspended_sensors: sensors mask of sensors turned off for suspend
 180 *  @data:              dma safe buffer used for bulk reads.
 181 */
 182struct inv_mpu6050_state {
 183        struct mutex lock;
 184        struct iio_trigger  *trig;
 185        struct inv_mpu6050_chip_config chip_config;
 186        const struct inv_mpu6050_reg_map *reg;
 187        const struct inv_mpu6050_hw *hw;
 188        enum   inv_devices chip_type;
 189        struct i2c_mux_core *muxc;
 190        struct i2c_client *mux_client;
 191        struct inv_mpu6050_platform_data plat_data;
 192        struct iio_mount_matrix orientation;
 193        struct regmap *map;
 194        int irq;
 195        u8 irq_mask;
 196        unsigned skip_samples;
 197        s64 chip_period;
 198        s64 it_timestamp;
 199        s64 data_timestamp;
 200        struct regulator *vdd_supply;
 201        struct regulator *vddio_supply;
 202        bool magn_disabled;
 203        s32 magn_raw_to_gauss[3];
 204        struct iio_mount_matrix magn_orient;
 205        unsigned int suspended_sensors;
 206        u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] ____cacheline_aligned;
 207};
 208
 209/*register and associated bit definition*/
 210#define INV_MPU6050_REG_ACCEL_OFFSET        0x06
 211#define INV_MPU6050_REG_GYRO_OFFSET         0x13
 212
 213#define INV_MPU6050_REG_SAMPLE_RATE_DIV     0x19
 214#define INV_MPU6050_REG_CONFIG              0x1A
 215#define INV_MPU6050_REG_GYRO_CONFIG         0x1B
 216#define INV_MPU6050_REG_ACCEL_CONFIG        0x1C
 217
 218#define INV_MPU6050_REG_FIFO_EN             0x23
 219#define INV_MPU6050_BIT_SLAVE_0             0x01
 220#define INV_MPU6050_BIT_SLAVE_1             0x02
 221#define INV_MPU6050_BIT_SLAVE_2             0x04
 222#define INV_MPU6050_BIT_ACCEL_OUT           0x08
 223#define INV_MPU6050_BITS_GYRO_OUT           0x70
 224#define INV_MPU6050_BIT_TEMP_OUT            0x80
 225
 226#define INV_MPU6050_REG_I2C_MST_CTRL        0x24
 227#define INV_MPU6050_BITS_I2C_MST_CLK_400KHZ 0x0D
 228#define INV_MPU6050_BIT_I2C_MST_P_NSR       0x10
 229#define INV_MPU6050_BIT_SLV3_FIFO_EN        0x20
 230#define INV_MPU6050_BIT_WAIT_FOR_ES         0x40
 231#define INV_MPU6050_BIT_MULT_MST_EN         0x80
 232
 233/* control I2C slaves from 0 to 3 */
 234#define INV_MPU6050_REG_I2C_SLV_ADDR(_x)    (0x25 + 3 * (_x))
 235#define INV_MPU6050_BIT_I2C_SLV_RNW         0x80
 236
 237#define INV_MPU6050_REG_I2C_SLV_REG(_x)     (0x26 + 3 * (_x))
 238
 239#define INV_MPU6050_REG_I2C_SLV_CTRL(_x)    (0x27 + 3 * (_x))
 240#define INV_MPU6050_BIT_SLV_GRP             0x10
 241#define INV_MPU6050_BIT_SLV_REG_DIS         0x20
 242#define INV_MPU6050_BIT_SLV_BYTE_SW         0x40
 243#define INV_MPU6050_BIT_SLV_EN              0x80
 244
 245/* I2C master delay register */
 246#define INV_MPU6050_REG_I2C_SLV4_CTRL       0x34
 247#define INV_MPU6050_BITS_I2C_MST_DLY(_x)    ((_x) & 0x1F)
 248
 249#define INV_MPU6050_REG_I2C_MST_STATUS      0x36
 250#define INV_MPU6050_BIT_I2C_SLV0_NACK       0x01
 251#define INV_MPU6050_BIT_I2C_SLV1_NACK       0x02
 252#define INV_MPU6050_BIT_I2C_SLV2_NACK       0x04
 253#define INV_MPU6050_BIT_I2C_SLV3_NACK       0x08
 254
 255#define INV_MPU6050_REG_INT_ENABLE          0x38
 256#define INV_MPU6050_BIT_DATA_RDY_EN         0x01
 257#define INV_MPU6050_BIT_DMP_INT_EN          0x02
 258
 259#define INV_MPU6050_REG_RAW_ACCEL           0x3B
 260#define INV_MPU6050_REG_TEMPERATURE         0x41
 261#define INV_MPU6050_REG_RAW_GYRO            0x43
 262
 263#define INV_MPU6050_REG_INT_STATUS          0x3A
 264#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT   0x10
 265#define INV_MPU6050_BIT_RAW_DATA_RDY_INT    0x01
 266
 267#define INV_MPU6050_REG_EXT_SENS_DATA       0x49
 268
 269/* I2C slaves data output from 0 to 3 */
 270#define INV_MPU6050_REG_I2C_SLV_DO(_x)      (0x63 + (_x))
 271
 272#define INV_MPU6050_REG_I2C_MST_DELAY_CTRL  0x67
 273#define INV_MPU6050_BIT_I2C_SLV0_DLY_EN     0x01
 274#define INV_MPU6050_BIT_I2C_SLV1_DLY_EN     0x02
 275#define INV_MPU6050_BIT_I2C_SLV2_DLY_EN     0x04
 276#define INV_MPU6050_BIT_I2C_SLV3_DLY_EN     0x08
 277#define INV_MPU6050_BIT_DELAY_ES_SHADOW     0x80
 278
 279#define INV_MPU6050_REG_SIGNAL_PATH_RESET   0x68
 280#define INV_MPU6050_BIT_TEMP_RST            BIT(0)
 281#define INV_MPU6050_BIT_ACCEL_RST           BIT(1)
 282#define INV_MPU6050_BIT_GYRO_RST            BIT(2)
 283
 284#define INV_MPU6050_REG_USER_CTRL           0x6A
 285#define INV_MPU6050_BIT_SIG_COND_RST        0x01
 286#define INV_MPU6050_BIT_FIFO_RST            0x04
 287#define INV_MPU6050_BIT_DMP_RST             0x08
 288#define INV_MPU6050_BIT_I2C_MST_EN          0x20
 289#define INV_MPU6050_BIT_FIFO_EN             0x40
 290#define INV_MPU6050_BIT_DMP_EN              0x80
 291#define INV_MPU6050_BIT_I2C_IF_DIS          0x10
 292
 293#define INV_MPU6050_REG_PWR_MGMT_1          0x6B
 294#define INV_MPU6050_BIT_H_RESET             0x80
 295#define INV_MPU6050_BIT_SLEEP               0x40
 296#define INV_MPU6050_BIT_TEMP_DIS            0x08
 297#define INV_MPU6050_BIT_CLK_MASK            0x7
 298
 299#define INV_MPU6050_REG_PWR_MGMT_2          0x6C
 300#define INV_MPU6050_BIT_PWR_ACCL_STBY       0x38
 301#define INV_MPU6050_BIT_PWR_GYRO_STBY       0x07
 302
 303/* ICM20602 register */
 304#define INV_ICM20602_REG_I2C_IF             0x70
 305#define INV_ICM20602_BIT_I2C_IF_DIS         0x40
 306
 307#define INV_MPU6050_REG_FIFO_COUNT_H        0x72
 308#define INV_MPU6050_REG_FIFO_R_W            0x74
 309
 310#define INV_MPU6050_BYTES_PER_3AXIS_SENSOR   6
 311#define INV_MPU6050_FIFO_COUNT_BYTE          2
 312
 313/* MPU9X50 9-axis magnetometer */
 314#define INV_MPU9X50_BYTES_MAGN               7
 315
 316/* FIFO temperature sample size */
 317#define INV_MPU6050_BYTES_PER_TEMP_SENSOR   2
 318
 319/* mpu6500 registers */
 320#define INV_MPU6500_REG_ACCEL_CONFIG_2      0x1D
 321#define INV_ICM20689_BITS_FIFO_SIZE_MAX     0xC0
 322#define INV_MPU6500_REG_ACCEL_OFFSET        0x77
 323
 324/* delay time in milliseconds */
 325#define INV_MPU6050_POWER_UP_TIME            100
 326#define INV_MPU6050_TEMP_UP_TIME             100
 327#define INV_MPU6050_ACCEL_STARTUP_TIME       20
 328#define INV_MPU6050_GYRO_STARTUP_TIME        60
 329#define INV_MPU6050_GYRO_DOWN_TIME           150
 330#define INV_MPU6050_SUSPEND_DELAY_MS         2000
 331
 332#define INV_MPU6500_GYRO_STARTUP_TIME        70
 333#define INV_MPU6500_ACCEL_STARTUP_TIME       30
 334
 335#define INV_ICM20602_GYRO_STARTUP_TIME       100
 336#define INV_ICM20602_ACCEL_STARTUP_TIME      20
 337
 338#define INV_ICM20690_GYRO_STARTUP_TIME       80
 339#define INV_ICM20690_ACCEL_STARTUP_TIME      10
 340
 341
 342/* delay time in microseconds */
 343#define INV_MPU6050_REG_UP_TIME_MIN          5000
 344#define INV_MPU6050_REG_UP_TIME_MAX          10000
 345
 346#define INV_MPU6050_TEMP_OFFSET              12420
 347#define INV_MPU6050_TEMP_SCALE               2941176
 348#define INV_MPU6050_MAX_GYRO_FS_PARAM        3
 349#define INV_MPU6050_MAX_ACCL_FS_PARAM        3
 350#define INV_MPU6050_THREE_AXIS               3
 351#define INV_MPU6050_GYRO_CONFIG_FSR_SHIFT    3
 352#define INV_ICM20690_GYRO_CONFIG_FSR_SHIFT   2
 353#define INV_MPU6050_ACCL_CONFIG_FSR_SHIFT    3
 354
 355#define INV_MPU6500_TEMP_OFFSET              7011
 356#define INV_MPU6500_TEMP_SCALE               2995178
 357
 358#define INV_ICM20608_TEMP_OFFSET             8170
 359#define INV_ICM20608_TEMP_SCALE              3059976
 360
 361#define INV_MPU6050_REG_INT_PIN_CFG     0x37
 362#define INV_MPU6050_ACTIVE_HIGH         0x00
 363#define INV_MPU6050_ACTIVE_LOW          0x80
 364/* enable level triggering */
 365#define INV_MPU6050_LATCH_INT_EN        0x20
 366#define INV_MPU6050_BIT_BYPASS_EN       0x2
 367
 368/* Allowed timestamp period jitter in percent */
 369#define INV_MPU6050_TS_PERIOD_JITTER    4
 370
 371/* init parameters */
 372#define INV_MPU6050_MAX_FIFO_RATE            1000
 373#define INV_MPU6050_MIN_FIFO_RATE            4
 374
 375/* chip internal frequency: 1KHz */
 376#define INV_MPU6050_INTERNAL_FREQ_HZ            1000
 377/* return the frequency divider (chip sample rate divider + 1) */
 378#define INV_MPU6050_FREQ_DIVIDER(st)                                    \
 379        ((st)->chip_config.divider + 1)
 380/* chip sample rate divider to fifo rate */
 381#define INV_MPU6050_FIFO_RATE_TO_DIVIDER(fifo_rate)                     \
 382        ((INV_MPU6050_INTERNAL_FREQ_HZ / (fifo_rate)) - 1)
 383#define INV_MPU6050_DIVIDER_TO_FIFO_RATE(divider)                       \
 384        (INV_MPU6050_INTERNAL_FREQ_HZ / ((divider) + 1))
 385
 386#define INV_MPU6050_REG_WHOAMI                  117
 387
 388#define INV_MPU6000_WHOAMI_VALUE                0x68
 389#define INV_MPU6050_WHOAMI_VALUE                0x68
 390#define INV_MPU6500_WHOAMI_VALUE                0x70
 391#define INV_MPU6880_WHOAMI_VALUE                0x78
 392#define INV_MPU9150_WHOAMI_VALUE                0x68
 393#define INV_MPU9250_WHOAMI_VALUE                0x71
 394#define INV_MPU9255_WHOAMI_VALUE                0x73
 395#define INV_MPU6515_WHOAMI_VALUE                0x74
 396#define INV_ICM20608_WHOAMI_VALUE               0xAF
 397#define INV_ICM20609_WHOAMI_VALUE               0xA6
 398#define INV_ICM20689_WHOAMI_VALUE               0x98
 399#define INV_ICM20602_WHOAMI_VALUE               0x12
 400#define INV_ICM20690_WHOAMI_VALUE               0x20
 401#define INV_IAM20680_WHOAMI_VALUE               0xA9
 402
 403/* scan element definition for generic MPU6xxx devices */
 404enum inv_mpu6050_scan {
 405        INV_MPU6050_SCAN_ACCL_X,
 406        INV_MPU6050_SCAN_ACCL_Y,
 407        INV_MPU6050_SCAN_ACCL_Z,
 408        INV_MPU6050_SCAN_TEMP,
 409        INV_MPU6050_SCAN_GYRO_X,
 410        INV_MPU6050_SCAN_GYRO_Y,
 411        INV_MPU6050_SCAN_GYRO_Z,
 412        INV_MPU6050_SCAN_TIMESTAMP,
 413
 414        INV_MPU9X50_SCAN_MAGN_X = INV_MPU6050_SCAN_GYRO_Z + 1,
 415        INV_MPU9X50_SCAN_MAGN_Y,
 416        INV_MPU9X50_SCAN_MAGN_Z,
 417        INV_MPU9X50_SCAN_TIMESTAMP,
 418};
 419
 420enum inv_mpu6050_filter_e {
 421        INV_MPU6050_FILTER_NOLPF2 = 0,
 422        INV_MPU6050_FILTER_200HZ,
 423        INV_MPU6050_FILTER_100HZ,
 424        INV_MPU6050_FILTER_45HZ,
 425        INV_MPU6050_FILTER_20HZ,
 426        INV_MPU6050_FILTER_10HZ,
 427        INV_MPU6050_FILTER_5HZ,
 428        INV_MPU6050_FILTER_NOLPF,
 429        NUM_MPU6050_FILTER
 430};
 431
 432/* IIO attribute address */
 433enum INV_MPU6050_IIO_ATTR_ADDR {
 434        ATTR_GYRO_MATRIX,
 435        ATTR_ACCL_MATRIX,
 436};
 437
 438enum inv_mpu6050_accl_fs_e {
 439        INV_MPU6050_FS_02G = 0,
 440        INV_MPU6050_FS_04G,
 441        INV_MPU6050_FS_08G,
 442        INV_MPU6050_FS_16G,
 443        NUM_ACCL_FSR
 444};
 445
 446enum inv_mpu6050_fsr_e {
 447        INV_MPU6050_FSR_250DPS = 0,
 448        INV_MPU6050_FSR_500DPS,
 449        INV_MPU6050_FSR_1000DPS,
 450        INV_MPU6050_FSR_2000DPS,
 451        NUM_MPU6050_FSR
 452};
 453
 454enum inv_mpu6050_clock_sel_e {
 455        INV_CLK_INTERNAL = 0,
 456        INV_CLK_PLL,
 457        NUM_CLK
 458};
 459
 460irqreturn_t inv_mpu6050_read_fifo(int irq, void *p);
 461int inv_mpu6050_probe_trigger(struct iio_dev *indio_dev, int irq_type);
 462int inv_mpu6050_prepare_fifo(struct inv_mpu6050_state *st, bool enable);
 463int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en,
 464                              unsigned int mask);
 465int inv_mpu6050_write_reg(struct inv_mpu6050_state *st, int reg, u8 val);
 466int inv_mpu_acpi_create_mux_client(struct i2c_client *client);
 467void inv_mpu_acpi_delete_mux_client(struct i2c_client *client);
 468int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
 469                int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type);
 470extern const struct dev_pm_ops inv_mpu_pmops;
 471
 472#endif
 473