1
2
3
4
5
6#include <linux/firmware.h>
7#include <linux/mutex.h>
8#include <linux/module.h>
9#include <linux/delay.h>
10#include <linux/crc32.h>
11
12#include "hfi.h"
13#include "trace.h"
14
15
16
17
18
19
20#define DEFAULT_FW_8051_NAME_FPGA "hfi_dc8051.bin"
21#define DEFAULT_FW_8051_NAME_ASIC "hfi1_dc8051.fw"
22#define DEFAULT_FW_FABRIC_NAME "hfi1_fabric.fw"
23#define DEFAULT_FW_SBUS_NAME "hfi1_sbus.fw"
24#define DEFAULT_FW_PCIE_NAME "hfi1_pcie.fw"
25#define ALT_FW_8051_NAME_ASIC "hfi1_dc8051_d.fw"
26#define ALT_FW_FABRIC_NAME "hfi1_fabric_d.fw"
27#define ALT_FW_SBUS_NAME "hfi1_sbus_d.fw"
28#define ALT_FW_PCIE_NAME "hfi1_pcie_d.fw"
29
30MODULE_FIRMWARE(DEFAULT_FW_8051_NAME_ASIC);
31MODULE_FIRMWARE(DEFAULT_FW_FABRIC_NAME);
32MODULE_FIRMWARE(DEFAULT_FW_SBUS_NAME);
33MODULE_FIRMWARE(DEFAULT_FW_PCIE_NAME);
34
35static uint fw_8051_load = 1;
36static uint fw_fabric_serdes_load = 1;
37static uint fw_pcie_serdes_load = 1;
38static uint fw_sbus_load = 1;
39
40
41static char *fw_8051_name;
42static char *fw_fabric_serdes_name;
43static char *fw_sbus_name;
44static char *fw_pcie_serdes_name;
45
46#define SBUS_MAX_POLL_COUNT 100
47#define SBUS_COUNTER(reg, name) \
48 (((reg) >> ASIC_STS_SBUS_COUNTERS_##name##_CNT_SHIFT) & \
49 ASIC_STS_SBUS_COUNTERS_##name##_CNT_MASK)
50
51
52
53
54struct css_header {
55 u32 module_type;
56 u32 header_len;
57 u32 header_version;
58 u32 module_id;
59 u32 module_vendor;
60 u32 date;
61 u32 size;
62 u32 key_size;
63 u32 modulus_size;
64 u32 exponent_size;
65 u32 reserved[22];
66};
67
68
69#define CSS_MODULE_TYPE 0x00000006
70#define CSS_HEADER_LEN 0x000000a1
71#define CSS_HEADER_VERSION 0x00010000
72#define CSS_MODULE_VENDOR 0x00008086
73
74#define KEY_SIZE 256
75#define MU_SIZE 8
76#define EXPONENT_SIZE 4
77
78
79#define MAX_PLATFORM_CONFIG_FILE_SIZE 4096
80
81
82#define PLATFORM_CONFIG_FORMAT_4_FILE_SIZE 528
83
84
85struct firmware_file {
86 struct css_header css_header;
87 u8 modulus[KEY_SIZE];
88 u8 exponent[EXPONENT_SIZE];
89 u8 signature[KEY_SIZE];
90 u8 firmware[];
91};
92
93struct augmented_firmware_file {
94 struct css_header css_header;
95 u8 modulus[KEY_SIZE];
96 u8 exponent[EXPONENT_SIZE];
97 u8 signature[KEY_SIZE];
98 u8 r2[KEY_SIZE];
99 u8 mu[MU_SIZE];
100 u8 firmware[];
101};
102
103
104#define AUGMENT_SIZE (sizeof(struct augmented_firmware_file) - \
105 sizeof(struct firmware_file))
106
107struct firmware_details {
108
109 const struct firmware *fw;
110
111 struct css_header *css_header;
112 u8 *firmware_ptr;
113 u32 firmware_len;
114 u8 *modulus;
115 u8 *exponent;
116 u8 *signature;
117 u8 *r2;
118 u8 *mu;
119 struct augmented_firmware_file dummy_header;
120};
121
122
123
124
125
126static DEFINE_MUTEX(fw_mutex);
127enum fw_state {
128 FW_EMPTY,
129 FW_TRY,
130 FW_FINAL,
131 FW_ERR
132};
133
134static enum fw_state fw_state = FW_EMPTY;
135static int fw_err;
136static struct firmware_details fw_8051;
137static struct firmware_details fw_fabric;
138static struct firmware_details fw_pcie;
139static struct firmware_details fw_sbus;
140
141
142#define SPICO_SBUS 0x1
143#define SPICO_FABRIC 0x2
144#define ENABLE_SPICO_SMASK 0x1
145
146
147#define RSA_CMD_INIT 0x1
148#define RSA_CMD_START 0x2
149
150
151#define RSA_STATUS_IDLE 0x0
152#define RSA_STATUS_ACTIVE 0x1
153#define RSA_STATUS_DONE 0x2
154#define RSA_STATUS_FAILED 0x3
155
156
157#define RSA_ENGINE_TIMEOUT 100
158
159
160#define HM_TIMEOUT 10
161
162
163#define DC8051_ACCESS_TIMEOUT 100
164
165
166#define NUM_FABRIC_SERDES 4
167
168
169#define SBUS_READ_COMPLETE 0x4
170
171
172static const u8 fabric_serdes_addrs[2][NUM_FABRIC_SERDES] = {
173 { 0x01, 0x02, 0x03, 0x04 },
174 { 0x28, 0x29, 0x2a, 0x2b }
175};
176
177
178static const u8 pcie_serdes_addrs[2][NUM_PCIE_SERDES] = {
179 { 0x08, 0x0a, 0x0c, 0x0e, 0x10, 0x12, 0x14, 0x16,
180 0x18, 0x1a, 0x1c, 0x1e, 0x20, 0x22, 0x24, 0x26 },
181 { 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d,
182 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d }
183};
184
185
186const u8 pcie_pcs_addrs[2][NUM_PCIE_SERDES] = {
187 { 0x09, 0x0b, 0x0d, 0x0f, 0x11, 0x13, 0x15, 0x17,
188 0x19, 0x1b, 0x1d, 0x1f, 0x21, 0x23, 0x25, 0x27 },
189 { 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e,
190 0x40, 0x42, 0x44, 0x46, 0x48, 0x4a, 0x4c, 0x4e }
191};
192
193
194static const u8 fabric_serdes_broadcast[2] = { 0xe4, 0xe5 };
195static const u8 all_fabric_serdes_broadcast = 0xe1;
196
197
198const u8 pcie_serdes_broadcast[2] = { 0xe2, 0xe3 };
199static const u8 all_pcie_serdes_broadcast = 0xe0;
200
201static const u32 platform_config_table_limits[PLATFORM_CONFIG_TABLE_MAX] = {
202 0,
203 SYSTEM_TABLE_MAX,
204 PORT_TABLE_MAX,
205 RX_PRESET_TABLE_MAX,
206 TX_PRESET_TABLE_MAX,
207 QSFP_ATTEN_TABLE_MAX,
208 VARIABLE_SETTINGS_TABLE_MAX
209};
210
211
212static void dispose_one_firmware(struct firmware_details *fdet);
213static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
214 struct firmware_details *fdet);
215static void dump_fw_version(struct hfi1_devdata *dd);
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230static int __read_8051_data(struct hfi1_devdata *dd, u32 addr, u64 *result)
231{
232 u64 reg;
233 int count;
234
235
236 reg = (addr & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
237 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT;
238 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
239
240 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL,
241 reg | DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK);
242
243
244 count = 0;
245 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
246 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
247 == 0) {
248 count++;
249 if (count > DC8051_ACCESS_TIMEOUT) {
250 dd_dev_err(dd, "timeout reading 8051 data\n");
251 return -ENXIO;
252 }
253 ndelay(10);
254 }
255
256
257 *result = read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_RD_DATA);
258
259 return 0;
260}
261
262
263
264
265
266int read_8051_data(struct hfi1_devdata *dd, u32 addr, u32 len, u64 *result)
267{
268 unsigned long flags;
269 u32 done;
270 int ret = 0;
271
272 spin_lock_irqsave(&dd->dc8051_memlock, flags);
273
274
275 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
276
277 for (done = 0; done < len; addr += 8, done += 8, result++) {
278 ret = __read_8051_data(dd, addr, result);
279 if (ret)
280 break;
281 }
282
283
284 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
285
286 spin_unlock_irqrestore(&dd->dc8051_memlock, flags);
287
288 return ret;
289}
290
291
292
293
294static int write_8051(struct hfi1_devdata *dd, int code, u32 start,
295 const u8 *data, u32 len)
296{
297 u64 reg;
298 u32 offset;
299 int aligned, count;
300
301
302 aligned = ((unsigned long)data & 0x7) == 0;
303
304
305 reg = (code ? DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK : 0ull)
306 | DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK;
307 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, reg);
308
309 reg = ((start & DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK)
310 << DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT)
311 | DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK;
312 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, reg);
313
314
315 for (offset = 0; offset < len; offset += 8) {
316 int bytes = len - offset;
317
318 if (bytes < 8) {
319 reg = 0;
320 memcpy(®, &data[offset], bytes);
321 } else if (aligned) {
322 reg = *(u64 *)&data[offset];
323 } else {
324 memcpy(®, &data[offset], 8);
325 }
326 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_WR_DATA, reg);
327
328
329 count = 0;
330 while ((read_csr(dd, DC_DC8051_CFG_RAM_ACCESS_STATUS)
331 & DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK)
332 == 0) {
333 count++;
334 if (count > DC8051_ACCESS_TIMEOUT) {
335 dd_dev_err(dd, "timeout writing 8051 data\n");
336 return -ENXIO;
337 }
338 udelay(1);
339 }
340 }
341
342
343 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_CTRL, 0);
344 write_csr(dd, DC_DC8051_CFG_RAM_ACCESS_SETUP, 0);
345
346 return 0;
347}
348
349
350static int invalid_header(struct hfi1_devdata *dd, const char *what,
351 u32 actual, u32 expected)
352{
353 if (actual == expected)
354 return 0;
355
356 dd_dev_err(dd,
357 "invalid firmware header field %s: expected 0x%x, actual 0x%x\n",
358 what, expected, actual);
359 return 1;
360}
361
362
363
364
365static int verify_css_header(struct hfi1_devdata *dd, struct css_header *css)
366{
367
368 if (invalid_header(dd, "module_type", css->module_type,
369 CSS_MODULE_TYPE) ||
370 invalid_header(dd, "header_len", css->header_len,
371 (sizeof(struct firmware_file) / 4)) ||
372 invalid_header(dd, "header_version", css->header_version,
373 CSS_HEADER_VERSION) ||
374 invalid_header(dd, "module_vendor", css->module_vendor,
375 CSS_MODULE_VENDOR) ||
376 invalid_header(dd, "key_size", css->key_size, KEY_SIZE / 4) ||
377 invalid_header(dd, "modulus_size", css->modulus_size,
378 KEY_SIZE / 4) ||
379 invalid_header(dd, "exponent_size", css->exponent_size,
380 EXPONENT_SIZE / 4)) {
381 return -EINVAL;
382 }
383 return 0;
384}
385
386
387
388
389static int payload_check(struct hfi1_devdata *dd, const char *name,
390 long file_size, long prefix_size)
391{
392
393 if (prefix_size >= file_size) {
394 dd_dev_err(dd,
395 "firmware \"%s\", size %ld, must be larger than %ld bytes\n",
396 name, file_size, prefix_size);
397 return -EINVAL;
398 }
399
400 return 0;
401}
402
403
404
405
406
407
408static int obtain_one_firmware(struct hfi1_devdata *dd, const char *name,
409 struct firmware_details *fdet)
410{
411 struct css_header *css;
412 int ret;
413
414 memset(fdet, 0, sizeof(*fdet));
415
416 ret = request_firmware(&fdet->fw, name, &dd->pcidev->dev);
417 if (ret) {
418 dd_dev_warn(dd, "cannot find firmware \"%s\", err %d\n",
419 name, ret);
420 return ret;
421 }
422
423
424 if (fdet->fw->size < sizeof(struct css_header)) {
425 dd_dev_err(dd, "firmware \"%s\" is too small\n", name);
426 ret = -EINVAL;
427 goto done;
428 }
429 css = (struct css_header *)fdet->fw->data;
430
431 hfi1_cdbg(FIRMWARE, "Firmware %s details:", name);
432 hfi1_cdbg(FIRMWARE, "file size: 0x%lx bytes", fdet->fw->size);
433 hfi1_cdbg(FIRMWARE, "CSS structure:");
434 hfi1_cdbg(FIRMWARE, " module_type 0x%x", css->module_type);
435 hfi1_cdbg(FIRMWARE, " header_len 0x%03x (0x%03x bytes)",
436 css->header_len, 4 * css->header_len);
437 hfi1_cdbg(FIRMWARE, " header_version 0x%x", css->header_version);
438 hfi1_cdbg(FIRMWARE, " module_id 0x%x", css->module_id);
439 hfi1_cdbg(FIRMWARE, " module_vendor 0x%x", css->module_vendor);
440 hfi1_cdbg(FIRMWARE, " date 0x%x", css->date);
441 hfi1_cdbg(FIRMWARE, " size 0x%03x (0x%03x bytes)",
442 css->size, 4 * css->size);
443 hfi1_cdbg(FIRMWARE, " key_size 0x%03x (0x%03x bytes)",
444 css->key_size, 4 * css->key_size);
445 hfi1_cdbg(FIRMWARE, " modulus_size 0x%03x (0x%03x bytes)",
446 css->modulus_size, 4 * css->modulus_size);
447 hfi1_cdbg(FIRMWARE, " exponent_size 0x%03x (0x%03x bytes)",
448 css->exponent_size, 4 * css->exponent_size);
449 hfi1_cdbg(FIRMWARE, "firmware size: 0x%lx bytes",
450 fdet->fw->size - sizeof(struct firmware_file));
451
452
453
454
455
456
457
458
459
460
461
462 ret = verify_css_header(dd, css);
463 if (ret) {
464 dd_dev_info(dd, "Invalid CSS header for \"%s\"\n", name);
465 } else if ((css->size * 4) == fdet->fw->size) {
466
467 struct firmware_file *ff = (struct firmware_file *)
468 fdet->fw->data;
469
470
471 ret = payload_check(dd, name, fdet->fw->size,
472 sizeof(struct firmware_file));
473 if (ret == 0) {
474 fdet->css_header = css;
475 fdet->modulus = ff->modulus;
476 fdet->exponent = ff->exponent;
477 fdet->signature = ff->signature;
478 fdet->r2 = fdet->dummy_header.r2;
479 fdet->mu = fdet->dummy_header.mu;
480 fdet->firmware_ptr = ff->firmware;
481 fdet->firmware_len = fdet->fw->size -
482 sizeof(struct firmware_file);
483
484
485
486
487 dd_dev_err(dd, "driver is unable to validate firmware without r2 and mu (not in firmware file)\n");
488 ret = -EINVAL;
489 }
490 } else if ((css->size * 4) + AUGMENT_SIZE == fdet->fw->size) {
491
492 struct augmented_firmware_file *aff =
493 (struct augmented_firmware_file *)fdet->fw->data;
494
495
496 ret = payload_check(dd, name, fdet->fw->size,
497 sizeof(struct augmented_firmware_file));
498 if (ret == 0) {
499 fdet->css_header = css;
500 fdet->modulus = aff->modulus;
501 fdet->exponent = aff->exponent;
502 fdet->signature = aff->signature;
503 fdet->r2 = aff->r2;
504 fdet->mu = aff->mu;
505 fdet->firmware_ptr = aff->firmware;
506 fdet->firmware_len = fdet->fw->size -
507 sizeof(struct augmented_firmware_file);
508 }
509 } else {
510
511 dd_dev_err(dd,
512 "invalid firmware header field size: expected 0x%lx or 0x%lx, actual 0x%x\n",
513 fdet->fw->size / 4,
514 (fdet->fw->size - AUGMENT_SIZE) / 4,
515 css->size);
516
517 ret = -EINVAL;
518 }
519
520done:
521
522 if (ret)
523 dispose_one_firmware(fdet);
524 return ret;
525}
526
527static void dispose_one_firmware(struct firmware_details *fdet)
528{
529 release_firmware(fdet->fw);
530
531 memset(fdet, 0, sizeof(*fdet));
532}
533
534
535
536
537
538
539
540
541
542static void __obtain_firmware(struct hfi1_devdata *dd)
543{
544 int err = 0;
545
546 if (fw_state == FW_FINAL)
547 return;
548 if (fw_state == FW_ERR)
549 return;
550
551
552retry:
553 if (fw_state == FW_TRY) {
554
555
556
557
558 dd_dev_warn(dd, "using alternate firmware names\n");
559
560
561
562
563
564 cond_resched();
565 if (fw_8051_load)
566 dispose_one_firmware(&fw_8051);
567 if (fw_fabric_serdes_load)
568 dispose_one_firmware(&fw_fabric);
569 if (fw_sbus_load)
570 dispose_one_firmware(&fw_sbus);
571 if (fw_pcie_serdes_load)
572 dispose_one_firmware(&fw_pcie);
573 fw_8051_name = ALT_FW_8051_NAME_ASIC;
574 fw_fabric_serdes_name = ALT_FW_FABRIC_NAME;
575 fw_sbus_name = ALT_FW_SBUS_NAME;
576 fw_pcie_serdes_name = ALT_FW_PCIE_NAME;
577
578
579
580
581
582
583
584 usleep_range(100, 120);
585 }
586
587 if (fw_sbus_load) {
588 err = obtain_one_firmware(dd, fw_sbus_name, &fw_sbus);
589 if (err)
590 goto done;
591 }
592
593 if (fw_pcie_serdes_load) {
594 err = obtain_one_firmware(dd, fw_pcie_serdes_name, &fw_pcie);
595 if (err)
596 goto done;
597 }
598
599 if (fw_fabric_serdes_load) {
600 err = obtain_one_firmware(dd, fw_fabric_serdes_name,
601 &fw_fabric);
602 if (err)
603 goto done;
604 }
605
606 if (fw_8051_load) {
607 err = obtain_one_firmware(dd, fw_8051_name, &fw_8051);
608 if (err)
609 goto done;
610 }
611
612done:
613 if (err) {
614
615 if (fw_state == FW_EMPTY && dd->icode == ICODE_RTL_SILICON) {
616
617 fw_state = FW_TRY;
618 goto retry;
619 }
620 dd_dev_err(dd, "unable to obtain working firmware\n");
621 fw_state = FW_ERR;
622 fw_err = -ENOENT;
623 } else {
624
625 if (fw_state == FW_EMPTY &&
626 dd->icode != ICODE_FUNCTIONAL_SIMULATOR)
627 fw_state = FW_TRY;
628 else
629 fw_state = FW_FINAL;
630 }
631}
632
633
634
635
636
637
638
639
640
641
642static int obtain_firmware(struct hfi1_devdata *dd)
643{
644 unsigned long timeout;
645
646 mutex_lock(&fw_mutex);
647
648
649 timeout = jiffies + msecs_to_jiffies(40000);
650 while (fw_state == FW_TRY) {
651
652
653
654
655 if (time_after(jiffies, timeout)) {
656
657 dd_dev_err(dd, "Timeout waiting for firmware try");
658 fw_state = FW_ERR;
659 fw_err = -ETIMEDOUT;
660 break;
661 }
662 mutex_unlock(&fw_mutex);
663 msleep(20);
664 mutex_lock(&fw_mutex);
665 }
666
667
668
669 if (fw_state == FW_EMPTY)
670 __obtain_firmware(dd);
671
672 mutex_unlock(&fw_mutex);
673 return fw_err;
674}
675
676
677
678
679
680
681
682
683
684
685
686
687void dispose_firmware(void)
688{
689 dispose_one_firmware(&fw_8051);
690 dispose_one_firmware(&fw_fabric);
691 dispose_one_firmware(&fw_pcie);
692 dispose_one_firmware(&fw_sbus);
693
694
695 if (fw_state != FW_ERR)
696 fw_state = FW_EMPTY;
697}
698
699
700
701
702
703
704static int retry_firmware(struct hfi1_devdata *dd, int load_result)
705{
706 int retry;
707
708 mutex_lock(&fw_mutex);
709
710 if (load_result == 0) {
711
712
713
714
715 if (fw_state == FW_TRY)
716 fw_state = FW_FINAL;
717 retry = 0;
718 } else if (fw_state == FW_TRY) {
719
720 __obtain_firmware(dd);
721 retry = (fw_state == FW_FINAL);
722 } else {
723
724 retry = 0;
725 }
726
727 mutex_unlock(&fw_mutex);
728 return retry;
729}
730
731
732
733
734
735static void write_rsa_data(struct hfi1_devdata *dd, int what,
736 const u8 *data, int nbytes)
737{
738 int qw_size = nbytes / 8;
739 int i;
740
741 if (((unsigned long)data & 0x7) == 0) {
742
743 u64 *ptr = (u64 *)data;
744
745 for (i = 0; i < qw_size; i++, ptr++)
746 write_csr(dd, what + (8 * i), *ptr);
747 } else {
748
749 for (i = 0; i < qw_size; i++, data += 8) {
750 u64 value;
751
752 memcpy(&value, data, 8);
753 write_csr(dd, what + (8 * i), value);
754 }
755 }
756}
757
758
759
760
761
762static void write_streamed_rsa_data(struct hfi1_devdata *dd, int what,
763 const u8 *data, int nbytes)
764{
765 u64 *ptr = (u64 *)data;
766 int qw_size = nbytes / 8;
767
768 for (; qw_size > 0; qw_size--, ptr++)
769 write_csr(dd, what, *ptr);
770}
771
772
773
774
775
776static int run_rsa(struct hfi1_devdata *dd, const char *who,
777 const u8 *signature)
778{
779 unsigned long timeout;
780 u64 reg;
781 u32 status;
782 int ret = 0;
783
784
785 write_rsa_data(dd, MISC_CFG_RSA_SIGNATURE, signature, KEY_SIZE);
786
787
788 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_INIT);
789
790
791
792
793
794 status = (read_csr(dd, MISC_CFG_FW_CTRL)
795 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
796 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
797 if (status != RSA_STATUS_IDLE) {
798 dd_dev_err(dd, "%s security engine not idle - giving up\n",
799 who);
800 return -EBUSY;
801 }
802
803
804 write_csr(dd, MISC_CFG_RSA_CMD, RSA_CMD_START);
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827 timeout = msecs_to_jiffies(RSA_ENGINE_TIMEOUT) + jiffies;
828 while (1) {
829 status = (read_csr(dd, MISC_CFG_FW_CTRL)
830 & MISC_CFG_FW_CTRL_RSA_STATUS_SMASK)
831 >> MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT;
832
833 if (status == RSA_STATUS_IDLE) {
834
835 dd_dev_err(dd, "%s firmware security bad idle state\n",
836 who);
837 ret = -EINVAL;
838 break;
839 } else if (status == RSA_STATUS_DONE) {
840
841 break;
842 } else if (status == RSA_STATUS_FAILED) {
843
844 ret = -EINVAL;
845 break;
846 }
847
848
849 if (time_after(jiffies, timeout)) {
850
851
852
853
854
855 dd_dev_err(dd, "%s firmware security time out\n", who);
856 ret = -ETIMEDOUT;
857 break;
858 }
859
860 msleep(20);
861 }
862
863
864
865
866
867
868
869 write_csr(dd, MISC_ERR_CLEAR,
870 MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK |
871 MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK);
872
873
874
875
876
877 reg = read_csr(dd, MISC_ERR_STATUS);
878 if (ret) {
879 if (reg & MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK)
880 dd_dev_warn(dd, "%s firmware authorization failed\n",
881 who);
882 if (reg & MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK)
883 dd_dev_warn(dd, "%s firmware key mismatch\n", who);
884 }
885
886 return ret;
887}
888
889static void load_security_variables(struct hfi1_devdata *dd,
890 struct firmware_details *fdet)
891{
892
893 write_rsa_data(dd, MISC_CFG_RSA_MODULUS, fdet->modulus, KEY_SIZE);
894
895 write_rsa_data(dd, MISC_CFG_RSA_R2, fdet->r2, KEY_SIZE);
896
897 write_rsa_data(dd, MISC_CFG_RSA_MU, fdet->mu, MU_SIZE);
898
899 write_streamed_rsa_data(dd, MISC_CFG_SHA_PRELOAD,
900 (u8 *)fdet->css_header,
901 sizeof(struct css_header));
902}
903
904
905static inline u32 get_firmware_state(struct hfi1_devdata *dd)
906{
907 u64 reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);
908
909 return (reg >> DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT)
910 & DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK;
911}
912
913
914
915
916
917int wait_fm_ready(struct hfi1_devdata *dd, u32 mstimeout)
918{
919 unsigned long timeout;
920
921
922 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
923 return 0;
924
925 timeout = msecs_to_jiffies(mstimeout) + jiffies;
926 while (1) {
927 if (get_firmware_state(dd) == 0xa0)
928 return 0;
929 if (time_after(jiffies, timeout))
930 return -ETIMEDOUT;
931 usleep_range(1950, 2050);
932 }
933}
934
935
936
937
938static int load_8051_firmware(struct hfi1_devdata *dd,
939 struct firmware_details *fdet)
940{
941 u64 reg;
942 int ret;
943 u8 ver_major;
944 u8 ver_minor;
945 u8 ver_patch;
946
947
948
949
950
951
952
953
954 reg = DC_DC8051_CFG_RST_M8051W_SMASK
955 | DC_DC8051_CFG_RST_CRAM_SMASK
956 | DC_DC8051_CFG_RST_DRAM_SMASK
957 | DC_DC8051_CFG_RST_IRAM_SMASK
958 | DC_DC8051_CFG_RST_SFR_SMASK;
959 write_csr(dd, DC_DC8051_CFG_RST, reg);
960
961
962
963
964
965
966
967
968
969
970 reg = DC_DC8051_CFG_RST_M8051W_SMASK;
971 write_csr(dd, DC_DC8051_CFG_RST, reg);
972
973
974 load_security_variables(dd, fdet);
975
976
977
978
979 write_csr(dd, MISC_CFG_FW_CTRL, 0);
980
981
982 ret = write_8051(dd, 1, 0, fdet->firmware_ptr,
983 fdet->firmware_len);
984 if (ret)
985 return ret;
986
987
988
989
990
991
992
993 write_csr(dd, MISC_CFG_FW_CTRL, MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK);
994
995
996 ret = run_rsa(dd, "8051", fdet->signature);
997 if (ret)
998 return ret;
999
1000
1001 write_csr(dd, DC_DC8051_CFG_RST, 0ull);
1002
1003
1004
1005
1006
1007 ret = wait_fm_ready(dd, TIMEOUT_8051_START);
1008 if (ret) {
1009 dd_dev_err(dd, "8051 start timeout, current state 0x%x\n",
1010 get_firmware_state(dd));
1011 return -ETIMEDOUT;
1012 }
1013
1014 read_misc_status(dd, &ver_major, &ver_minor, &ver_patch);
1015 dd_dev_info(dd, "8051 firmware version %d.%d.%d\n",
1016 (int)ver_major, (int)ver_minor, (int)ver_patch);
1017 dd->dc8051_ver = dc8051_ver(ver_major, ver_minor, ver_patch);
1018 ret = write_host_interface_version(dd, HOST_INTERFACE_VERSION);
1019 if (ret != HCMD_SUCCESS) {
1020 dd_dev_err(dd,
1021 "Failed to set host interface version, return 0x%x\n",
1022 ret);
1023 return -EIO;
1024 }
1025
1026 return 0;
1027}
1028
1029
1030
1031
1032
1033
1034void sbus_request(struct hfi1_devdata *dd,
1035 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1036{
1037 write_csr(dd, ASIC_CFG_SBUS_REQUEST,
1038 ((u64)data_in << ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT) |
1039 ((u64)command << ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT) |
1040 ((u64)data_addr << ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT) |
1041 ((u64)receiver_addr <<
1042 ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT));
1043}
1044
1045
1046
1047
1048
1049
1050static u32 sbus_read(struct hfi1_devdata *dd, u8 receiver_addr, u8 data_addr,
1051 u32 data_in)
1052{
1053 u64 reg;
1054 int retries;
1055 int success = 0;
1056 u32 result = 0;
1057 u32 result_code = 0;
1058
1059 sbus_request(dd, receiver_addr, data_addr, READ_SBUS_RECEIVER, data_in);
1060
1061 for (retries = 0; retries < 100; retries++) {
1062 usleep_range(1000, 1200);
1063 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1064 result_code = (reg >> ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT)
1065 & ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK;
1066 if (result_code != SBUS_READ_COMPLETE)
1067 continue;
1068
1069 success = 1;
1070 result = (reg >> ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT)
1071 & ASIC_STS_SBUS_RESULT_DATA_OUT_MASK;
1072 break;
1073 }
1074
1075 if (!success) {
1076 dd_dev_err(dd, "%s: read failed, result code 0x%x\n", __func__,
1077 result_code);
1078 }
1079
1080 return result;
1081}
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091static void turn_off_spicos(struct hfi1_devdata *dd, int flags)
1092{
1093
1094 if (!is_ax(dd))
1095 return;
1096
1097 dd_dev_info(dd, "Turning off spicos:%s%s\n",
1098 flags & SPICO_SBUS ? " SBus" : "",
1099 flags & SPICO_FABRIC ? " fabric" : "");
1100
1101 write_csr(dd, MISC_CFG_FW_CTRL, ENABLE_SPICO_SMASK);
1102
1103 if (flags & SPICO_SBUS)
1104 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x01,
1105 WRITE_SBUS_RECEIVER, 0x00000040);
1106
1107
1108 if (flags & SPICO_FABRIC)
1109 sbus_request(dd, fabric_serdes_broadcast[dd->hfi1_id],
1110 0x07, WRITE_SBUS_RECEIVER, 0x00000000);
1111 write_csr(dd, MISC_CFG_FW_CTRL, 0);
1112}
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128void fabric_serdes_reset(struct hfi1_devdata *dd)
1129{
1130 int ret;
1131
1132 if (!fw_fabric_serdes_load)
1133 return;
1134
1135 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1136 if (ret) {
1137 dd_dev_err(dd,
1138 "Cannot acquire SBus resource to reset fabric SerDes - perhaps you should reboot\n");
1139 return;
1140 }
1141 set_sbus_fast_mode(dd);
1142
1143 if (is_ax(dd)) {
1144
1145 u8 ra = fabric_serdes_broadcast[dd->hfi1_id];
1146
1147
1148 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1149
1150 udelay(1);
1151
1152 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1153
1154 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1155 } else {
1156 turn_off_spicos(dd, SPICO_FABRIC);
1157
1158
1159
1160
1161
1162
1163
1164 (void)load_fabric_serdes_firmware(dd, &fw_fabric);
1165 }
1166
1167 clear_sbus_fast_mode(dd);
1168 release_chip_resource(dd, CR_SBUS);
1169}
1170
1171
1172int sbus_request_slow(struct hfi1_devdata *dd,
1173 u8 receiver_addr, u8 data_addr, u8 command, u32 data_in)
1174{
1175 u64 reg, count = 0;
1176
1177
1178 clear_sbus_fast_mode(dd);
1179
1180 sbus_request(dd, receiver_addr, data_addr, command, data_in);
1181 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1182 ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK);
1183
1184 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1185 while (!((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1186 (reg & ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK))) {
1187 if (count++ >= SBUS_MAX_POLL_COUNT) {
1188 u64 counts = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1189
1190
1191
1192
1193
1194 if ((reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) &&
1195 (SBUS_COUNTER(counts, RCV_DATA_VALID) ==
1196 SBUS_COUNTER(counts, EXECUTE)))
1197 break;
1198 return -ETIMEDOUT;
1199 }
1200 udelay(1);
1201 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1202 }
1203 count = 0;
1204 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1205
1206 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1207 while (reg & ASIC_STS_SBUS_RESULT_DONE_SMASK) {
1208 if (count++ >= SBUS_MAX_POLL_COUNT)
1209 return -ETIME;
1210 udelay(1);
1211 reg = read_csr(dd, ASIC_STS_SBUS_RESULT);
1212 }
1213 return 0;
1214}
1215
1216static int load_fabric_serdes_firmware(struct hfi1_devdata *dd,
1217 struct firmware_details *fdet)
1218{
1219 int i, err;
1220 const u8 ra = fabric_serdes_broadcast[dd->hfi1_id];
1221
1222 dd_dev_info(dd, "Downloading fabric firmware\n");
1223
1224
1225 load_security_variables(dd, fdet);
1226
1227 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000011);
1228
1229 udelay(1);
1230
1231 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000010);
1232
1233 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x40000000);
1234
1235 for (i = 0; i < fdet->firmware_len; i += 4) {
1236 sbus_request(dd, ra, 0x0a, WRITE_SBUS_RECEIVER,
1237 *(u32 *)&fdet->firmware_ptr[i]);
1238 }
1239
1240 sbus_request(dd, ra, 0x00, WRITE_SBUS_RECEIVER, 0x00000000);
1241
1242 sbus_request(dd, ra, 0x0b, WRITE_SBUS_RECEIVER, 0x000c0000);
1243
1244
1245 err = run_rsa(dd, "fabric serdes", fdet->signature);
1246 if (err)
1247 return err;
1248
1249
1250 sbus_request(dd, ra, 0x07, WRITE_SBUS_RECEIVER, 0x00000002);
1251
1252 sbus_request(dd, ra, 0x08, WRITE_SBUS_RECEIVER, 0x00000000);
1253
1254 return 0;
1255}
1256
1257static int load_sbus_firmware(struct hfi1_devdata *dd,
1258 struct firmware_details *fdet)
1259{
1260 int i, err;
1261 const u8 ra = SBUS_MASTER_BROADCAST;
1262
1263 dd_dev_info(dd, "Downloading SBus firmware\n");
1264
1265
1266 load_security_variables(dd, fdet);
1267
1268 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x000000c0);
1269
1270 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000240);
1271
1272 sbus_request(dd, ra, 0x03, WRITE_SBUS_RECEIVER, 0x80000000);
1273
1274 for (i = 0; i < fdet->firmware_len; i += 4) {
1275 sbus_request(dd, ra, 0x14, WRITE_SBUS_RECEIVER,
1276 *(u32 *)&fdet->firmware_ptr[i]);
1277 }
1278
1279 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000040);
1280
1281 sbus_request(dd, ra, 0x16, WRITE_SBUS_RECEIVER, 0x000c0000);
1282
1283
1284 err = run_rsa(dd, "SBus", fdet->signature);
1285 if (err)
1286 return err;
1287
1288
1289 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1290
1291 return 0;
1292}
1293
1294static int load_pcie_serdes_firmware(struct hfi1_devdata *dd,
1295 struct firmware_details *fdet)
1296{
1297 int i;
1298 const u8 ra = SBUS_MASTER_BROADCAST;
1299
1300 dd_dev_info(dd, "Downloading PCIe firmware\n");
1301
1302
1303 load_security_variables(dd, fdet);
1304
1305 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000001);
1306
1307 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000d40);
1308
1309
1310
1311
1312
1313 for (i = 0; i < fdet->firmware_len; i += 4) {
1314 sbus_request(dd, ra, 0x04, WRITE_SBUS_RECEIVER,
1315 *(u32 *)&fdet->firmware_ptr[i]);
1316 }
1317
1318 sbus_request(dd, ra, 0x01, WRITE_SBUS_RECEIVER, 0x00000140);
1319
1320 sbus_request(dd, ra, 0x05, WRITE_SBUS_RECEIVER, 0x00000000);
1321
1322
1323
1324
1325
1326 return run_rsa(dd, "PCIe serdes", fdet->signature);
1327}
1328
1329
1330
1331
1332static void set_serdes_broadcast(struct hfi1_devdata *dd, u8 bg1, u8 bg2,
1333 const u8 *addrs, int count)
1334{
1335 while (--count >= 0) {
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348 sbus_request(dd, addrs[count], 0xfd, WRITE_SBUS_RECEIVER,
1349 (u32)bg1 << 4 | (u32)bg2 << 16);
1350 }
1351}
1352
1353int acquire_hw_mutex(struct hfi1_devdata *dd)
1354{
1355 unsigned long timeout;
1356 int try = 0;
1357 u8 mask = 1 << dd->hfi1_id;
1358 u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1359
1360 if (user == mask) {
1361 dd_dev_info(dd,
1362 "Hardware mutex already acquired, mutex mask %u\n",
1363 (u32)mask);
1364 return 0;
1365 }
1366
1367retry:
1368 timeout = msecs_to_jiffies(HM_TIMEOUT) + jiffies;
1369 while (1) {
1370 write_csr(dd, ASIC_CFG_MUTEX, mask);
1371 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1372 if (user == mask)
1373 return 0;
1374 if (time_after(jiffies, timeout))
1375 break;
1376 msleep(20);
1377 }
1378
1379
1380 dd_dev_err(dd,
1381 "Unable to acquire hardware mutex, mutex mask %u, my mask %u (%s)\n",
1382 (u32)user, (u32)mask, (try == 0) ? "retrying" : "giving up");
1383
1384 if (try == 0) {
1385
1386 write_csr(dd, ASIC_CFG_MUTEX, 0);
1387 try++;
1388 goto retry;
1389 }
1390
1391 return -EBUSY;
1392}
1393
1394void release_hw_mutex(struct hfi1_devdata *dd)
1395{
1396 u8 mask = 1 << dd->hfi1_id;
1397 u8 user = (u8)read_csr(dd, ASIC_CFG_MUTEX);
1398
1399 if (user != mask)
1400 dd_dev_warn(dd,
1401 "Unable to release hardware mutex, mutex mask %u, my mask %u\n",
1402 (u32)user, (u32)mask);
1403 else
1404 write_csr(dd, ASIC_CFG_MUTEX, 0);
1405}
1406
1407
1408static inline u64 resource_mask(u32 hfi1_id, u32 resource)
1409{
1410 return ((u64)resource) << (hfi1_id ? CR_DYN_SHIFT : 0);
1411}
1412
1413static void fail_mutex_acquire_message(struct hfi1_devdata *dd,
1414 const char *func)
1415{
1416 dd_dev_err(dd,
1417 "%s: hardware mutex stuck - suggest rebooting the machine\n",
1418 func);
1419}
1420
1421
1422
1423
1424
1425
1426static int __acquire_chip_resource(struct hfi1_devdata *dd, u32 resource)
1427{
1428 u64 scratch0, all_bits, my_bit;
1429 int ret;
1430
1431 if (resource & CR_DYN_MASK) {
1432
1433 if (dd->pcidev->device == PCI_DEVICE_ID_INTEL0 &&
1434 (resource & (CR_I2C1 | CR_I2C2))) {
1435
1436 all_bits = resource_mask(0, CR_I2C1 | CR_I2C2) |
1437 resource_mask(1, CR_I2C1 | CR_I2C2);
1438 } else {
1439 all_bits = resource_mask(0, resource) |
1440 resource_mask(1, resource);
1441 }
1442 my_bit = resource_mask(dd->hfi1_id, resource);
1443 } else {
1444
1445 all_bits = resource;
1446 my_bit = resource;
1447 }
1448
1449
1450 mutex_lock(&dd->asic_data->asic_resource_mutex);
1451
1452 ret = acquire_hw_mutex(dd);
1453 if (ret) {
1454 fail_mutex_acquire_message(dd, __func__);
1455 ret = -EIO;
1456 goto done;
1457 }
1458
1459 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1460 if (scratch0 & all_bits) {
1461 ret = -EBUSY;
1462 } else {
1463 write_csr(dd, ASIC_CFG_SCRATCH, scratch0 | my_bit);
1464
1465 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1466 }
1467
1468 release_hw_mutex(dd);
1469
1470done:
1471 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1472 return ret;
1473}
1474
1475
1476
1477
1478
1479
1480
1481
1482int acquire_chip_resource(struct hfi1_devdata *dd, u32 resource, u32 mswait)
1483{
1484 unsigned long timeout;
1485 int ret;
1486
1487 timeout = jiffies + msecs_to_jiffies(mswait);
1488 while (1) {
1489 ret = __acquire_chip_resource(dd, resource);
1490 if (ret != -EBUSY)
1491 return ret;
1492
1493 if (time_after_eq(jiffies, timeout))
1494 return -EBUSY;
1495 usleep_range(80, 120);
1496 }
1497}
1498
1499
1500
1501
1502void release_chip_resource(struct hfi1_devdata *dd, u32 resource)
1503{
1504 u64 scratch0, bit;
1505
1506
1507 if (!(resource & CR_DYN_MASK)) {
1508 dd_dev_err(dd, "%s: invalid resource 0x%x\n", __func__,
1509 resource);
1510 return;
1511 }
1512 bit = resource_mask(dd->hfi1_id, resource);
1513
1514
1515 mutex_lock(&dd->asic_data->asic_resource_mutex);
1516
1517 if (acquire_hw_mutex(dd)) {
1518 fail_mutex_acquire_message(dd, __func__);
1519 goto done;
1520 }
1521
1522 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1523 if ((scratch0 & bit) != 0) {
1524 scratch0 &= ~bit;
1525 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1526
1527 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1528 } else {
1529 dd_dev_warn(dd, "%s: id %d, resource 0x%x: bit not set\n",
1530 __func__, dd->hfi1_id, resource);
1531 }
1532
1533 release_hw_mutex(dd);
1534
1535done:
1536 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1537}
1538
1539
1540
1541
1542
1543bool check_chip_resource(struct hfi1_devdata *dd, u32 resource,
1544 const char *func)
1545{
1546 u64 scratch0, bit;
1547
1548 if (resource & CR_DYN_MASK)
1549 bit = resource_mask(dd->hfi1_id, resource);
1550 else
1551 bit = resource;
1552
1553 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1554 if ((scratch0 & bit) == 0) {
1555 if (func)
1556 dd_dev_warn(dd,
1557 "%s: id %d, resource 0x%x, not acquired!\n",
1558 func, dd->hfi1_id, resource);
1559 return false;
1560 }
1561 return true;
1562}
1563
1564static void clear_chip_resources(struct hfi1_devdata *dd, const char *func)
1565{
1566 u64 scratch0;
1567
1568
1569 mutex_lock(&dd->asic_data->asic_resource_mutex);
1570
1571 if (acquire_hw_mutex(dd)) {
1572 fail_mutex_acquire_message(dd, func);
1573 goto done;
1574 }
1575
1576
1577 scratch0 = read_csr(dd, ASIC_CFG_SCRATCH);
1578 scratch0 &= ~resource_mask(dd->hfi1_id, CR_DYN_MASK);
1579 write_csr(dd, ASIC_CFG_SCRATCH, scratch0);
1580
1581 (void)read_csr(dd, ASIC_CFG_SCRATCH);
1582
1583 release_hw_mutex(dd);
1584
1585done:
1586 mutex_unlock(&dd->asic_data->asic_resource_mutex);
1587}
1588
1589void init_chip_resources(struct hfi1_devdata *dd)
1590{
1591
1592 clear_chip_resources(dd, __func__);
1593}
1594
1595void finish_chip_resources(struct hfi1_devdata *dd)
1596{
1597
1598 clear_chip_resources(dd, __func__);
1599}
1600
1601void set_sbus_fast_mode(struct hfi1_devdata *dd)
1602{
1603 write_csr(dd, ASIC_CFG_SBUS_EXECUTE,
1604 ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK);
1605}
1606
1607void clear_sbus_fast_mode(struct hfi1_devdata *dd)
1608{
1609 u64 reg, count = 0;
1610
1611 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1612 while (SBUS_COUNTER(reg, EXECUTE) !=
1613 SBUS_COUNTER(reg, RCV_DATA_VALID)) {
1614 if (count++ >= SBUS_MAX_POLL_COUNT)
1615 break;
1616 udelay(1);
1617 reg = read_csr(dd, ASIC_STS_SBUS_COUNTERS);
1618 }
1619 write_csr(dd, ASIC_CFG_SBUS_EXECUTE, 0);
1620}
1621
1622int load_firmware(struct hfi1_devdata *dd)
1623{
1624 int ret;
1625
1626 if (fw_fabric_serdes_load) {
1627 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
1628 if (ret)
1629 return ret;
1630
1631 set_sbus_fast_mode(dd);
1632
1633 set_serdes_broadcast(dd, all_fabric_serdes_broadcast,
1634 fabric_serdes_broadcast[dd->hfi1_id],
1635 fabric_serdes_addrs[dd->hfi1_id],
1636 NUM_FABRIC_SERDES);
1637 turn_off_spicos(dd, SPICO_FABRIC);
1638 do {
1639 ret = load_fabric_serdes_firmware(dd, &fw_fabric);
1640 } while (retry_firmware(dd, ret));
1641
1642 clear_sbus_fast_mode(dd);
1643 release_chip_resource(dd, CR_SBUS);
1644 if (ret)
1645 return ret;
1646 }
1647
1648 if (fw_8051_load) {
1649 do {
1650 ret = load_8051_firmware(dd, &fw_8051);
1651 } while (retry_firmware(dd, ret));
1652 if (ret)
1653 return ret;
1654 }
1655
1656 dump_fw_version(dd);
1657 return 0;
1658}
1659
1660int hfi1_firmware_init(struct hfi1_devdata *dd)
1661{
1662
1663 if (dd->icode != ICODE_RTL_SILICON) {
1664 fw_fabric_serdes_load = 0;
1665 fw_pcie_serdes_load = 0;
1666 fw_sbus_load = 0;
1667 }
1668
1669
1670 if (dd->icode == ICODE_FUNCTIONAL_SIMULATOR)
1671 fw_8051_load = 0;
1672
1673 if (!fw_8051_name) {
1674 if (dd->icode == ICODE_RTL_SILICON)
1675 fw_8051_name = DEFAULT_FW_8051_NAME_ASIC;
1676 else
1677 fw_8051_name = DEFAULT_FW_8051_NAME_FPGA;
1678 }
1679 if (!fw_fabric_serdes_name)
1680 fw_fabric_serdes_name = DEFAULT_FW_FABRIC_NAME;
1681 if (!fw_sbus_name)
1682 fw_sbus_name = DEFAULT_FW_SBUS_NAME;
1683 if (!fw_pcie_serdes_name)
1684 fw_pcie_serdes_name = DEFAULT_FW_PCIE_NAME;
1685
1686 return obtain_firmware(dd);
1687}
1688
1689
1690
1691
1692
1693
1694
1695
1696static int check_meta_version(struct hfi1_devdata *dd, u32 *system_table)
1697{
1698 u32 meta_ver, meta_ver_meta, ver_start, ver_len, mask;
1699 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1700
1701 if (!system_table)
1702 return -EINVAL;
1703
1704 meta_ver_meta =
1705 *(pcfgcache->config_tables[PLATFORM_CONFIG_SYSTEM_TABLE].table_metadata
1706 + SYSTEM_TABLE_META_VERSION);
1707
1708 mask = ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
1709 ver_start = meta_ver_meta & mask;
1710
1711 meta_ver_meta >>= METADATA_TABLE_FIELD_LEN_SHIFT;
1712
1713 mask = ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
1714 ver_len = meta_ver_meta & mask;
1715
1716 ver_start /= 8;
1717 meta_ver = *((u8 *)system_table + ver_start) & ((1 << ver_len) - 1);
1718
1719 if (meta_ver < 4) {
1720 dd_dev_info(
1721 dd, "%s:Please update platform config\n", __func__);
1722 return -EINVAL;
1723 }
1724 return 0;
1725}
1726
1727int parse_platform_config(struct hfi1_devdata *dd)
1728{
1729 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1730 struct hfi1_pportdata *ppd = dd->pport;
1731 u32 *ptr = NULL;
1732 u32 header1 = 0, header2 = 0, magic_num = 0, crc = 0, file_length = 0;
1733 u32 record_idx = 0, table_type = 0, table_length_dwords = 0;
1734 int ret = -EINVAL;
1735
1736
1737
1738
1739
1740
1741
1742 if (ppd->config_from_scratch)
1743 return 0;
1744
1745 if (!dd->platform_config.data) {
1746 dd_dev_err(dd, "%s: Missing config file\n", __func__);
1747 goto bail;
1748 }
1749 ptr = (u32 *)dd->platform_config.data;
1750
1751 magic_num = *ptr;
1752 ptr++;
1753 if (magic_num != PLATFORM_CONFIG_MAGIC_NUM) {
1754 dd_dev_err(dd, "%s: Bad config file\n", __func__);
1755 goto bail;
1756 }
1757
1758
1759 file_length = (*ptr) * 4;
1760
1761
1762
1763
1764
1765
1766 if (file_length > MAX_PLATFORM_CONFIG_FILE_SIZE) {
1767 dd_dev_info(dd,
1768 "%s:File length out of bounds, using alternative format\n",
1769 __func__);
1770 file_length = PLATFORM_CONFIG_FORMAT_4_FILE_SIZE;
1771 } else {
1772 ptr++;
1773 }
1774
1775 if (file_length > dd->platform_config.size) {
1776 dd_dev_info(dd, "%s:File claims to be larger than read size\n",
1777 __func__);
1778 goto bail;
1779 } else if (file_length < dd->platform_config.size) {
1780 dd_dev_info(dd,
1781 "%s:File claims to be smaller than read size, continuing\n",
1782 __func__);
1783 }
1784
1785
1786
1787
1788
1789
1790
1791 while (ptr < (u32 *)(dd->platform_config.data + file_length)) {
1792 header1 = *ptr;
1793 header2 = *(ptr + 1);
1794 if (header1 != ~header2) {
1795 dd_dev_err(dd, "%s: Failed validation at offset %ld\n",
1796 __func__, (ptr - (u32 *)
1797 dd->platform_config.data));
1798 goto bail;
1799 }
1800
1801 record_idx = *ptr &
1802 ((1 << PLATFORM_CONFIG_HEADER_RECORD_IDX_LEN_BITS) - 1);
1803
1804 table_length_dwords = (*ptr >>
1805 PLATFORM_CONFIG_HEADER_TABLE_LENGTH_SHIFT) &
1806 ((1 << PLATFORM_CONFIG_HEADER_TABLE_LENGTH_LEN_BITS) - 1);
1807
1808 table_type = (*ptr >> PLATFORM_CONFIG_HEADER_TABLE_TYPE_SHIFT) &
1809 ((1 << PLATFORM_CONFIG_HEADER_TABLE_TYPE_LEN_BITS) - 1);
1810
1811
1812 ptr += 2;
1813
1814 if (record_idx) {
1815
1816 switch (table_type) {
1817 case PLATFORM_CONFIG_SYSTEM_TABLE:
1818 pcfgcache->config_tables[table_type].num_table =
1819 1;
1820 ret = check_meta_version(dd, ptr);
1821 if (ret)
1822 goto bail;
1823 break;
1824 case PLATFORM_CONFIG_PORT_TABLE:
1825 pcfgcache->config_tables[table_type].num_table =
1826 2;
1827 break;
1828 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1829 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1830 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1831 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1832 pcfgcache->config_tables[table_type].num_table =
1833 table_length_dwords;
1834 break;
1835 default:
1836 dd_dev_err(dd,
1837 "%s: Unknown data table %d, offset %ld\n",
1838 __func__, table_type,
1839 (ptr - (u32 *)
1840 dd->platform_config.data));
1841 goto bail;
1842 }
1843 pcfgcache->config_tables[table_type].table = ptr;
1844 } else {
1845
1846 switch (table_type) {
1847 case PLATFORM_CONFIG_SYSTEM_TABLE:
1848 case PLATFORM_CONFIG_PORT_TABLE:
1849 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1850 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1851 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1852 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1853 break;
1854 default:
1855 dd_dev_err(dd,
1856 "%s: Unknown meta table %d, offset %ld\n",
1857 __func__, table_type,
1858 (ptr -
1859 (u32 *)dd->platform_config.data));
1860 goto bail;
1861 }
1862 pcfgcache->config_tables[table_type].table_metadata =
1863 ptr;
1864 }
1865
1866
1867 crc = crc32_le(~(u32)0, (unsigned char const *)ptr,
1868 (table_length_dwords * 4));
1869 crc ^= ~(u32)0;
1870
1871
1872 ptr += table_length_dwords;
1873 if (crc != *ptr) {
1874 dd_dev_err(dd, "%s: Failed CRC check at offset %ld\n",
1875 __func__, (ptr -
1876 (u32 *)dd->platform_config.data));
1877 ret = -EINVAL;
1878 goto bail;
1879 }
1880
1881 ptr++;
1882 }
1883
1884 pcfgcache->cache_valid = 1;
1885 return 0;
1886bail:
1887 memset(pcfgcache, 0, sizeof(struct platform_config_cache));
1888 return ret;
1889}
1890
1891static void get_integrated_platform_config_field(
1892 struct hfi1_devdata *dd,
1893 enum platform_config_table_type_encoding table_type,
1894 int field_index, u32 *data)
1895{
1896 struct hfi1_pportdata *ppd = dd->pport;
1897 u8 *cache = ppd->qsfp_info.cache;
1898 u32 tx_preset = 0;
1899
1900 switch (table_type) {
1901 case PLATFORM_CONFIG_SYSTEM_TABLE:
1902 if (field_index == SYSTEM_TABLE_QSFP_POWER_CLASS_MAX)
1903 *data = ppd->max_power_class;
1904 else if (field_index == SYSTEM_TABLE_QSFP_ATTENUATION_DEFAULT_25G)
1905 *data = ppd->default_atten;
1906 break;
1907 case PLATFORM_CONFIG_PORT_TABLE:
1908 if (field_index == PORT_TABLE_PORT_TYPE)
1909 *data = ppd->port_type;
1910 else if (field_index == PORT_TABLE_LOCAL_ATTEN_25G)
1911 *data = ppd->local_atten;
1912 else if (field_index == PORT_TABLE_REMOTE_ATTEN_25G)
1913 *data = ppd->remote_atten;
1914 break;
1915 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1916 if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR_APPLY)
1917 *data = (ppd->rx_preset & QSFP_RX_CDR_APPLY_SMASK) >>
1918 QSFP_RX_CDR_APPLY_SHIFT;
1919 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP_APPLY)
1920 *data = (ppd->rx_preset & QSFP_RX_EMP_APPLY_SMASK) >>
1921 QSFP_RX_EMP_APPLY_SHIFT;
1922 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP_APPLY)
1923 *data = (ppd->rx_preset & QSFP_RX_AMP_APPLY_SMASK) >>
1924 QSFP_RX_AMP_APPLY_SHIFT;
1925 else if (field_index == RX_PRESET_TABLE_QSFP_RX_CDR)
1926 *data = (ppd->rx_preset & QSFP_RX_CDR_SMASK) >>
1927 QSFP_RX_CDR_SHIFT;
1928 else if (field_index == RX_PRESET_TABLE_QSFP_RX_EMP)
1929 *data = (ppd->rx_preset & QSFP_RX_EMP_SMASK) >>
1930 QSFP_RX_EMP_SHIFT;
1931 else if (field_index == RX_PRESET_TABLE_QSFP_RX_AMP)
1932 *data = (ppd->rx_preset & QSFP_RX_AMP_SMASK) >>
1933 QSFP_RX_AMP_SHIFT;
1934 break;
1935 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1936 if (cache[QSFP_EQ_INFO_OFFS] & 0x4)
1937 tx_preset = ppd->tx_preset_eq;
1938 else
1939 tx_preset = ppd->tx_preset_noeq;
1940 if (field_index == TX_PRESET_TABLE_PRECUR)
1941 *data = (tx_preset & TX_PRECUR_SMASK) >>
1942 TX_PRECUR_SHIFT;
1943 else if (field_index == TX_PRESET_TABLE_ATTN)
1944 *data = (tx_preset & TX_ATTN_SMASK) >>
1945 TX_ATTN_SHIFT;
1946 else if (field_index == TX_PRESET_TABLE_POSTCUR)
1947 *data = (tx_preset & TX_POSTCUR_SMASK) >>
1948 TX_POSTCUR_SHIFT;
1949 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR_APPLY)
1950 *data = (tx_preset & QSFP_TX_CDR_APPLY_SMASK) >>
1951 QSFP_TX_CDR_APPLY_SHIFT;
1952 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ_APPLY)
1953 *data = (tx_preset & QSFP_TX_EQ_APPLY_SMASK) >>
1954 QSFP_TX_EQ_APPLY_SHIFT;
1955 else if (field_index == TX_PRESET_TABLE_QSFP_TX_CDR)
1956 *data = (tx_preset & QSFP_TX_CDR_SMASK) >>
1957 QSFP_TX_CDR_SHIFT;
1958 else if (field_index == TX_PRESET_TABLE_QSFP_TX_EQ)
1959 *data = (tx_preset & QSFP_TX_EQ_SMASK) >>
1960 QSFP_TX_EQ_SHIFT;
1961 break;
1962 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1963 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1964 default:
1965 break;
1966 }
1967}
1968
1969static int get_platform_fw_field_metadata(struct hfi1_devdata *dd, int table,
1970 int field, u32 *field_len_bits,
1971 u32 *field_start_bits)
1972{
1973 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
1974 u32 *src_ptr = NULL;
1975
1976 if (!pcfgcache->cache_valid)
1977 return -EINVAL;
1978
1979 switch (table) {
1980 case PLATFORM_CONFIG_SYSTEM_TABLE:
1981 case PLATFORM_CONFIG_PORT_TABLE:
1982 case PLATFORM_CONFIG_RX_PRESET_TABLE:
1983 case PLATFORM_CONFIG_TX_PRESET_TABLE:
1984 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
1985 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
1986 if (field && field < platform_config_table_limits[table])
1987 src_ptr =
1988 pcfgcache->config_tables[table].table_metadata + field;
1989 break;
1990 default:
1991 dd_dev_info(dd, "%s: Unknown table\n", __func__);
1992 break;
1993 }
1994
1995 if (!src_ptr)
1996 return -EINVAL;
1997
1998 if (field_start_bits)
1999 *field_start_bits = *src_ptr &
2000 ((1 << METADATA_TABLE_FIELD_START_LEN_BITS) - 1);
2001
2002 if (field_len_bits)
2003 *field_len_bits = (*src_ptr >> METADATA_TABLE_FIELD_LEN_SHIFT)
2004 & ((1 << METADATA_TABLE_FIELD_LEN_LEN_BITS) - 1);
2005
2006 return 0;
2007}
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020
2021
2022
2023
2024
2025int get_platform_config_field(struct hfi1_devdata *dd,
2026 enum platform_config_table_type_encoding
2027 table_type, int table_index, int field_index,
2028 u32 *data, u32 len)
2029{
2030 int ret = 0, wlen = 0, seek = 0;
2031 u32 field_len_bits = 0, field_start_bits = 0, *src_ptr = NULL;
2032 struct platform_config_cache *pcfgcache = &dd->pcfg_cache;
2033 struct hfi1_pportdata *ppd = dd->pport;
2034
2035 if (data)
2036 memset(data, 0, len);
2037 else
2038 return -EINVAL;
2039
2040 if (ppd->config_from_scratch) {
2041
2042
2043
2044 get_integrated_platform_config_field(dd, table_type,
2045 field_index, data);
2046 return 0;
2047 }
2048
2049 ret = get_platform_fw_field_metadata(dd, table_type, field_index,
2050 &field_len_bits,
2051 &field_start_bits);
2052 if (ret)
2053 return -EINVAL;
2054
2055
2056 len *= 8;
2057
2058
2059 switch (table_type) {
2060 case PLATFORM_CONFIG_SYSTEM_TABLE:
2061 src_ptr = pcfgcache->config_tables[table_type].table;
2062
2063 if (field_index != SYSTEM_TABLE_QSFP_POWER_CLASS_MAX) {
2064 if (len < field_len_bits)
2065 return -EINVAL;
2066
2067 seek = field_start_bits / 8;
2068 wlen = field_len_bits / 8;
2069
2070 src_ptr = (u32 *)((u8 *)src_ptr + seek);
2071
2072
2073
2074
2075
2076 memcpy(data, src_ptr, wlen);
2077 return 0;
2078 }
2079 break;
2080 case PLATFORM_CONFIG_PORT_TABLE:
2081
2082 src_ptr = dd->hfi1_id ?
2083 pcfgcache->config_tables[table_type].table + 4 :
2084 pcfgcache->config_tables[table_type].table;
2085 break;
2086 case PLATFORM_CONFIG_RX_PRESET_TABLE:
2087 case PLATFORM_CONFIG_TX_PRESET_TABLE:
2088 case PLATFORM_CONFIG_QSFP_ATTEN_TABLE:
2089 case PLATFORM_CONFIG_VARIABLE_SETTINGS_TABLE:
2090 src_ptr = pcfgcache->config_tables[table_type].table;
2091
2092 if (table_index <
2093 pcfgcache->config_tables[table_type].num_table)
2094 src_ptr += table_index;
2095 else
2096 src_ptr = NULL;
2097 break;
2098 default:
2099 dd_dev_info(dd, "%s: Unknown table\n", __func__);
2100 break;
2101 }
2102
2103 if (!src_ptr || len < field_len_bits)
2104 return -EINVAL;
2105
2106 src_ptr += (field_start_bits / 32);
2107 *data = (*src_ptr >> (field_start_bits % 32)) &
2108 ((1 << field_len_bits) - 1);
2109
2110 return 0;
2111}
2112
2113
2114
2115
2116
2117
2118
2119int load_pcie_firmware(struct hfi1_devdata *dd)
2120{
2121 int ret = 0;
2122
2123
2124 set_sbus_fast_mode(dd);
2125
2126 if (fw_sbus_load) {
2127 turn_off_spicos(dd, SPICO_SBUS);
2128 do {
2129 ret = load_sbus_firmware(dd, &fw_sbus);
2130 } while (retry_firmware(dd, ret));
2131 if (ret)
2132 goto done;
2133 }
2134
2135 if (fw_pcie_serdes_load) {
2136 dd_dev_info(dd, "Setting PCIe SerDes broadcast\n");
2137 set_serdes_broadcast(dd, all_pcie_serdes_broadcast,
2138 pcie_serdes_broadcast[dd->hfi1_id],
2139 pcie_serdes_addrs[dd->hfi1_id],
2140 NUM_PCIE_SERDES);
2141 do {
2142 ret = load_pcie_serdes_firmware(dd, &fw_pcie);
2143 } while (retry_firmware(dd, ret));
2144 if (ret)
2145 goto done;
2146 }
2147
2148done:
2149 clear_sbus_fast_mode(dd);
2150
2151 return ret;
2152}
2153
2154
2155
2156
2157void read_guid(struct hfi1_devdata *dd)
2158{
2159
2160 write_csr(dd, CCE_DC_CTRL, 0);
2161 (void)read_csr(dd, CCE_DC_CTRL);
2162
2163 dd->base_guid = read_csr(dd, DC_DC8051_CFG_LOCAL_GUID);
2164 dd_dev_info(dd, "GUID %llx",
2165 (unsigned long long)dd->base_guid);
2166}
2167
2168
2169static void dump_fw_version(struct hfi1_devdata *dd)
2170{
2171 u32 pcie_vers[NUM_PCIE_SERDES];
2172 u32 fabric_vers[NUM_FABRIC_SERDES];
2173 u32 sbus_vers;
2174 int i;
2175 int all_same;
2176 int ret;
2177 u8 rcv_addr;
2178
2179 ret = acquire_chip_resource(dd, CR_SBUS, SBUS_TIMEOUT);
2180 if (ret) {
2181 dd_dev_err(dd, "Unable to acquire SBus to read firmware versions\n");
2182 return;
2183 }
2184
2185
2186 set_sbus_fast_mode(dd);
2187
2188
2189 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x02, WRITE_SBUS_RECEIVER, 0);
2190 sbus_request(dd, SBUS_MASTER_BROADCAST, 0x07, WRITE_SBUS_RECEIVER, 0x1);
2191
2192 usleep_range(10000, 11000);
2193 sbus_vers = sbus_read(dd, SBUS_MASTER_BROADCAST, 0x08, 0x1);
2194 dd_dev_info(dd, "SBus Master firmware version 0x%08x\n", sbus_vers);
2195
2196
2197 all_same = 1;
2198 pcie_vers[0] = 0;
2199 for (i = 0; i < NUM_PCIE_SERDES; i++) {
2200 rcv_addr = pcie_serdes_addrs[dd->hfi1_id][i];
2201 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0);
2202
2203 usleep_range(10000, 11000);
2204 pcie_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0);
2205 if (i > 0 && pcie_vers[0] != pcie_vers[i])
2206 all_same = 0;
2207 }
2208
2209 if (all_same) {
2210 dd_dev_info(dd, "PCIe SerDes firmware version 0x%x\n",
2211 pcie_vers[0]);
2212 } else {
2213 dd_dev_warn(dd, "PCIe SerDes do not have the same firmware version\n");
2214 for (i = 0; i < NUM_PCIE_SERDES; i++) {
2215 dd_dev_info(dd,
2216 "PCIe SerDes lane %d firmware version 0x%x\n",
2217 i, pcie_vers[i]);
2218 }
2219 }
2220
2221
2222 all_same = 1;
2223 fabric_vers[0] = 0;
2224 for (i = 0; i < NUM_FABRIC_SERDES; i++) {
2225 rcv_addr = fabric_serdes_addrs[dd->hfi1_id][i];
2226 sbus_request(dd, rcv_addr, 0x03, WRITE_SBUS_RECEIVER, 0);
2227
2228 usleep_range(10000, 11000);
2229 fabric_vers[i] = sbus_read(dd, rcv_addr, 0x04, 0x0);
2230 if (i > 0 && fabric_vers[0] != fabric_vers[i])
2231 all_same = 0;
2232 }
2233
2234 if (all_same) {
2235 dd_dev_info(dd, "Fabric SerDes firmware version 0x%x\n",
2236 fabric_vers[0]);
2237 } else {
2238 dd_dev_warn(dd, "Fabric SerDes do not have the same firmware version\n");
2239 for (i = 0; i < NUM_FABRIC_SERDES; i++) {
2240 dd_dev_info(dd,
2241 "Fabric SerDes lane %d firmware version 0x%x\n",
2242 i, fabric_vers[i]);
2243 }
2244 }
2245
2246 clear_sbus_fast_mode(dd);
2247 release_chip_resource(dd, CR_SBUS);
2248}
2249