1
2
3#ifndef IRDMA_MAIN_H
4#define IRDMA_MAIN_H
5
6#include <linux/ip.h>
7#include <linux/tcp.h>
8#include <linux/if_vlan.h>
9#include <net/addrconf.h>
10#include <net/netevent.h>
11#include <net/tcp.h>
12#include <net/ip6_route.h>
13#include <net/flow.h>
14#include <net/secure_seq.h>
15#include <linux/netdevice.h>
16#include <linux/etherdevice.h>
17#include <linux/inetdevice.h>
18#include <linux/spinlock.h>
19#include <linux/kernel.h>
20#include <linux/delay.h>
21#include <linux/pci.h>
22#include <linux/dma-mapping.h>
23#include <linux/workqueue.h>
24#include <linux/slab.h>
25#include <linux/io.h>
26#include <linux/crc32c.h>
27#include <linux/kthread.h>
28#ifndef CONFIG_64BIT
29#include <linux/io-64-nonatomic-lo-hi.h>
30#endif
31#include <linux/auxiliary_bus.h>
32#include <linux/net/intel/iidc.h>
33#include <crypto/hash.h>
34#include <rdma/ib_smi.h>
35#include <rdma/ib_verbs.h>
36#include <rdma/ib_pack.h>
37#include <rdma/rdma_cm.h>
38#include <rdma/iw_cm.h>
39#include <rdma/ib_user_verbs.h>
40#include <rdma/ib_umem.h>
41#include <rdma/ib_cache.h>
42#include <rdma/uverbs_ioctl.h>
43#include "status.h"
44#include "osdep.h"
45#include "defs.h"
46#include "hmc.h"
47#include "type.h"
48#include "ws.h"
49#include "protos.h"
50#include "pble.h"
51#include "cm.h"
52#include <rdma/irdma-abi.h>
53#include "verbs.h"
54#include "user.h"
55#include "puda.h"
56
57extern struct auxiliary_driver i40iw_auxiliary_drv;
58
59#define IRDMA_FW_VER_DEFAULT 2
60#define IRDMA_HW_VER 2
61
62#define IRDMA_ARP_ADD 1
63#define IRDMA_ARP_DELETE 2
64#define IRDMA_ARP_RESOLVE 3
65
66#define IRDMA_MACIP_ADD 1
67#define IRDMA_MACIP_DELETE 2
68
69#define IW_CCQ_SIZE (IRDMA_CQP_SW_SQSIZE_2048 + 1)
70#define IW_CEQ_SIZE 2048
71#define IW_AEQ_SIZE 2048
72
73#define RX_BUF_SIZE (1536 + 8)
74#define IW_REG0_SIZE (4 * 1024)
75#define IW_TX_TIMEOUT (6 * HZ)
76#define IW_FIRST_QPN 1
77
78#define IW_SW_CONTEXT_ALIGN 1024
79
80#define MAX_DPC_ITERATIONS 128
81
82#define IRDMA_EVENT_TIMEOUT 50000
83#define IRDMA_VCHNL_EVENT_TIMEOUT 100000
84#define IRDMA_RST_TIMEOUT_HZ 4
85
86#define IRDMA_NO_QSET 0xffff
87
88#define IW_CFG_FPM_QP_COUNT 32768
89#define IRDMA_MAX_PAGES_PER_FMR 512
90#define IRDMA_MIN_PAGES_PER_FMR 1
91#define IRDMA_CQP_COMPL_RQ_WQE_FLUSHED 2
92#define IRDMA_CQP_COMPL_SQ_WQE_FLUSHED 3
93
94#define IRDMA_Q_TYPE_PE_AEQ 0x80
95#define IRDMA_Q_INVALID_IDX 0xffff
96#define IRDMA_REM_ENDPOINT_TRK_QPID 3
97
98#define IRDMA_DRV_OPT_ENA_MPA_VER_0 0x00000001
99#define IRDMA_DRV_OPT_DISABLE_MPA_CRC 0x00000002
100#define IRDMA_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
101#define IRDMA_DRV_OPT_DISABLE_INTF 0x00000008
102#define IRDMA_DRV_OPT_ENA_MSI 0x00000010
103#define IRDMA_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
104#define IRDMA_DRV_OPT_NO_INLINE_DATA 0x00000080
105#define IRDMA_DRV_OPT_DISABLE_INT_MOD 0x00000100
106#define IRDMA_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
107#define IRDMA_DRV_OPT_ENA_PAU 0x00000400
108#define IRDMA_DRV_OPT_MCAST_LOGPORT_MAP 0x00000800
109
110#define IW_HMC_OBJ_TYPE_NUM ARRAY_SIZE(iw_hmc_obj_types)
111#define IRDMA_ROCE_CWND_DEFAULT 0x400
112#define IRDMA_ROCE_ACKCREDS_DEFAULT 0x1E
113
114#define IRDMA_FLUSH_SQ BIT(0)
115#define IRDMA_FLUSH_RQ BIT(1)
116#define IRDMA_REFLUSH BIT(2)
117#define IRDMA_FLUSH_WAIT BIT(3)
118
119enum init_completion_state {
120 INVALID_STATE = 0,
121 INITIAL_STATE,
122 CQP_CREATED,
123 HMC_OBJS_CREATED,
124 HW_RSRC_INITIALIZED,
125 CCQ_CREATED,
126 CEQ0_CREATED,
127 ILQ_CREATED,
128 IEQ_CREATED,
129 CEQS_CREATED,
130 PBLE_CHUNK_MEM,
131 AEQ_CREATED,
132 IP_ADDR_REGISTERED,
133};
134
135struct irdma_rsrc_limits {
136 u32 qplimit;
137 u32 mrlimit;
138 u32 cqlimit;
139};
140
141struct irdma_cqp_err_info {
142 u16 maj;
143 u16 min;
144 const char *desc;
145};
146
147struct irdma_cqp_compl_info {
148 u32 op_ret_val;
149 u16 maj_err_code;
150 u16 min_err_code;
151 bool error;
152 u8 op_code;
153};
154
155struct irdma_cqp_request {
156 struct cqp_cmds_info info;
157 wait_queue_head_t waitq;
158 struct list_head list;
159 refcount_t refcnt;
160 void (*callback_fcn)(struct irdma_cqp_request *cqp_request);
161 void *param;
162 struct irdma_cqp_compl_info compl_info;
163 bool waiting:1;
164 bool request_done:1;
165 bool dynamic:1;
166};
167
168struct irdma_cqp {
169 struct irdma_sc_cqp sc_cqp;
170 spinlock_t req_lock;
171 spinlock_t compl_lock;
172 wait_queue_head_t waitq;
173 wait_queue_head_t remove_wq;
174 struct irdma_dma_mem sq;
175 struct irdma_dma_mem host_ctx;
176 u64 *scratch_array;
177 struct irdma_cqp_request *cqp_requests;
178 struct list_head cqp_avail_reqs;
179 struct list_head cqp_pending_reqs;
180};
181
182struct irdma_ccq {
183 struct irdma_sc_cq sc_cq;
184 struct irdma_dma_mem mem_cq;
185 struct irdma_dma_mem shadow_area;
186};
187
188struct irdma_ceq {
189 struct irdma_sc_ceq sc_ceq;
190 struct irdma_dma_mem mem;
191 u32 irq;
192 u32 msix_idx;
193 struct irdma_pci_f *rf;
194 struct tasklet_struct dpc_tasklet;
195 spinlock_t ce_lock;
196};
197
198struct irdma_aeq {
199 struct irdma_sc_aeq sc_aeq;
200 struct irdma_dma_mem mem;
201 struct irdma_pble_alloc palloc;
202 bool virtual_map;
203};
204
205struct irdma_arp_entry {
206 u32 ip_addr[4];
207 u8 mac_addr[ETH_ALEN];
208};
209
210struct irdma_msix_vector {
211 u32 idx;
212 u32 irq;
213 u32 cpu_affinity;
214 u32 ceq_id;
215 cpumask_t mask;
216};
217
218struct irdma_mc_table_info {
219 u32 mgn;
220 u32 dest_ip[4];
221 bool lan_fwd:1;
222 bool ipv4_valid:1;
223};
224
225struct mc_table_list {
226 struct list_head list;
227 struct irdma_mc_table_info mc_info;
228 struct irdma_mcast_grp_info mc_grp_ctx;
229};
230
231struct irdma_qv_info {
232 u32 v_idx;
233 u16 ceq_idx;
234 u16 aeq_idx;
235 u8 itr_idx;
236};
237
238struct irdma_qvlist_info {
239 u32 num_vectors;
240 struct irdma_qv_info qv_info[1];
241};
242
243struct irdma_gen_ops {
244 void (*request_reset)(struct irdma_pci_f *rf);
245 enum irdma_status_code (*register_qset)(struct irdma_sc_vsi *vsi,
246 struct irdma_ws_node *tc_node);
247 void (*unregister_qset)(struct irdma_sc_vsi *vsi,
248 struct irdma_ws_node *tc_node);
249};
250
251struct irdma_pci_f {
252 bool reset:1;
253 bool rsrc_created:1;
254 bool msix_shared:1;
255 u8 rsrc_profile;
256 u8 *hmc_info_mem;
257 u8 *mem_rsrc;
258 u8 rdma_ver;
259 u8 rst_to;
260 enum irdma_protocol_used protocol_used;
261 u32 sd_type;
262 u32 msix_count;
263 u32 max_mr;
264 u32 max_qp;
265 u32 max_cq;
266 u32 max_ah;
267 u32 next_ah;
268 u32 max_mcg;
269 u32 next_mcg;
270 u32 max_pd;
271 u32 next_qp;
272 u32 next_cq;
273 u32 next_pd;
274 u32 max_mr_size;
275 u32 max_cqe;
276 u32 mr_stagmask;
277 u32 used_pds;
278 u32 used_cqs;
279 u32 used_mrs;
280 u32 used_qps;
281 u32 arp_table_size;
282 u32 next_arp_index;
283 u32 ceqs_count;
284 u32 next_ws_node_id;
285 u32 max_ws_node_id;
286 u32 limits_sel;
287 unsigned long *allocated_ws_nodes;
288 unsigned long *allocated_qps;
289 unsigned long *allocated_cqs;
290 unsigned long *allocated_mrs;
291 unsigned long *allocated_pds;
292 unsigned long *allocated_mcgs;
293 unsigned long *allocated_ahs;
294 unsigned long *allocated_arps;
295 enum init_completion_state init_state;
296 struct irdma_sc_dev sc_dev;
297 struct pci_dev *pcidev;
298 void *cdev;
299 struct irdma_hw hw;
300 struct irdma_cqp cqp;
301 struct irdma_ccq ccq;
302 struct irdma_aeq aeq;
303 struct irdma_ceq *ceqlist;
304 struct irdma_hmc_pble_rsrc *pble_rsrc;
305 struct irdma_arp_entry *arp_table;
306 spinlock_t arp_lock;
307 spinlock_t rsrc_lock;
308 spinlock_t qptable_lock;
309 struct irdma_qp **qp_table;
310 spinlock_t qh_list_lock;
311 struct mc_table_list mc_qht_list;
312 struct irdma_msix_vector *iw_msixtbl;
313 struct irdma_qvlist_info *iw_qvlist;
314 struct tasklet_struct dpc_tasklet;
315 struct msix_entry *msix_entries;
316 struct irdma_dma_mem obj_mem;
317 struct irdma_dma_mem obj_next;
318 atomic_t vchnl_msgs;
319 wait_queue_head_t vchnl_waitq;
320 struct workqueue_struct *cqp_cmpl_wq;
321 struct work_struct cqp_cmpl_work;
322 struct irdma_sc_vsi default_vsi;
323 void *back_fcn;
324 struct irdma_gen_ops gen_ops;
325 struct irdma_device *iwdev;
326};
327
328struct irdma_device {
329 struct ib_device ibdev;
330 struct irdma_pci_f *rf;
331 struct net_device *netdev;
332 struct workqueue_struct *cleanup_wq;
333 struct irdma_sc_vsi vsi;
334 struct irdma_cm_core cm_core;
335 u32 roce_cwnd;
336 u32 roce_ackcreds;
337 u32 vendor_id;
338 u32 vendor_part_id;
339 u32 device_cap_flags;
340 u32 push_mode;
341 u32 rcv_wnd;
342 u16 mac_ip_table_idx;
343 u16 vsi_num;
344 u8 rcv_wscale;
345 u8 iw_status;
346 bool roce_mode:1;
347 bool roce_dcqcn_en:1;
348 bool dcb:1;
349 bool iw_ooo:1;
350 enum init_completion_state init_state;
351
352 wait_queue_head_t suspend_wq;
353};
354
355static inline struct irdma_device *to_iwdev(struct ib_device *ibdev)
356{
357 return container_of(ibdev, struct irdma_device, ibdev);
358}
359
360static inline struct irdma_ucontext *to_ucontext(struct ib_ucontext *ibucontext)
361{
362 return container_of(ibucontext, struct irdma_ucontext, ibucontext);
363}
364
365static inline struct irdma_user_mmap_entry *
366to_irdma_mmap_entry(struct rdma_user_mmap_entry *rdma_entry)
367{
368 return container_of(rdma_entry, struct irdma_user_mmap_entry,
369 rdma_entry);
370}
371
372static inline struct irdma_pd *to_iwpd(struct ib_pd *ibpd)
373{
374 return container_of(ibpd, struct irdma_pd, ibpd);
375}
376
377static inline struct irdma_ah *to_iwah(struct ib_ah *ibah)
378{
379 return container_of(ibah, struct irdma_ah, ibah);
380}
381
382static inline struct irdma_mr *to_iwmr(struct ib_mr *ibmr)
383{
384 return container_of(ibmr, struct irdma_mr, ibmr);
385}
386
387static inline struct irdma_mr *to_iwmw(struct ib_mw *ibmw)
388{
389 return container_of(ibmw, struct irdma_mr, ibmw);
390}
391
392static inline struct irdma_cq *to_iwcq(struct ib_cq *ibcq)
393{
394 return container_of(ibcq, struct irdma_cq, ibcq);
395}
396
397static inline struct irdma_qp *to_iwqp(struct ib_qp *ibqp)
398{
399 return container_of(ibqp, struct irdma_qp, ibqp);
400}
401
402static inline struct irdma_pci_f *dev_to_rf(struct irdma_sc_dev *dev)
403{
404 return container_of(dev, struct irdma_pci_f, sc_dev);
405}
406
407
408
409
410
411
412
413
414
415static inline int irdma_alloc_rsrc(struct irdma_pci_f *rf,
416 unsigned long *rsrc_array, u32 max_rsrc,
417 u32 *req_rsrc_num, u32 *next)
418{
419 u32 rsrc_num;
420 unsigned long flags;
421
422 spin_lock_irqsave(&rf->rsrc_lock, flags);
423 rsrc_num = find_next_zero_bit(rsrc_array, max_rsrc, *next);
424 if (rsrc_num >= max_rsrc) {
425 rsrc_num = find_first_zero_bit(rsrc_array, max_rsrc);
426 if (rsrc_num >= max_rsrc) {
427 spin_unlock_irqrestore(&rf->rsrc_lock, flags);
428 ibdev_dbg(&rf->iwdev->ibdev,
429 "ERR: resource [%d] allocation failed\n",
430 rsrc_num);
431 return -EOVERFLOW;
432 }
433 }
434 __set_bit(rsrc_num, rsrc_array);
435 *next = rsrc_num + 1;
436 if (*next == max_rsrc)
437 *next = 0;
438 *req_rsrc_num = rsrc_num;
439 spin_unlock_irqrestore(&rf->rsrc_lock, flags);
440
441 return 0;
442}
443
444
445
446
447
448
449
450static inline void irdma_free_rsrc(struct irdma_pci_f *rf,
451 unsigned long *rsrc_array, u32 rsrc_num)
452{
453 unsigned long flags;
454
455 spin_lock_irqsave(&rf->rsrc_lock, flags);
456 __clear_bit(rsrc_num, rsrc_array);
457 spin_unlock_irqrestore(&rf->rsrc_lock, flags);
458}
459
460enum irdma_status_code irdma_ctrl_init_hw(struct irdma_pci_f *rf);
461void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf);
462enum irdma_status_code irdma_rt_init_hw(struct irdma_device *iwdev,
463 struct irdma_l2params *l2params);
464void irdma_rt_deinit_hw(struct irdma_device *iwdev);
465void irdma_qp_add_ref(struct ib_qp *ibqp);
466void irdma_qp_rem_ref(struct ib_qp *ibqp);
467void irdma_free_lsmm_rsrc(struct irdma_qp *iwqp);
468struct ib_qp *irdma_get_qp(struct ib_device *ibdev, int qpn);
469void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask);
470void irdma_manage_arp_cache(struct irdma_pci_f *rf, unsigned char *mac_addr,
471 u32 *ip_addr, bool ipv4, u32 action);
472struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port);
473void irdma_del_apbvt(struct irdma_device *iwdev,
474 struct irdma_apbvt_entry *entry);
475struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp,
476 bool wait);
477void irdma_free_cqp_request(struct irdma_cqp *cqp,
478 struct irdma_cqp_request *cqp_request);
479void irdma_put_cqp_request(struct irdma_cqp *cqp,
480 struct irdma_cqp_request *cqp_request);
481int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx);
482int irdma_add_local_mac_entry(struct irdma_pci_f *rf, u8 *mac_addr, u16 idx);
483void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx);
484
485u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf);
486void irdma_port_ibevent(struct irdma_device *iwdev);
487void irdma_cm_disconn(struct irdma_qp *qp);
488
489bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd,
490 u16 maj_err_code, u16 min_err_code);
491enum irdma_status_code
492irdma_handle_cqp_op(struct irdma_pci_f *rf,
493 struct irdma_cqp_request *cqp_request);
494
495int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
496 struct ib_udata *udata);
497int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr,
498 int attr_mask, struct ib_udata *udata);
499void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq);
500
501void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf);
502enum irdma_status_code irdma_hw_modify_qp(struct irdma_device *iwdev,
503 struct irdma_qp *iwqp,
504 struct irdma_modify_qp_info *info,
505 bool wait);
506enum irdma_status_code irdma_qp_suspend_resume(struct irdma_sc_qp *qp,
507 bool suspend);
508enum irdma_status_code
509irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo,
510 enum irdma_quad_entry_type etype,
511 enum irdma_quad_hash_manage_type mtype, void *cmnode,
512 bool wait);
513void irdma_receive_ilq(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *rbuf);
514void irdma_free_sqbuf(struct irdma_sc_vsi *vsi, void *bufp);
515void irdma_free_qp_rsrc(struct irdma_qp *iwqp);
516enum irdma_status_code irdma_setup_cm_core(struct irdma_device *iwdev, u8 ver);
517void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core);
518void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term,
519 u8 term_len);
520int irdma_send_syn(struct irdma_cm_node *cm_node, u32 sendack);
521int irdma_send_reset(struct irdma_cm_node *cm_node);
522struct irdma_cm_node *irdma_find_node(struct irdma_cm_core *cm_core,
523 u16 rem_port, u32 *rem_addr, u16 loc_port,
524 u32 *loc_addr, u16 vlan_id);
525enum irdma_status_code irdma_hw_flush_wqes(struct irdma_pci_f *rf,
526 struct irdma_sc_qp *qp,
527 struct irdma_qp_flush_info *info,
528 bool wait);
529void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp,
530 struct irdma_gen_ae_info *info, bool wait);
531void irdma_copy_ip_ntohl(u32 *dst, __be32 *src);
532void irdma_copy_ip_htonl(__be32 *dst, u32 *src);
533u16 irdma_get_vlan_ipv4(u32 *addr);
534struct net_device *irdma_netdev_vlan_ipv6(u32 *addr, u16 *vlan_id, u8 *mac);
535struct ib_mr *irdma_reg_phys_mr(struct ib_pd *ib_pd, u64 addr, u64 size,
536 int acc, u64 *iova_start);
537int irdma_upload_qp_context(struct irdma_qp *iwqp, bool freeze, bool raw);
538void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq);
539int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd,
540 bool wait,
541 void (*callback_fcn)(struct irdma_cqp_request *cqp_request),
542 void *cb_param);
543void irdma_gsi_ud_qp_ah_cb(struct irdma_cqp_request *cqp_request);
544int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event,
545 void *ptr);
546int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event,
547 void *ptr);
548int irdma_net_event(struct notifier_block *notifier, unsigned long event,
549 void *ptr);
550int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event,
551 void *ptr);
552void irdma_add_ip(struct irdma_device *iwdev);
553void cqp_compl_worker(struct work_struct *work);
554#endif
555
