1#ifndef _QIB_KERNEL_H
2#define _QIB_KERNEL_H
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42#include <linux/interrupt.h>
43#include <linux/pci.h>
44#include <linux/dma-mapping.h>
45#include <linux/mutex.h>
46#include <linux/list.h>
47#include <linux/scatterlist.h>
48#include <linux/slab.h>
49#include <linux/io.h>
50#include <linux/fs.h>
51#include <linux/completion.h>
52#include <linux/kref.h>
53#include <linux/sched.h>
54#include <linux/kthread.h>
55#include <linux/xarray.h>
56#include <rdma/ib_hdrs.h>
57#include <rdma/rdma_vt.h>
58
59#include "qib_common.h"
60#include "qib_verbs.h"
61
62
63#define QIB_CHIP_VERS_MAJ 2U
64
65
66#define QIB_CHIP_VERS_MIN 0U
67
68
69#define QIB_OUI 0x001175
70#define QIB_OUI_LSB 40
71
72
73
74
75
76
77
78
79
80struct qlogic_ib_stats {
81 __u64 sps_ints;
82 __u64 sps_errints;
83 __u64 sps_txerrs;
84 __u64 sps_rcverrs;
85 __u64 sps_hwerrs;
86 __u64 sps_nopiobufs;
87 __u64 sps_ctxts;
88 __u64 sps_lenerrs;
89 __u64 sps_buffull;
90 __u64 sps_hdrfull;
91};
92
93extern struct qlogic_ib_stats qib_stats;
94extern const struct pci_error_handlers qib_pci_err_handler;
95
96#define QIB_CHIP_SWVERSION QIB_CHIP_VERS_MAJ
97
98
99
100
101
102
103#define QIB_TRAFFIC_ACTIVE_THRESHOLD (2000)
104
105
106
107
108
109#ifdef CONFIG_DEBUG_FS
110struct qib_opcode_stats_perctx;
111#endif
112
113struct qib_ctxtdata {
114 void **rcvegrbuf;
115 dma_addr_t *rcvegrbuf_phys;
116
117 void *rcvhdrq;
118
119 void *rcvhdrtail_kvaddr;
120
121
122
123
124 void *tid_pg_list;
125
126
127
128
129
130 unsigned long *user_event_mask;
131
132 wait_queue_head_t wait;
133
134
135
136
137 dma_addr_t rcvegr_phys;
138
139 dma_addr_t rcvhdrq_phys;
140 dma_addr_t rcvhdrqtailaddr_phys;
141
142
143
144
145
146 int cnt;
147
148
149
150
151
152 unsigned ctxt;
153
154 int node_id;
155
156 u16 subctxt_cnt;
157
158 u16 subctxt_id;
159
160 u16 rcvegrcnt;
161
162 u16 rcvegr_tid_base;
163
164 u32 piocnt;
165
166 u32 pio_base;
167
168 u32 piobufs;
169
170 u32 rcvegrbuf_chunks;
171
172 u16 rcvegrbufs_perchunk;
173
174 u16 rcvegrbufs_perchunk_shift;
175
176 size_t rcvegrbuf_size;
177
178 size_t rcvhdrq_size;
179
180 unsigned long flag;
181
182 u32 tidcursor;
183
184 u32 rcvwait_to;
185
186 u32 piowait_to;
187
188 u32 rcvnowait;
189
190 u32 pionowait;
191
192 u32 urgent;
193
194 u32 urgent_poll;
195
196 pid_t pid;
197 pid_t subpid[QLOGIC_IB_MAX_SUBCTXT];
198
199 char comm[16];
200
201 u16 pkeys[4];
202
203 struct qib_devdata *dd;
204
205 struct qib_pportdata *ppd;
206
207 void *subctxt_uregbase;
208
209 void *subctxt_rcvegrbuf;
210
211 void *subctxt_rcvhdr_base;
212
213 u32 userversion;
214
215 u32 active_slaves;
216
217 u16 poll_type;
218
219 u8 seq_cnt;
220 u8 redirect_seq_cnt;
221
222 u32 head;
223
224 struct list_head qp_wait_list;
225#ifdef CONFIG_DEBUG_FS
226
227 struct qib_opcode_stats_perctx *opstats;
228#endif
229};
230
231struct rvt_sge_state;
232
233struct qib_sdma_txreq {
234 int flags;
235 int sg_count;
236 dma_addr_t addr;
237 void (*callback)(struct qib_sdma_txreq *, int);
238 u16 start_idx;
239 u16 next_descq_idx;
240 struct list_head list;
241};
242
243struct qib_sdma_desc {
244 __le64 qw[2];
245};
246
247struct qib_verbs_txreq {
248 struct qib_sdma_txreq txreq;
249 struct rvt_qp *qp;
250 struct rvt_swqe *wqe;
251 u32 dwords;
252 u16 hdr_dwords;
253 u16 hdr_inx;
254 struct qib_pio_header *align_buf;
255 struct rvt_mregion *mr;
256 struct rvt_sge_state *ss;
257};
258
259#define QIB_SDMA_TXREQ_F_USELARGEBUF 0x1
260#define QIB_SDMA_TXREQ_F_HEADTOHOST 0x2
261#define QIB_SDMA_TXREQ_F_INTREQ 0x4
262#define QIB_SDMA_TXREQ_F_FREEBUF 0x8
263#define QIB_SDMA_TXREQ_F_FREEDESC 0x10
264
265#define QIB_SDMA_TXREQ_S_OK 0
266#define QIB_SDMA_TXREQ_S_SENDERROR 1
267#define QIB_SDMA_TXREQ_S_ABORTED 2
268#define QIB_SDMA_TXREQ_S_SHUTDOWN 3
269
270
271
272
273
274
275#define QIB_IB_CFG_LIDLMC 0
276#define QIB_IB_CFG_LWID_ENB 2
277#define QIB_IB_CFG_LWID 3
278#define QIB_IB_CFG_SPD_ENB 4
279#define QIB_IB_CFG_SPD 5
280#define QIB_IB_CFG_RXPOL_ENB 6
281#define QIB_IB_CFG_LREV_ENB 7
282#define QIB_IB_CFG_LINKLATENCY 8
283#define QIB_IB_CFG_HRTBT 9
284#define QIB_IB_CFG_OP_VLS 10
285#define QIB_IB_CFG_VL_HIGH_CAP 11
286#define QIB_IB_CFG_VL_LOW_CAP 12
287#define QIB_IB_CFG_OVERRUN_THRESH 13
288#define QIB_IB_CFG_PHYERR_THRESH 14
289#define QIB_IB_CFG_LINKDEFAULT 15
290#define QIB_IB_CFG_PKEYS 16
291#define QIB_IB_CFG_MTU 17
292#define QIB_IB_CFG_LSTATE 18
293#define QIB_IB_CFG_VL_HIGH_LIMIT 19
294#define QIB_IB_CFG_PMA_TICKS 20
295#define QIB_IB_CFG_PORT 21
296
297
298
299
300
301
302#define IB_LINKCMD_DOWN (0 << 16)
303#define IB_LINKCMD_ARMED (1 << 16)
304#define IB_LINKCMD_ACTIVE (2 << 16)
305#define IB_LINKINITCMD_NOP 0
306#define IB_LINKINITCMD_POLL 1
307#define IB_LINKINITCMD_SLEEP 2
308#define IB_LINKINITCMD_DISABLE 3
309
310
311
312
313#define QIB_IB_LINKDOWN 0
314#define QIB_IB_LINKARM 1
315#define QIB_IB_LINKACTIVE 2
316#define QIB_IB_LINKDOWN_ONLY 3
317#define QIB_IB_LINKDOWN_SLEEP 4
318#define QIB_IB_LINKDOWN_DISABLE 5
319
320
321
322
323
324
325
326
327#define QIB_IB_SDR 1
328#define QIB_IB_DDR 2
329#define QIB_IB_QDR 4
330
331#define QIB_DEFAULT_MTU 4096
332
333
334#define QIB_MAX_IB_PORTS 2
335
336
337
338
339#define QIB_IB_TBL_VL_HIGH_ARB 1
340#define QIB_IB_TBL_VL_LOW_ARB 2
341
342
343
344
345
346
347#define QIB_RCVCTRL_TAILUPD_ENB 0x01
348#define QIB_RCVCTRL_TAILUPD_DIS 0x02
349#define QIB_RCVCTRL_CTXT_ENB 0x04
350#define QIB_RCVCTRL_CTXT_DIS 0x08
351#define QIB_RCVCTRL_INTRAVAIL_ENB 0x10
352#define QIB_RCVCTRL_INTRAVAIL_DIS 0x20
353#define QIB_RCVCTRL_PKEY_ENB 0x40
354#define QIB_RCVCTRL_PKEY_DIS 0x80
355#define QIB_RCVCTRL_BP_ENB 0x0100
356#define QIB_RCVCTRL_BP_DIS 0x0200
357#define QIB_RCVCTRL_TIDFLOW_ENB 0x0400
358#define QIB_RCVCTRL_TIDFLOW_DIS 0x0800
359
360
361
362
363
364
365
366
367#define QIB_SENDCTRL_DISARM (0x1000)
368#define QIB_SENDCTRL_DISARM_BUF(bufn) ((bufn) | QIB_SENDCTRL_DISARM)
369
370#define QIB_SENDCTRL_AVAIL_DIS (0x4000)
371#define QIB_SENDCTRL_AVAIL_ENB (0x8000)
372#define QIB_SENDCTRL_AVAIL_BLIP (0x10000)
373#define QIB_SENDCTRL_SEND_DIS (0x20000)
374#define QIB_SENDCTRL_SEND_ENB (0x40000)
375#define QIB_SENDCTRL_FLUSH (0x80000)
376#define QIB_SENDCTRL_CLEAR (0x100000)
377#define QIB_SENDCTRL_DISARM_ALL (0x200000)
378
379
380
381
382
383
384
385
386#define QIBPORTCNTR_PKTSEND 0U
387#define QIBPORTCNTR_WORDSEND 1U
388#define QIBPORTCNTR_PSXMITDATA 2U
389#define QIBPORTCNTR_PSXMITPKTS 3U
390#define QIBPORTCNTR_PSXMITWAIT 4U
391#define QIBPORTCNTR_SENDSTALL 5U
392
393#define QIBPORTCNTR_PKTRCV 6U
394#define QIBPORTCNTR_PSRCVDATA 7U
395#define QIBPORTCNTR_PSRCVPKTS 8U
396#define QIBPORTCNTR_RCVEBP 9U
397#define QIBPORTCNTR_RCVOVFL 10U
398#define QIBPORTCNTR_WORDRCV 11U
399
400#define QIBPORTCNTR_RXLOCALPHYERR 12U
401#define QIBPORTCNTR_RXVLERR 13U
402#define QIBPORTCNTR_ERRICRC 14U
403#define QIBPORTCNTR_ERRVCRC 15U
404#define QIBPORTCNTR_ERRLPCRC 16U
405#define QIBPORTCNTR_BADFORMAT 17U
406#define QIBPORTCNTR_ERR_RLEN 18U
407#define QIBPORTCNTR_IBSYMBOLERR 19U
408#define QIBPORTCNTR_INVALIDRLEN 20U
409#define QIBPORTCNTR_UNSUPVL 21U
410#define QIBPORTCNTR_EXCESSBUFOVFL 22U
411#define QIBPORTCNTR_ERRLINK 23U
412#define QIBPORTCNTR_IBLINKDOWN 24U
413#define QIBPORTCNTR_IBLINKERRRECOV 25U
414#define QIBPORTCNTR_LLI 26U
415
416#define QIBPORTCNTR_RXDROPPKT 27U
417#define QIBPORTCNTR_VL15PKTDROP 28U
418#define QIBPORTCNTR_ERRPKEY 29U
419#define QIBPORTCNTR_KHDROVFL 30U
420
421#define QIBPORTCNTR_PSINTERVAL 31U
422#define QIBPORTCNTR_PSSTART 32U
423#define QIBPORTCNTR_PSSTAT 33U
424
425
426#define ACTIVITY_TIMER 5
427
428#define MAX_NAME_SIZE 64
429
430#ifdef CONFIG_INFINIBAND_QIB_DCA
431struct qib_irq_notify;
432#endif
433
434struct qib_msix_entry {
435 void *arg;
436#ifdef CONFIG_INFINIBAND_QIB_DCA
437 int dca;
438 int rcv;
439 struct qib_irq_notify *notifier;
440#endif
441 cpumask_var_t mask;
442};
443
444
445
446
447
448
449struct qib_chip_specific;
450struct qib_chipport_specific;
451
452enum qib_sdma_states {
453 qib_sdma_state_s00_hw_down,
454 qib_sdma_state_s10_hw_start_up_wait,
455 qib_sdma_state_s20_idle,
456 qib_sdma_state_s30_sw_clean_up_wait,
457 qib_sdma_state_s40_hw_clean_up_wait,
458 qib_sdma_state_s50_hw_halt_wait,
459 qib_sdma_state_s99_running,
460};
461
462enum qib_sdma_events {
463 qib_sdma_event_e00_go_hw_down,
464 qib_sdma_event_e10_go_hw_start,
465 qib_sdma_event_e20_hw_started,
466 qib_sdma_event_e30_go_running,
467 qib_sdma_event_e40_sw_cleaned,
468 qib_sdma_event_e50_hw_cleaned,
469 qib_sdma_event_e60_hw_halted,
470 qib_sdma_event_e70_go_idle,
471 qib_sdma_event_e7220_err_halted,
472 qib_sdma_event_e7322_err_halted,
473 qib_sdma_event_e90_timer_tick,
474};
475
476struct sdma_set_state_action {
477 unsigned op_enable:1;
478 unsigned op_intenable:1;
479 unsigned op_halt:1;
480 unsigned op_drain:1;
481 unsigned go_s99_running_tofalse:1;
482 unsigned go_s99_running_totrue:1;
483};
484
485struct qib_sdma_state {
486 struct kref kref;
487 struct completion comp;
488 enum qib_sdma_states current_state;
489 struct sdma_set_state_action *set_state_action;
490 unsigned current_op;
491 unsigned go_s99_running;
492 unsigned first_sendbuf;
493 unsigned last_sendbuf;
494
495 enum qib_sdma_states previous_state;
496 unsigned previous_op;
497 enum qib_sdma_events last_event;
498};
499
500struct xmit_wait {
501 struct timer_list timer;
502 u64 counter;
503 u8 flags;
504 struct cache {
505 u64 psxmitdata;
506 u64 psrcvdata;
507 u64 psxmitpkts;
508 u64 psrcvpkts;
509 u64 psxmitwait;
510 } counter_cache;
511};
512
513
514
515
516
517
518
519struct qib_pportdata {
520 struct qib_ibport ibport_data;
521
522 struct qib_devdata *dd;
523 struct qib_chippport_specific *cpspec;
524
525
526 __be64 guid;
527
528
529 u32 lflags;
530
531 u32 state_wanted;
532 spinlock_t lflags_lock;
533
534
535 atomic_t pkeyrefs[4];
536
537
538
539
540
541 u64 *statusp;
542
543
544
545
546 struct qib_sdma_desc *sdma_descq;
547 struct workqueue_struct *qib_wq;
548 struct qib_sdma_state sdma_state;
549 dma_addr_t sdma_descq_phys;
550 volatile __le64 *sdma_head_dma;
551 dma_addr_t sdma_head_phys;
552 u16 sdma_descq_cnt;
553
554
555 spinlock_t sdma_lock ____cacheline_aligned_in_smp;
556 struct list_head sdma_activelist;
557 struct list_head sdma_userpending;
558 u64 sdma_descq_added;
559 u64 sdma_descq_removed;
560 u16 sdma_descq_tail;
561 u16 sdma_descq_head;
562 u8 sdma_generation;
563 u8 sdma_intrequest;
564
565 struct tasklet_struct sdma_sw_clean_up_task
566 ____cacheline_aligned_in_smp;
567
568 wait_queue_head_t state_wait;
569
570
571 unsigned hol_state;
572 struct timer_list hol_timer;
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589 u64 lastibcstat;
590
591
592
593
594
595
596
597 unsigned long p_rcvctrl;
598 unsigned long p_sendctrl;
599
600 u32 ibmtu;
601
602
603
604
605 u32 ibmaxlen;
606
607
608
609
610 u32 init_ibmaxlen;
611
612 u16 lid;
613
614 u16 pkeys[4];
615
616 u8 lmc;
617 u8 link_width_supported;
618 u16 link_speed_supported;
619 u8 link_width_enabled;
620 u16 link_speed_enabled;
621 u8 link_width_active;
622 u16 link_speed_active;
623 u8 vls_supported;
624 u8 vls_operational;
625
626 u8 rx_pol_inv;
627
628 u8 hw_pidx;
629 u32 port;
630
631 u8 delay_mult;
632
633
634 u8 led_override;
635 u16 led_override_timeoff;
636 u8 led_override_vals[2];
637 u8 led_override_phase;
638 atomic_t led_override_timer_active;
639
640 struct timer_list led_override_timer;
641 struct xmit_wait cong_stats;
642 struct timer_list symerr_clear_timer;
643
644
645 spinlock_t cc_shadow_lock
646 ____cacheline_aligned_in_smp;
647
648
649 struct cc_table_shadow *ccti_entries_shadow;
650
651
652 struct ib_cc_congestion_setting_attr_shadow *congestion_entries_shadow;
653
654
655 struct ib_cc_table_entry_shadow *ccti_entries;
656
657
658 struct ib_cc_congestion_entry_shadow *congestion_entries;
659
660
661
662
663 u16 cc_supported_table_entries;
664
665
666 u16 total_cct_entry;
667
668
669 u16 cc_sl_control_map;
670
671
672 u16 ccti_limit;
673
674
675 u8 cc_max_table_entries;
676};
677
678
679
680
681
682
683
684
685struct diag_observer;
686
687typedef int (*diag_hook) (struct qib_devdata *dd,
688 const struct diag_observer *op,
689 u32 offs, u64 *data, u64 mask, int only_32);
690
691struct diag_observer {
692 diag_hook hook;
693 u32 bottom;
694 u32 top;
695};
696
697extern int qib_register_observer(struct qib_devdata *dd,
698 const struct diag_observer *op);
699
700
701struct diag_observer_list_elt;
702
703
704
705
706
707
708struct qib_devdata {
709 struct qib_ibdev verbs_dev;
710 struct list_head list;
711
712
713 struct pci_dev *pcidev;
714 struct cdev *user_cdev;
715 struct cdev *diag_cdev;
716 struct device *user_device;
717 struct device *diag_device;
718
719
720 u64 __iomem *kregbase;
721
722 u64 __iomem *kregend;
723
724 resource_size_t physaddr;
725
726 struct qib_ctxtdata **rcd;
727
728
729
730
731 struct qib_pportdata *pport;
732 struct qib_chip_specific *cspec;
733
734
735 void __iomem *pio2kbase;
736
737 void __iomem *pio4kbase;
738
739 void __iomem *piobase;
740
741 u64 __iomem *userbase;
742 void __iomem *piovl15base;
743
744
745
746
747
748
749
750 volatile __le64 *pioavailregs_dma;
751
752 dma_addr_t pioavailregs_phys;
753
754
755
756
757
758
759
760 int (*f_intr_fallback)(struct qib_devdata *);
761
762 int (*f_reset)(struct qib_devdata *);
763 void (*f_quiet_serdes)(struct qib_pportdata *);
764 int (*f_bringup_serdes)(struct qib_pportdata *);
765 int (*f_early_init)(struct qib_devdata *);
766 void (*f_clear_tids)(struct qib_devdata *, struct qib_ctxtdata *);
767 void (*f_put_tid)(struct qib_devdata *, u64 __iomem*,
768 u32, unsigned long);
769 void (*f_cleanup)(struct qib_devdata *);
770 void (*f_setextled)(struct qib_pportdata *, u32);
771
772 int (*f_get_base_info)(struct qib_ctxtdata *, struct qib_base_info *);
773
774 void (*f_free_irq)(struct qib_devdata *);
775 struct qib_message_header *(*f_get_msgheader)
776 (struct qib_devdata *, __le32 *);
777 void (*f_config_ctxts)(struct qib_devdata *);
778 int (*f_get_ib_cfg)(struct qib_pportdata *, int);
779 int (*f_set_ib_cfg)(struct qib_pportdata *, int, u32);
780 int (*f_set_ib_loopback)(struct qib_pportdata *, const char *);
781 int (*f_get_ib_table)(struct qib_pportdata *, int, void *);
782 int (*f_set_ib_table)(struct qib_pportdata *, int, void *);
783 u32 (*f_iblink_state)(u64);
784 u8 (*f_ibphys_portstate)(u64);
785 void (*f_xgxs_reset)(struct qib_pportdata *);
786
787 int (*f_ib_updown)(struct qib_pportdata *, int, u64);
788 u32 __iomem *(*f_getsendbuf)(struct qib_pportdata *, u64, u32 *);
789
790 int (*f_gpio_mod)(struct qib_devdata *dd, u32 out, u32 dir,
791 u32 mask);
792
793 int (*f_eeprom_wen)(struct qib_devdata *dd, int wen);
794
795
796
797
798
799
800 void (*f_rcvctrl)(struct qib_pportdata *, unsigned int op,
801 int ctxt);
802
803 void (*f_sendctrl)(struct qib_pportdata *, u32 op);
804 void (*f_set_intr_state)(struct qib_devdata *, u32);
805 void (*f_set_armlaunch)(struct qib_devdata *, u32);
806 void (*f_wantpiobuf_intr)(struct qib_devdata *, u32);
807 int (*f_late_initreg)(struct qib_devdata *);
808 int (*f_init_sdma_regs)(struct qib_pportdata *);
809 u16 (*f_sdma_gethead)(struct qib_pportdata *);
810 int (*f_sdma_busy)(struct qib_pportdata *);
811 void (*f_sdma_update_tail)(struct qib_pportdata *, u16);
812 void (*f_sdma_set_desc_cnt)(struct qib_pportdata *, unsigned);
813 void (*f_sdma_sendctrl)(struct qib_pportdata *, unsigned);
814 void (*f_sdma_hw_clean_up)(struct qib_pportdata *);
815 void (*f_sdma_hw_start_up)(struct qib_pportdata *);
816 void (*f_sdma_init_early)(struct qib_pportdata *);
817 void (*f_set_cntr_sample)(struct qib_pportdata *, u32, u32);
818 void (*f_update_usrhead)(struct qib_ctxtdata *, u64, u32, u32, u32);
819 u32 (*f_hdrqempty)(struct qib_ctxtdata *);
820 u64 (*f_portcntr)(struct qib_pportdata *, u32);
821 u32 (*f_read_cntrs)(struct qib_devdata *, loff_t, char **,
822 u64 **);
823 u32 (*f_read_portcntrs)(struct qib_devdata *, loff_t, u32,
824 char **, u64 **);
825 u32 (*f_setpbc_control)(struct qib_pportdata *, u32, u8, u8);
826 void (*f_initvl15_bufs)(struct qib_devdata *);
827 void (*f_init_ctxt)(struct qib_ctxtdata *);
828 void (*f_txchk_change)(struct qib_devdata *, u32, u32, u32,
829 struct qib_ctxtdata *);
830 void (*f_writescratch)(struct qib_devdata *, u32);
831 int (*f_tempsense_rd)(struct qib_devdata *, int regnum);
832#ifdef CONFIG_INFINIBAND_QIB_DCA
833 int (*f_notify_dca)(struct qib_devdata *, unsigned long event);
834#endif
835
836 char *boardname;
837
838
839 u64 tidtemplate;
840
841 u64 tidinvalid;
842
843
844 u32 pioavregs;
845
846 u32 flags;
847
848 u32 lastctxt_piobuf;
849
850
851 u64 z_int_counter;
852
853 u64 __percpu *int_counter;
854
855
856 u32 pbufsctxt;
857
858 u32 ctxts_extrabuf;
859
860
861
862
863 u32 cfgctxts;
864
865
866
867 u32 freectxts;
868
869
870
871
872
873 u32 upd_pio_shadow;
874
875
876 u32 maxpkts_call;
877 u32 avgpkts_call;
878 u64 nopiobufs;
879
880
881 u16 vendorid;
882
883 u16 deviceid;
884
885 int wc_cookie;
886 unsigned long wc_base;
887 unsigned long wc_len;
888
889
890 struct page **pageshadow;
891
892 dma_addr_t *physshadow;
893 u64 __iomem *egrtidbase;
894 spinlock_t sendctrl_lock;
895
896 spinlock_t uctxt_lock;
897
898
899
900
901
902 u64 *devstatusp;
903 char *freezemsg;
904 u32 freezelen;
905
906 struct timer_list stats_timer;
907
908
909 struct timer_list intrchk_timer;
910 unsigned long ureg_align;
911
912
913
914
915
916 spinlock_t pioavail_lock;
917
918
919
920 u32 last_pio;
921
922
923
924 u32 min_kernel_pio;
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940 unsigned long pioavailshadow[6];
941
942 unsigned long pioavailkernel[6];
943
944 unsigned long pio_need_disarm[3];
945
946 unsigned long pio_writing[3];
947
948 u64 revision;
949
950 __be64 base_guid;
951
952
953
954
955
956 u64 piobufbase;
957 u32 pio2k_bufbase;
958
959
960
961
962 u32 nguid;
963
964
965
966
967 unsigned long rcvctrl;
968 unsigned long sendctrl;
969
970
971 u32 rcvhdrcnt;
972
973 u32 rcvhdrsize;
974
975 u32 rcvhdrentsize;
976
977 u32 ctxtcnt;
978
979 u32 palign;
980
981 u32 piobcnt2k;
982
983 u32 piosize2k;
984
985 u32 piosize2kmax_dwords;
986
987 u32 piobcnt4k;
988
989 u32 piosize4k;
990
991 u32 rcvegrbase;
992
993 u32 rcvtidbase;
994
995 u32 rcvtidcnt;
996
997 u32 uregbase;
998
999 u32 control;
1000
1001
1002 u32 align4k;
1003
1004 u16 rcvegrbufsize;
1005
1006 u16 rcvegrbufsize_shift;
1007
1008 u32 lbus_width;
1009
1010 u32 lbus_speed;
1011 int unit;
1012
1013
1014
1015 u32 msi_lo;
1016
1017 u32 msi_hi;
1018
1019 u16 msi_data;
1020
1021 u32 pcibar0;
1022
1023 u32 pcibar1;
1024 u64 rhdrhead_intr_off;
1025
1026
1027
1028
1029
1030 u8 serial[16];
1031
1032 u8 boardversion[96];
1033 u8 lbus_info[32];
1034
1035 u8 majrev;
1036
1037 u8 minrev;
1038
1039
1040
1041 u8 num_pports;
1042
1043 u8 first_user_ctxt;
1044 u8 n_krcv_queues;
1045 u8 qpn_mask;
1046 u8 skip_kctxt_mask;
1047
1048 u16 rhf_offset;
1049
1050
1051
1052
1053 u8 gpio_sda_num;
1054 u8 gpio_scl_num;
1055 u8 twsi_eeprom_dev;
1056 u8 board_atten;
1057
1058
1059
1060 spinlock_t eep_st_lock;
1061
1062 struct mutex eep_lock;
1063 uint64_t traffic_wds;
1064 struct qib_diag_client *diag_client;
1065 spinlock_t qib_diag_trans_lock;
1066 struct diag_observer_list_elt *diag_observer_list;
1067
1068 u8 psxmitwait_supported;
1069
1070 u16 psxmitwait_check_rate;
1071
1072 struct tasklet_struct error_tasklet;
1073
1074 int assigned_node_id;
1075};
1076
1077
1078#define QIB_HOL_UP 0
1079#define QIB_HOL_INIT 1
1080
1081#define QIB_SDMA_SENDCTRL_OP_ENABLE (1U << 0)
1082#define QIB_SDMA_SENDCTRL_OP_INTENABLE (1U << 1)
1083#define QIB_SDMA_SENDCTRL_OP_HALT (1U << 2)
1084#define QIB_SDMA_SENDCTRL_OP_CLEANUP (1U << 3)
1085#define QIB_SDMA_SENDCTRL_OP_DRAIN (1U << 4)
1086
1087
1088#define TXCHK_CHG_TYPE_DIS1 3
1089#define TXCHK_CHG_TYPE_ENAB1 2
1090#define TXCHK_CHG_TYPE_KERN 1
1091#define TXCHK_CHG_TYPE_USER 0
1092
1093#define QIB_CHASE_TIME msecs_to_jiffies(145)
1094#define QIB_CHASE_DIS_TIME msecs_to_jiffies(160)
1095
1096
1097struct qib_filedata {
1098 struct qib_ctxtdata *rcd;
1099 unsigned subctxt;
1100 unsigned tidcursor;
1101 struct qib_user_sdma_queue *pq;
1102 int rec_cpu_num;
1103};
1104
1105extern struct xarray qib_dev_table;
1106extern struct qib_devdata *qib_lookup(int unit);
1107extern u32 qib_cpulist_count;
1108extern unsigned long *qib_cpulist;
1109extern unsigned qib_cc_table_size;
1110
1111int qib_init(struct qib_devdata *, int);
1112int init_chip_wc_pat(struct qib_devdata *dd, u32);
1113int qib_enable_wc(struct qib_devdata *dd);
1114void qib_disable_wc(struct qib_devdata *dd);
1115int qib_count_units(int *npresentp, int *nupp);
1116int qib_count_active_units(void);
1117
1118int qib_cdev_init(int minor, const char *name,
1119 const struct file_operations *fops,
1120 struct cdev **cdevp, struct device **devp);
1121void qib_cdev_cleanup(struct cdev **cdevp, struct device **devp);
1122int qib_dev_init(void);
1123void qib_dev_cleanup(void);
1124
1125int qib_diag_add(struct qib_devdata *);
1126void qib_diag_remove(struct qib_devdata *);
1127void qib_handle_e_ibstatuschanged(struct qib_pportdata *, u64);
1128void qib_sdma_update_tail(struct qib_pportdata *, u16);
1129
1130int qib_decode_err(struct qib_devdata *dd, char *buf, size_t blen, u64 err);
1131void qib_bad_intrstatus(struct qib_devdata *);
1132void qib_handle_urcv(struct qib_devdata *, u64);
1133
1134
1135void qib_chip_cleanup(struct qib_devdata *);
1136
1137void qib_chip_done(void);
1138
1139
1140int qib_unordered_wc(void);
1141void qib_pio_copy(void __iomem *to, const void *from, size_t count);
1142
1143void qib_disarm_piobufs(struct qib_devdata *, unsigned, unsigned);
1144int qib_disarm_piobufs_ifneeded(struct qib_ctxtdata *);
1145void qib_disarm_piobufs_set(struct qib_devdata *, unsigned long *, unsigned);
1146void qib_cancel_sends(struct qib_pportdata *);
1147
1148int qib_create_rcvhdrq(struct qib_devdata *, struct qib_ctxtdata *);
1149int qib_setup_eagerbufs(struct qib_ctxtdata *);
1150void qib_set_ctxtcnt(struct qib_devdata *);
1151int qib_create_ctxts(struct qib_devdata *dd);
1152struct qib_ctxtdata *qib_create_ctxtdata(struct qib_pportdata *, u32, int);
1153int qib_init_pportdata(struct qib_pportdata *, struct qib_devdata *, u8, u8);
1154void qib_free_ctxtdata(struct qib_devdata *, struct qib_ctxtdata *);
1155
1156u32 qib_kreceive(struct qib_ctxtdata *, u32 *, u32 *);
1157int qib_reset_device(int);
1158int qib_wait_linkstate(struct qib_pportdata *, u32, int);
1159int qib_set_linkstate(struct qib_pportdata *, u8);
1160int qib_set_mtu(struct qib_pportdata *, u16);
1161int qib_set_lid(struct qib_pportdata *, u32, u8);
1162void qib_hol_down(struct qib_pportdata *);
1163void qib_hol_init(struct qib_pportdata *);
1164void qib_hol_up(struct qib_pportdata *);
1165void qib_hol_event(struct timer_list *);
1166void qib_disable_after_error(struct qib_devdata *);
1167int qib_set_uevent_bits(struct qib_pportdata *, const int);
1168
1169
1170#define ctxt_fp(fp) \
1171 (((struct qib_filedata *)(fp)->private_data)->rcd)
1172#define subctxt_fp(fp) \
1173 (((struct qib_filedata *)(fp)->private_data)->subctxt)
1174#define tidcursor_fp(fp) \
1175 (((struct qib_filedata *)(fp)->private_data)->tidcursor)
1176#define user_sdma_queue_fp(fp) \
1177 (((struct qib_filedata *)(fp)->private_data)->pq)
1178
1179static inline struct qib_devdata *dd_from_ppd(struct qib_pportdata *ppd)
1180{
1181 return ppd->dd;
1182}
1183
1184static inline struct qib_devdata *dd_from_dev(struct qib_ibdev *dev)
1185{
1186 return container_of(dev, struct qib_devdata, verbs_dev);
1187}
1188
1189static inline struct qib_devdata *dd_from_ibdev(struct ib_device *ibdev)
1190{
1191 return dd_from_dev(to_idev(ibdev));
1192}
1193
1194static inline struct qib_pportdata *ppd_from_ibp(struct qib_ibport *ibp)
1195{
1196 return container_of(ibp, struct qib_pportdata, ibport_data);
1197}
1198
1199static inline struct qib_ibport *to_iport(struct ib_device *ibdev, u32 port)
1200{
1201 struct qib_devdata *dd = dd_from_ibdev(ibdev);
1202 u32 pidx = port - 1;
1203
1204 WARN_ON(pidx >= dd->num_pports);
1205 return &dd->pport[pidx].ibport_data;
1206}
1207
1208
1209
1210
1211#define QIB_HAS_LINK_LATENCY 0x1
1212#define QIB_INITTED 0x2
1213#define QIB_DOING_RESET 0x4
1214#define QIB_PRESENT 0x8
1215#define QIB_PIO_FLUSH_WC 0x10
1216#define QIB_HAS_THRESH_UPDATE 0x40
1217#define QIB_HAS_SDMA_TIMEOUT 0x80
1218#define QIB_USE_SPCL_TRIG 0x100
1219#define QIB_NODMA_RTAIL 0x200
1220#define QIB_HAS_INTX 0x800
1221#define QIB_HAS_SEND_DMA 0x1000
1222#define QIB_HAS_VLSUPP 0x2000
1223#define QIB_HAS_HDRSUPP 0x4000
1224#define QIB_BADINTR 0x8000
1225#define QIB_DCA_ENABLED 0x10000
1226#define QIB_HAS_QSFP 0x20000
1227#define QIB_SHUTDOWN 0x40000
1228
1229
1230
1231
1232#define QIBL_LINKV 0x1
1233#define QIBL_LINKDOWN 0x8
1234#define QIBL_LINKINIT 0x10
1235#define QIBL_LINKARMED 0x20
1236#define QIBL_LINKACTIVE 0x40
1237
1238#define QIBL_IB_AUTONEG_INPROG 0x1000
1239#define QIBL_IB_AUTONEG_FAILED 0x2000
1240#define QIBL_IB_LINK_DISABLED 0x4000
1241
1242#define QIBL_IB_FORCE_NOTIFY 0x8000
1243
1244
1245#define QIB_PBC_LENGTH_MASK ((1 << 11) - 1)
1246
1247
1248
1249
1250#define QIB_CTXT_WAITING_RCV 2
1251
1252#define QIB_CTXT_MASTER_UNINIT 4
1253
1254#define QIB_CTXT_WAITING_URG 5
1255
1256
1257void qib_free_data(struct qib_ctxtdata *dd);
1258void qib_chg_pioavailkernel(struct qib_devdata *, unsigned, unsigned,
1259 u32, struct qib_ctxtdata *);
1260struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *,
1261 const struct pci_device_id *);
1262struct qib_devdata *qib_init_iba7220_funcs(struct pci_dev *,
1263 const struct pci_device_id *);
1264struct qib_devdata *qib_init_iba6120_funcs(struct pci_dev *,
1265 const struct pci_device_id *);
1266void qib_free_devdata(struct qib_devdata *);
1267struct qib_devdata *qib_alloc_devdata(struct pci_dev *pdev, size_t extra);
1268
1269#define QIB_TWSI_NO_DEV 0xFF
1270
1271int qib_twsi_reset(struct qib_devdata *dd);
1272int qib_twsi_blk_rd(struct qib_devdata *dd, int dev, int addr, void *buffer,
1273 int len);
1274int qib_twsi_blk_wr(struct qib_devdata *dd, int dev, int addr,
1275 const void *buffer, int len);
1276void qib_get_eeprom_info(struct qib_devdata *);
1277void qib_dump_lookup_output_queue(struct qib_devdata *);
1278void qib_force_pio_avail_update(struct qib_devdata *);
1279void qib_clear_symerror_on_linkup(struct timer_list *t);
1280
1281
1282
1283
1284
1285
1286#define QIB_LED_PHYS 1
1287#define QIB_LED_LOG 2
1288void qib_set_led_override(struct qib_pportdata *ppd, unsigned int val);
1289
1290
1291int qib_setup_sdma(struct qib_pportdata *);
1292void qib_teardown_sdma(struct qib_pportdata *);
1293void __qib_sdma_intr(struct qib_pportdata *);
1294void qib_sdma_intr(struct qib_pportdata *);
1295void qib_user_sdma_send_desc(struct qib_pportdata *dd,
1296 struct list_head *pktlist);
1297int qib_sdma_verbs_send(struct qib_pportdata *, struct rvt_sge_state *,
1298 u32, struct qib_verbs_txreq *);
1299
1300int qib_sdma_make_progress(struct qib_pportdata *dd);
1301
1302
1303static inline u16 qib_sdma_descq_freecnt(const struct qib_pportdata *ppd)
1304{
1305 return ppd->sdma_descq_cnt -
1306 (ppd->sdma_descq_added - ppd->sdma_descq_removed) - 1;
1307}
1308
1309static inline int __qib_sdma_running(struct qib_pportdata *ppd)
1310{
1311 return ppd->sdma_state.current_state == qib_sdma_state_s99_running;
1312}
1313int qib_sdma_running(struct qib_pportdata *);
1314void dump_sdma_state(struct qib_pportdata *ppd);
1315void __qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1316void qib_sdma_process_event(struct qib_pportdata *, enum qib_sdma_events);
1317
1318
1319
1320
1321#define QIB_DFLT_RCVHDRSIZE 9
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334#define QIB_RCVHDR_ENTSIZE 32
1335
1336int qib_get_user_pages(unsigned long, size_t, struct page **);
1337void qib_release_user_pages(struct page **, size_t);
1338int qib_eeprom_read(struct qib_devdata *, u8, void *, int);
1339int qib_eeprom_write(struct qib_devdata *, u8, const void *, int);
1340u32 __iomem *qib_getsendbuf_range(struct qib_devdata *, u32 *, u32, u32);
1341void qib_sendbuf_done(struct qib_devdata *, unsigned);
1342
1343static inline void qib_clear_rcvhdrtail(const struct qib_ctxtdata *rcd)
1344{
1345 *((u64 *) rcd->rcvhdrtail_kvaddr) = 0ULL;
1346}
1347
1348static inline u32 qib_get_rcvhdrtail(const struct qib_ctxtdata *rcd)
1349{
1350
1351
1352
1353
1354 return (u32) le64_to_cpu(
1355 *((volatile __le64 *)rcd->rcvhdrtail_kvaddr));
1356}
1357
1358
1359
1360
1361
1362extern const char ib_qib_version[];
1363extern const struct attribute_group qib_attr_group;
1364extern const struct attribute_group *qib_attr_port_groups[];
1365
1366int qib_device_create(struct qib_devdata *);
1367void qib_device_remove(struct qib_devdata *);
1368
1369
1370extern int qib_qsfp_dump(struct qib_pportdata *ppd, char *buf, int len);
1371
1372int __init qib_init_qibfs(void);
1373int __exit qib_exit_qibfs(void);
1374
1375int qibfs_add(struct qib_devdata *);
1376int qibfs_remove(struct qib_devdata *);
1377
1378int qib_pcie_init(struct pci_dev *, const struct pci_device_id *);
1379int qib_pcie_ddinit(struct qib_devdata *, struct pci_dev *,
1380 const struct pci_device_id *);
1381void qib_pcie_ddcleanup(struct qib_devdata *);
1382int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent);
1383void qib_free_irq(struct qib_devdata *dd);
1384int qib_reinit_intr(struct qib_devdata *dd);
1385void qib_pcie_getcmd(struct qib_devdata *, u16 *, u8 *, u8 *);
1386void qib_pcie_reenable(struct qib_devdata *, u16, u8, u8);
1387
1388u64 qib_int_counter(struct qib_devdata *);
1389
1390u64 qib_sps_ints(void);
1391
1392
1393
1394
1395int qib_map_page(struct pci_dev *d, struct page *p, dma_addr_t *daddr);
1396struct pci_dev *qib_get_pci_dev(struct rvt_dev_info *rdi);
1397
1398
1399
1400
1401
1402static inline void qib_flush_wc(void)
1403{
1404#if defined(CONFIG_X86_64)
1405 asm volatile("sfence" : : : "memory");
1406#else
1407 wmb();
1408#endif
1409}
1410
1411
1412extern unsigned qib_ibmtu;
1413extern ushort qib_cfgctxts;
1414extern ushort qib_num_cfg_vls;
1415extern ushort qib_mini_init;
1416extern unsigned qib_n_krcv_queues;
1417extern unsigned qib_sdma_fetch_arb;
1418extern unsigned qib_compat_ddr_negotiate;
1419extern int qib_special_trigger;
1420extern unsigned qib_numa_aware;
1421
1422extern struct mutex qib_mutex;
1423
1424
1425#define STATUS_TIMEOUT 60
1426
1427#define QIB_DRV_NAME "ib_qib"
1428#define QIB_USER_MINOR_BASE 0
1429#define QIB_TRACE_MINOR 127
1430#define QIB_DIAGPKT_MINOR 128
1431#define QIB_DIAG_MINOR_BASE 129
1432#define QIB_NMINORS 255
1433
1434#define PCI_VENDOR_ID_PATHSCALE 0x1fc1
1435#define PCI_VENDOR_ID_QLOGIC 0x1077
1436#define PCI_DEVICE_ID_QLOGIC_IB_6120 0x10
1437#define PCI_DEVICE_ID_QLOGIC_IB_7220 0x7220
1438#define PCI_DEVICE_ID_QLOGIC_IB_7322 0x7322
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449#define qib_early_err(dev, fmt, ...) \
1450 dev_err(dev, fmt, ##__VA_ARGS__)
1451
1452#define qib_dev_err(dd, fmt, ...) \
1453 dev_err(&(dd)->pcidev->dev, "%s: " fmt, \
1454 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
1455
1456#define qib_dev_warn(dd, fmt, ...) \
1457 dev_warn(&(dd)->pcidev->dev, "%s: " fmt, \
1458 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), ##__VA_ARGS__)
1459
1460#define qib_dev_porterr(dd, port, fmt, ...) \
1461 dev_err(&(dd)->pcidev->dev, "%s: IB%u:%u " fmt, \
1462 rvt_get_ibdev_name(&(dd)->verbs_dev.rdi), (dd)->unit, (port), \
1463 ##__VA_ARGS__)
1464
1465#define qib_devinfo(pcidev, fmt, ...) \
1466 dev_info(&(pcidev)->dev, fmt, ##__VA_ARGS__)
1467
1468
1469
1470
1471struct qib_hwerror_msgs {
1472 u64 mask;
1473 const char *msg;
1474 size_t sz;
1475};
1476
1477#define QLOGIC_IB_HWE_MSG(a, b) { .mask = a, .msg = b }
1478
1479
1480void qib_format_hwerrors(u64 hwerrs,
1481 const struct qib_hwerror_msgs *hwerrmsgs,
1482 size_t nhwerrmsgs, char *msg, size_t lmsg);
1483
1484void qib_stop_send_queue(struct rvt_qp *qp);
1485void qib_quiesce_qp(struct rvt_qp *qp);
1486void qib_flush_qp_waiters(struct rvt_qp *qp);
1487int qib_mtu_to_path_mtu(u32 mtu);
1488u32 qib_mtu_from_qp(struct rvt_dev_info *rdi, struct rvt_qp *qp, u32 pmtu);
1489void qib_notify_error_qp(struct rvt_qp *qp);
1490int qib_get_pmtu_from_attr(struct rvt_dev_info *rdi, struct rvt_qp *qp,
1491 struct ib_qp_attr *attr);
1492
1493#endif
1494