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7#include <dt-bindings/interconnect/qcom,sdm660.h>
8#include <linux/clk.h>
9#include <linux/device.h>
10#include <linux/interconnect-provider.h>
11#include <linux/io.h>
12#include <linux/module.h>
13#include <linux/of_device.h>
14#include <linux/of_platform.h>
15#include <linux/platform_device.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18
19#include "smd-rpm.h"
20
21#define RPM_BUS_MASTER_REQ 0x73616d62
22#define RPM_BUS_SLAVE_REQ 0x766c7362
23
24
25#define M_BKE_REG_BASE(n) (0x300 + (0x4000 * n))
26#define M_BKE_EN_ADDR(n) (M_BKE_REG_BASE(n))
27#define M_BKE_HEALTH_CFG_ADDR(i, n) (M_BKE_REG_BASE(n) + 0x40 + (0x4 * i))
28
29#define M_BKE_HEALTH_CFG_LIMITCMDS_MASK 0x80000000
30#define M_BKE_HEALTH_CFG_AREQPRIO_MASK 0x300
31#define M_BKE_HEALTH_CFG_PRIOLVL_MASK 0x3
32#define M_BKE_HEALTH_CFG_AREQPRIO_SHIFT 0x8
33#define M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT 0x1f
34
35#define M_BKE_EN_EN_BMASK 0x1
36
37
38#define NOC_QOS_MODE_FIXED 0x0
39#define NOC_QOS_MODE_LIMITER 0x1
40#define NOC_QOS_MODE_BYPASS 0x2
41
42
43#define NOC_PERM_MODE_FIXED 1
44#define NOC_PERM_MODE_BYPASS (1 << NOC_QOS_MODE_BYPASS)
45
46#define NOC_QOS_PRIORITYn_ADDR(n) (0x8 + (n * 0x1000))
47#define NOC_QOS_PRIORITY_P1_MASK 0xc
48#define NOC_QOS_PRIORITY_P0_MASK 0x3
49#define NOC_QOS_PRIORITY_P1_SHIFT 0x2
50
51#define NOC_QOS_MODEn_ADDR(n) (0xc + (n * 0x1000))
52#define NOC_QOS_MODEn_MASK 0x3
53
54enum {
55 SDM660_MASTER_IPA = 1,
56 SDM660_MASTER_CNOC_A2NOC,
57 SDM660_MASTER_SDCC_1,
58 SDM660_MASTER_SDCC_2,
59 SDM660_MASTER_BLSP_1,
60 SDM660_MASTER_BLSP_2,
61 SDM660_MASTER_UFS,
62 SDM660_MASTER_USB_HS,
63 SDM660_MASTER_USB3,
64 SDM660_MASTER_CRYPTO_C0,
65 SDM660_MASTER_GNOC_BIMC,
66 SDM660_MASTER_OXILI,
67 SDM660_MASTER_MNOC_BIMC,
68 SDM660_MASTER_SNOC_BIMC,
69 SDM660_MASTER_PIMEM,
70 SDM660_MASTER_SNOC_CNOC,
71 SDM660_MASTER_QDSS_DAP,
72 SDM660_MASTER_APPS_PROC,
73 SDM660_MASTER_CNOC_MNOC_MMSS_CFG,
74 SDM660_MASTER_CNOC_MNOC_CFG,
75 SDM660_MASTER_CPP,
76 SDM660_MASTER_JPEG,
77 SDM660_MASTER_MDP_P0,
78 SDM660_MASTER_MDP_P1,
79 SDM660_MASTER_VENUS,
80 SDM660_MASTER_VFE,
81 SDM660_MASTER_QDSS_ETR,
82 SDM660_MASTER_QDSS_BAM,
83 SDM660_MASTER_SNOC_CFG,
84 SDM660_MASTER_BIMC_SNOC,
85 SDM660_MASTER_A2NOC_SNOC,
86 SDM660_MASTER_GNOC_SNOC,
87
88 SDM660_SLAVE_A2NOC_SNOC,
89 SDM660_SLAVE_EBI,
90 SDM660_SLAVE_HMSS_L3,
91 SDM660_SLAVE_BIMC_SNOC,
92 SDM660_SLAVE_CNOC_A2NOC,
93 SDM660_SLAVE_MPM,
94 SDM660_SLAVE_PMIC_ARB,
95 SDM660_SLAVE_TLMM_NORTH,
96 SDM660_SLAVE_TCSR,
97 SDM660_SLAVE_PIMEM_CFG,
98 SDM660_SLAVE_IMEM_CFG,
99 SDM660_SLAVE_MESSAGE_RAM,
100 SDM660_SLAVE_GLM,
101 SDM660_SLAVE_BIMC_CFG,
102 SDM660_SLAVE_PRNG,
103 SDM660_SLAVE_SPDM,
104 SDM660_SLAVE_QDSS_CFG,
105 SDM660_SLAVE_CNOC_MNOC_CFG,
106 SDM660_SLAVE_SNOC_CFG,
107 SDM660_SLAVE_QM_CFG,
108 SDM660_SLAVE_CLK_CTL,
109 SDM660_SLAVE_MSS_CFG,
110 SDM660_SLAVE_TLMM_SOUTH,
111 SDM660_SLAVE_UFS_CFG,
112 SDM660_SLAVE_A2NOC_CFG,
113 SDM660_SLAVE_A2NOC_SMMU_CFG,
114 SDM660_SLAVE_GPUSS_CFG,
115 SDM660_SLAVE_AHB2PHY,
116 SDM660_SLAVE_BLSP_1,
117 SDM660_SLAVE_SDCC_1,
118 SDM660_SLAVE_SDCC_2,
119 SDM660_SLAVE_TLMM_CENTER,
120 SDM660_SLAVE_BLSP_2,
121 SDM660_SLAVE_PDM,
122 SDM660_SLAVE_CNOC_MNOC_MMSS_CFG,
123 SDM660_SLAVE_USB_HS,
124 SDM660_SLAVE_USB3_0,
125 SDM660_SLAVE_SRVC_CNOC,
126 SDM660_SLAVE_GNOC_BIMC,
127 SDM660_SLAVE_GNOC_SNOC,
128 SDM660_SLAVE_CAMERA_CFG,
129 SDM660_SLAVE_CAMERA_THROTTLE_CFG,
130 SDM660_SLAVE_MISC_CFG,
131 SDM660_SLAVE_VENUS_THROTTLE_CFG,
132 SDM660_SLAVE_VENUS_CFG,
133 SDM660_SLAVE_MMSS_CLK_XPU_CFG,
134 SDM660_SLAVE_MMSS_CLK_CFG,
135 SDM660_SLAVE_MNOC_MPU_CFG,
136 SDM660_SLAVE_DISPLAY_CFG,
137 SDM660_SLAVE_CSI_PHY_CFG,
138 SDM660_SLAVE_DISPLAY_THROTTLE_CFG,
139 SDM660_SLAVE_SMMU_CFG,
140 SDM660_SLAVE_MNOC_BIMC,
141 SDM660_SLAVE_SRVC_MNOC,
142 SDM660_SLAVE_HMSS,
143 SDM660_SLAVE_LPASS,
144 SDM660_SLAVE_WLAN,
145 SDM660_SLAVE_CDSP,
146 SDM660_SLAVE_IPA,
147 SDM660_SLAVE_SNOC_BIMC,
148 SDM660_SLAVE_SNOC_CNOC,
149 SDM660_SLAVE_IMEM,
150 SDM660_SLAVE_PIMEM,
151 SDM660_SLAVE_QDSS_STM,
152 SDM660_SLAVE_SRVC_SNOC,
153
154 SDM660_A2NOC,
155 SDM660_BIMC,
156 SDM660_CNOC,
157 SDM660_GNOC,
158 SDM660_MNOC,
159 SDM660_SNOC,
160};
161
162#define to_qcom_provider(_provider) \
163 container_of(_provider, struct qcom_icc_provider, provider)
164
165static const struct clk_bulk_data bus_clocks[] = {
166 { .id = "bus" },
167 { .id = "bus_a" },
168};
169
170static const struct clk_bulk_data bus_mm_clocks[] = {
171 { .id = "bus" },
172 { .id = "bus_a" },
173 { .id = "iface" },
174};
175
176static const struct clk_bulk_data bus_a2noc_clocks[] = {
177 { .id = "bus" },
178 { .id = "bus_a" },
179 { .id = "ipa" },
180 { .id = "ufs_axi" },
181 { .id = "aggre2_ufs_axi" },
182 { .id = "aggre2_usb3_axi" },
183 { .id = "cfg_noc_usb2_axi" },
184};
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194
195struct qcom_icc_provider {
196 struct icc_provider provider;
197 struct clk_bulk_data *bus_clks;
198 int num_clks;
199 bool is_bimc_node;
200 struct regmap *regmap;
201 void __iomem *mmio;
202};
203
204#define SDM660_MAX_LINKS 34
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214
215struct qcom_icc_qos {
216 u32 areq_prio;
217 u32 prio_level;
218 bool limit_commands;
219 bool ap_owned;
220 int qos_mode;
221 int qos_port;
222};
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235
236struct qcom_icc_node {
237 unsigned char *name;
238 u16 id;
239 u16 links[SDM660_MAX_LINKS];
240 u16 num_links;
241 u16 buswidth;
242 int mas_rpm_id;
243 int slv_rpm_id;
244 struct qcom_icc_qos qos;
245 u64 rate;
246};
247
248struct qcom_icc_desc {
249 struct qcom_icc_node **nodes;
250 size_t num_nodes;
251 const struct regmap_config *regmap_cfg;
252};
253
254#define DEFINE_QNODE(_name, _id, _buswidth, _mas_rpm_id, _slv_rpm_id, \
255 _ap_owned, _qos_mode, _qos_prio, _qos_port, ...) \
256 static struct qcom_icc_node _name = { \
257 .name = #_name, \
258 .id = _id, \
259 .buswidth = _buswidth, \
260 .mas_rpm_id = _mas_rpm_id, \
261 .slv_rpm_id = _slv_rpm_id, \
262 .qos.ap_owned = _ap_owned, \
263 .qos.qos_mode = _qos_mode, \
264 .qos.areq_prio = _qos_prio, \
265 .qos.prio_level = _qos_prio, \
266 .qos.qos_port = _qos_port, \
267 .num_links = ARRAY_SIZE(((int[]){ __VA_ARGS__ })), \
268 .links = { __VA_ARGS__ }, \
269 }
270
271DEFINE_QNODE(mas_ipa, SDM660_MASTER_IPA, 8, 59, -1, true, NOC_QOS_MODE_FIXED, 1, 3, SDM660_SLAVE_A2NOC_SNOC);
272DEFINE_QNODE(mas_cnoc_a2noc, SDM660_MASTER_CNOC_A2NOC, 8, 146, -1, true, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
273DEFINE_QNODE(mas_sdcc_1, SDM660_MASTER_SDCC_1, 8, 33, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
274DEFINE_QNODE(mas_sdcc_2, SDM660_MASTER_SDCC_2, 8, 35, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
275DEFINE_QNODE(mas_blsp_1, SDM660_MASTER_BLSP_1, 4, 41, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
276DEFINE_QNODE(mas_blsp_2, SDM660_MASTER_BLSP_2, 4, 39, -1, false, -1, 0, -1, SDM660_SLAVE_A2NOC_SNOC);
277DEFINE_QNODE(mas_ufs, SDM660_MASTER_UFS, 8, 68, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_A2NOC_SNOC);
278DEFINE_QNODE(mas_usb_hs, SDM660_MASTER_USB_HS, 8, 42, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_A2NOC_SNOC);
279DEFINE_QNODE(mas_usb3, SDM660_MASTER_USB3, 8, 32, -1, true, NOC_QOS_MODE_FIXED, 1, 2, SDM660_SLAVE_A2NOC_SNOC);
280DEFINE_QNODE(mas_crypto, SDM660_MASTER_CRYPTO_C0, 8, 23, -1, true, NOC_QOS_MODE_FIXED, 1, 11, SDM660_SLAVE_A2NOC_SNOC);
281DEFINE_QNODE(mas_gnoc_bimc, SDM660_MASTER_GNOC_BIMC, 4, 144, -1, true, NOC_QOS_MODE_FIXED, 0, 0, SDM660_SLAVE_EBI);
282DEFINE_QNODE(mas_oxili, SDM660_MASTER_OXILI, 4, 6, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
283DEFINE_QNODE(mas_mnoc_bimc, SDM660_MASTER_MNOC_BIMC, 4, 2, -1, true, NOC_QOS_MODE_BYPASS, 0, 2, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI, SDM660_SLAVE_BIMC_SNOC);
284DEFINE_QNODE(mas_snoc_bimc, SDM660_MASTER_SNOC_BIMC, 4, 3, -1, false, -1, 0, -1, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
285DEFINE_QNODE(mas_pimem, SDM660_MASTER_PIMEM, 4, 113, -1, true, NOC_QOS_MODE_FIXED, 1, 4, SDM660_SLAVE_HMSS_L3, SDM660_SLAVE_EBI);
286DEFINE_QNODE(mas_snoc_cnoc, SDM660_MASTER_SNOC_CNOC, 8, 52, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
287DEFINE_QNODE(mas_qdss_dap, SDM660_MASTER_QDSS_DAP, 8, 49, -1, true, -1, 0, -1, SDM660_SLAVE_CLK_CTL, SDM660_SLAVE_QDSS_CFG, SDM660_SLAVE_QM_CFG, SDM660_SLAVE_SRVC_CNOC, SDM660_SLAVE_UFS_CFG, SDM660_SLAVE_TCSR, SDM660_SLAVE_A2NOC_SMMU_CFG, SDM660_SLAVE_SNOC_CFG, SDM660_SLAVE_TLMM_SOUTH, SDM660_SLAVE_MPM, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, SDM660_SLAVE_SDCC_2, SDM660_SLAVE_SDCC_1, SDM660_SLAVE_SPDM, SDM660_SLAVE_PMIC_ARB, SDM660_SLAVE_PRNG, SDM660_SLAVE_MSS_CFG, SDM660_SLAVE_GPUSS_CFG, SDM660_SLAVE_IMEM_CFG, SDM660_SLAVE_USB3_0, SDM660_SLAVE_A2NOC_CFG, SDM660_SLAVE_TLMM_NORTH, SDM660_SLAVE_USB_HS, SDM660_SLAVE_PDM, SDM660_SLAVE_TLMM_CENTER, SDM660_SLAVE_AHB2PHY, SDM660_SLAVE_BLSP_2, SDM660_SLAVE_BLSP_1, SDM660_SLAVE_PIMEM_CFG, SDM660_SLAVE_GLM, SDM660_SLAVE_MESSAGE_RAM, SDM660_SLAVE_CNOC_A2NOC, SDM660_SLAVE_BIMC_CFG, SDM660_SLAVE_CNOC_MNOC_CFG);
288DEFINE_QNODE(mas_apss_proc, SDM660_MASTER_APPS_PROC, 16, 0, -1, true, -1, 0, -1, SDM660_SLAVE_GNOC_SNOC, SDM660_SLAVE_GNOC_BIMC);
289DEFINE_QNODE(mas_cnoc_mnoc_mmss_cfg, SDM660_MASTER_CNOC_MNOC_MMSS_CFG, 8, 4, -1, true, -1, 0, -1, SDM660_SLAVE_VENUS_THROTTLE_CFG, SDM660_SLAVE_VENUS_CFG, SDM660_SLAVE_CAMERA_THROTTLE_CFG, SDM660_SLAVE_SMMU_CFG, SDM660_SLAVE_CAMERA_CFG, SDM660_SLAVE_CSI_PHY_CFG, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, SDM660_SLAVE_DISPLAY_CFG, SDM660_SLAVE_MMSS_CLK_CFG, SDM660_SLAVE_MNOC_MPU_CFG, SDM660_SLAVE_MISC_CFG, SDM660_SLAVE_MMSS_CLK_XPU_CFG);
290DEFINE_QNODE(mas_cnoc_mnoc_cfg, SDM660_MASTER_CNOC_MNOC_CFG, 4, 5, -1, true, -1, 0, -1, SDM660_SLAVE_SRVC_MNOC);
291DEFINE_QNODE(mas_cpp, SDM660_MASTER_CPP, 16, 115, -1, true, NOC_QOS_MODE_BYPASS, 0, 4, SDM660_SLAVE_MNOC_BIMC);
292DEFINE_QNODE(mas_jpeg, SDM660_MASTER_JPEG, 16, 7, -1, true, NOC_QOS_MODE_BYPASS, 0, 6, SDM660_SLAVE_MNOC_BIMC);
293DEFINE_QNODE(mas_mdp_p0, SDM660_MASTER_MDP_P0, 16, 8, -1, true, NOC_QOS_MODE_BYPASS, 0, 0, SDM660_SLAVE_MNOC_BIMC);
294DEFINE_QNODE(mas_mdp_p1, SDM660_MASTER_MDP_P1, 16, 61, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC);
295DEFINE_QNODE(mas_venus, SDM660_MASTER_VENUS, 16, 9, -1, true, NOC_QOS_MODE_BYPASS, 0, 1, SDM660_SLAVE_MNOC_BIMC);
296DEFINE_QNODE(mas_vfe, SDM660_MASTER_VFE, 16, 11, -1, true, NOC_QOS_MODE_BYPASS, 0, 5, SDM660_SLAVE_MNOC_BIMC);
297DEFINE_QNODE(mas_qdss_etr, SDM660_MASTER_QDSS_ETR, 8, 31, -1, true, NOC_QOS_MODE_FIXED, 1, 1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
298DEFINE_QNODE(mas_qdss_bam, SDM660_MASTER_QDSS_BAM, 4, 19, -1, true, NOC_QOS_MODE_FIXED, 1, 0, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IMEM, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_SNOC_BIMC);
299DEFINE_QNODE(mas_snoc_cfg, SDM660_MASTER_SNOC_CFG, 4, 20, -1, false, -1, 0, -1, SDM660_SLAVE_SRVC_SNOC);
300DEFINE_QNODE(mas_bimc_snoc, SDM660_MASTER_BIMC_SNOC, 8, 21, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
301DEFINE_QNODE(mas_gnoc_snoc, SDM660_MASTER_GNOC_SNOC, 8, 150, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
302DEFINE_QNODE(mas_a2noc_snoc, SDM660_MASTER_A2NOC_SNOC, 16, 112, -1, false, -1, 0, -1, SDM660_SLAVE_PIMEM, SDM660_SLAVE_IPA, SDM660_SLAVE_QDSS_STM, SDM660_SLAVE_LPASS, SDM660_SLAVE_HMSS, SDM660_SLAVE_SNOC_BIMC, SDM660_SLAVE_CDSP, SDM660_SLAVE_SNOC_CNOC, SDM660_SLAVE_WLAN, SDM660_SLAVE_IMEM);
303DEFINE_QNODE(slv_a2noc_snoc, SDM660_SLAVE_A2NOC_SNOC, 16, -1, 143, false, -1, 0, -1, SDM660_MASTER_A2NOC_SNOC);
304DEFINE_QNODE(slv_ebi, SDM660_SLAVE_EBI, 4, -1, 0, false, -1, 0, -1, 0);
305DEFINE_QNODE(slv_hmss_l3, SDM660_SLAVE_HMSS_L3, 4, -1, 160, false, -1, 0, -1, 0);
306DEFINE_QNODE(slv_bimc_snoc, SDM660_SLAVE_BIMC_SNOC, 4, -1, 2, false, -1, 0, -1, SDM660_MASTER_BIMC_SNOC);
307DEFINE_QNODE(slv_cnoc_a2noc, SDM660_SLAVE_CNOC_A2NOC, 8, -1, 208, true, -1, 0, -1, SDM660_MASTER_CNOC_A2NOC);
308DEFINE_QNODE(slv_mpm, SDM660_SLAVE_MPM, 4, -1, 62, true, -1, 0, -1, 0);
309DEFINE_QNODE(slv_pmic_arb, SDM660_SLAVE_PMIC_ARB, 4, -1, 59, true, -1, 0, -1, 0);
310DEFINE_QNODE(slv_tlmm_north, SDM660_SLAVE_TLMM_NORTH, 8, -1, 214, true, -1, 0, -1, 0);
311DEFINE_QNODE(slv_tcsr, SDM660_SLAVE_TCSR, 4, -1, 50, true, -1, 0, -1, 0);
312DEFINE_QNODE(slv_pimem_cfg, SDM660_SLAVE_PIMEM_CFG, 4, -1, 167, true, -1, 0, -1, 0);
313DEFINE_QNODE(slv_imem_cfg, SDM660_SLAVE_IMEM_CFG, 4, -1, 54, true, -1, 0, -1, 0);
314DEFINE_QNODE(slv_message_ram, SDM660_SLAVE_MESSAGE_RAM, 4, -1, 55, true, -1, 0, -1, 0);
315DEFINE_QNODE(slv_glm, SDM660_SLAVE_GLM, 4, -1, 209, true, -1, 0, -1, 0);
316DEFINE_QNODE(slv_bimc_cfg, SDM660_SLAVE_BIMC_CFG, 4, -1, 56, true, -1, 0, -1, 0);
317DEFINE_QNODE(slv_prng, SDM660_SLAVE_PRNG, 4, -1, 44, true, -1, 0, -1, 0);
318DEFINE_QNODE(slv_spdm, SDM660_SLAVE_SPDM, 4, -1, 60, true, -1, 0, -1, 0);
319DEFINE_QNODE(slv_qdss_cfg, SDM660_SLAVE_QDSS_CFG, 4, -1, 63, true, -1, 0, -1, 0);
320DEFINE_QNODE(slv_cnoc_mnoc_cfg, SDM660_SLAVE_CNOC_MNOC_CFG, 4, -1, 66, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_CFG);
321DEFINE_QNODE(slv_snoc_cfg, SDM660_SLAVE_SNOC_CFG, 4, -1, 70, true, -1, 0, -1, 0);
322DEFINE_QNODE(slv_qm_cfg, SDM660_SLAVE_QM_CFG, 4, -1, 212, true, -1, 0, -1, 0);
323DEFINE_QNODE(slv_clk_ctl, SDM660_SLAVE_CLK_CTL, 4, -1, 47, true, -1, 0, -1, 0);
324DEFINE_QNODE(slv_mss_cfg, SDM660_SLAVE_MSS_CFG, 4, -1, 48, true, -1, 0, -1, 0);
325DEFINE_QNODE(slv_tlmm_south, SDM660_SLAVE_TLMM_SOUTH, 4, -1, 217, true, -1, 0, -1, 0);
326DEFINE_QNODE(slv_ufs_cfg, SDM660_SLAVE_UFS_CFG, 4, -1, 92, true, -1, 0, -1, 0);
327DEFINE_QNODE(slv_a2noc_cfg, SDM660_SLAVE_A2NOC_CFG, 4, -1, 150, true, -1, 0, -1, 0);
328DEFINE_QNODE(slv_a2noc_smmu_cfg, SDM660_SLAVE_A2NOC_SMMU_CFG, 8, -1, 152, true, -1, 0, -1, 0);
329DEFINE_QNODE(slv_gpuss_cfg, SDM660_SLAVE_GPUSS_CFG, 8, -1, 11, true, -1, 0, -1, 0);
330DEFINE_QNODE(slv_ahb2phy, SDM660_SLAVE_AHB2PHY, 4, -1, 163, true, -1, 0, -1, 0);
331DEFINE_QNODE(slv_blsp_1, SDM660_SLAVE_BLSP_1, 4, -1, 39, true, -1, 0, -1, 0);
332DEFINE_QNODE(slv_sdcc_1, SDM660_SLAVE_SDCC_1, 4, -1, 31, true, -1, 0, -1, 0);
333DEFINE_QNODE(slv_sdcc_2, SDM660_SLAVE_SDCC_2, 4, -1, 33, true, -1, 0, -1, 0);
334DEFINE_QNODE(slv_tlmm_center, SDM660_SLAVE_TLMM_CENTER, 4, -1, 218, true, -1, 0, -1, 0);
335DEFINE_QNODE(slv_blsp_2, SDM660_SLAVE_BLSP_2, 4, -1, 37, true, -1, 0, -1, 0);
336DEFINE_QNODE(slv_pdm, SDM660_SLAVE_PDM, 4, -1, 41, true, -1, 0, -1, 0);
337DEFINE_QNODE(slv_cnoc_mnoc_mmss_cfg, SDM660_SLAVE_CNOC_MNOC_MMSS_CFG, 8, -1, 58, true, -1, 0, -1, SDM660_MASTER_CNOC_MNOC_MMSS_CFG);
338DEFINE_QNODE(slv_usb_hs, SDM660_SLAVE_USB_HS, 4, -1, 40, true, -1, 0, -1, 0);
339DEFINE_QNODE(slv_usb3_0, SDM660_SLAVE_USB3_0, 4, -1, 22, true, -1, 0, -1, 0);
340DEFINE_QNODE(slv_srvc_cnoc, SDM660_SLAVE_SRVC_CNOC, 4, -1, 76, true, -1, 0, -1, 0);
341DEFINE_QNODE(slv_gnoc_bimc, SDM660_SLAVE_GNOC_BIMC, 16, -1, 210, true, -1, 0, -1, SDM660_MASTER_GNOC_BIMC);
342DEFINE_QNODE(slv_gnoc_snoc, SDM660_SLAVE_GNOC_SNOC, 8, -1, 211, true, -1, 0, -1, SDM660_MASTER_GNOC_SNOC);
343DEFINE_QNODE(slv_camera_cfg, SDM660_SLAVE_CAMERA_CFG, 4, -1, 3, true, -1, 0, -1, 0);
344DEFINE_QNODE(slv_camera_throttle_cfg, SDM660_SLAVE_CAMERA_THROTTLE_CFG, 4, -1, 154, true, -1, 0, -1, 0);
345DEFINE_QNODE(slv_misc_cfg, SDM660_SLAVE_MISC_CFG, 4, -1, 8, true, -1, 0, -1, 0);
346DEFINE_QNODE(slv_venus_throttle_cfg, SDM660_SLAVE_VENUS_THROTTLE_CFG, 4, -1, 178, true, -1, 0, -1, 0);
347DEFINE_QNODE(slv_venus_cfg, SDM660_SLAVE_VENUS_CFG, 4, -1, 10, true, -1, 0, -1, 0);
348DEFINE_QNODE(slv_mmss_clk_xpu_cfg, SDM660_SLAVE_MMSS_CLK_XPU_CFG, 4, -1, 13, true, -1, 0, -1, 0);
349DEFINE_QNODE(slv_mmss_clk_cfg, SDM660_SLAVE_MMSS_CLK_CFG, 4, -1, 12, true, -1, 0, -1, 0);
350DEFINE_QNODE(slv_mnoc_mpu_cfg, SDM660_SLAVE_MNOC_MPU_CFG, 4, -1, 14, true, -1, 0, -1, 0);
351DEFINE_QNODE(slv_display_cfg, SDM660_SLAVE_DISPLAY_CFG, 4, -1, 4, true, -1, 0, -1, 0);
352DEFINE_QNODE(slv_csi_phy_cfg, SDM660_SLAVE_CSI_PHY_CFG, 4, -1, 224, true, -1, 0, -1, 0);
353DEFINE_QNODE(slv_display_throttle_cfg, SDM660_SLAVE_DISPLAY_THROTTLE_CFG, 4, -1, 156, true, -1, 0, -1, 0);
354DEFINE_QNODE(slv_smmu_cfg, SDM660_SLAVE_SMMU_CFG, 8, -1, 205, true, -1, 0, -1, 0);
355DEFINE_QNODE(slv_mnoc_bimc, SDM660_SLAVE_MNOC_BIMC, 16, -1, 16, true, -1, 0, -1, SDM660_MASTER_MNOC_BIMC);
356DEFINE_QNODE(slv_srvc_mnoc, SDM660_SLAVE_SRVC_MNOC, 8, -1, 17, true, -1, 0, -1, 0);
357DEFINE_QNODE(slv_hmss, SDM660_SLAVE_HMSS, 8, -1, 20, true, -1, 0, -1, 0);
358DEFINE_QNODE(slv_lpass, SDM660_SLAVE_LPASS, 4, -1, 21, true, -1, 0, -1, 0);
359DEFINE_QNODE(slv_wlan, SDM660_SLAVE_WLAN, 4, -1, 206, false, -1, 0, -1, 0);
360DEFINE_QNODE(slv_cdsp, SDM660_SLAVE_CDSP, 4, -1, 221, true, -1, 0, -1, 0);
361DEFINE_QNODE(slv_ipa, SDM660_SLAVE_IPA, 4, -1, 183, true, -1, 0, -1, 0);
362DEFINE_QNODE(slv_snoc_bimc, SDM660_SLAVE_SNOC_BIMC, 16, -1, 24, false, -1, 0, -1, SDM660_MASTER_SNOC_BIMC);
363DEFINE_QNODE(slv_snoc_cnoc, SDM660_SLAVE_SNOC_CNOC, 8, -1, 25, false, -1, 0, -1, SDM660_MASTER_SNOC_CNOC);
364DEFINE_QNODE(slv_imem, SDM660_SLAVE_IMEM, 8, -1, 26, false, -1, 0, -1, 0);
365DEFINE_QNODE(slv_pimem, SDM660_SLAVE_PIMEM, 8, -1, 166, false, -1, 0, -1, 0);
366DEFINE_QNODE(slv_qdss_stm, SDM660_SLAVE_QDSS_STM, 4, -1, 30, false, -1, 0, -1, 0);
367DEFINE_QNODE(slv_srvc_snoc, SDM660_SLAVE_SRVC_SNOC, 16, -1, 29, false, -1, 0, -1, 0);
368
369static struct qcom_icc_node *sdm660_a2noc_nodes[] = {
370 [MASTER_IPA] = &mas_ipa,
371 [MASTER_CNOC_A2NOC] = &mas_cnoc_a2noc,
372 [MASTER_SDCC_1] = &mas_sdcc_1,
373 [MASTER_SDCC_2] = &mas_sdcc_2,
374 [MASTER_BLSP_1] = &mas_blsp_1,
375 [MASTER_BLSP_2] = &mas_blsp_2,
376 [MASTER_UFS] = &mas_ufs,
377 [MASTER_USB_HS] = &mas_usb_hs,
378 [MASTER_USB3] = &mas_usb3,
379 [MASTER_CRYPTO_C0] = &mas_crypto,
380 [SLAVE_A2NOC_SNOC] = &slv_a2noc_snoc,
381};
382
383static const struct regmap_config sdm660_a2noc_regmap_config = {
384 .reg_bits = 32,
385 .reg_stride = 4,
386 .val_bits = 32,
387 .max_register = 0x20000,
388 .fast_io = true,
389};
390
391static struct qcom_icc_desc sdm660_a2noc = {
392 .nodes = sdm660_a2noc_nodes,
393 .num_nodes = ARRAY_SIZE(sdm660_a2noc_nodes),
394 .regmap_cfg = &sdm660_a2noc_regmap_config,
395};
396
397static struct qcom_icc_node *sdm660_bimc_nodes[] = {
398 [MASTER_GNOC_BIMC] = &mas_gnoc_bimc,
399 [MASTER_OXILI] = &mas_oxili,
400 [MASTER_MNOC_BIMC] = &mas_mnoc_bimc,
401 [MASTER_SNOC_BIMC] = &mas_snoc_bimc,
402 [MASTER_PIMEM] = &mas_pimem,
403 [SLAVE_EBI] = &slv_ebi,
404 [SLAVE_HMSS_L3] = &slv_hmss_l3,
405 [SLAVE_BIMC_SNOC] = &slv_bimc_snoc,
406};
407
408static const struct regmap_config sdm660_bimc_regmap_config = {
409 .reg_bits = 32,
410 .reg_stride = 4,
411 .val_bits = 32,
412 .max_register = 0x80000,
413 .fast_io = true,
414};
415
416static struct qcom_icc_desc sdm660_bimc = {
417 .nodes = sdm660_bimc_nodes,
418 .num_nodes = ARRAY_SIZE(sdm660_bimc_nodes),
419 .regmap_cfg = &sdm660_bimc_regmap_config,
420};
421
422static struct qcom_icc_node *sdm660_cnoc_nodes[] = {
423 [MASTER_SNOC_CNOC] = &mas_snoc_cnoc,
424 [MASTER_QDSS_DAP] = &mas_qdss_dap,
425 [SLAVE_CNOC_A2NOC] = &slv_cnoc_a2noc,
426 [SLAVE_MPM] = &slv_mpm,
427 [SLAVE_PMIC_ARB] = &slv_pmic_arb,
428 [SLAVE_TLMM_NORTH] = &slv_tlmm_north,
429 [SLAVE_TCSR] = &slv_tcsr,
430 [SLAVE_PIMEM_CFG] = &slv_pimem_cfg,
431 [SLAVE_IMEM_CFG] = &slv_imem_cfg,
432 [SLAVE_MESSAGE_RAM] = &slv_message_ram,
433 [SLAVE_GLM] = &slv_glm,
434 [SLAVE_BIMC_CFG] = &slv_bimc_cfg,
435 [SLAVE_PRNG] = &slv_prng,
436 [SLAVE_SPDM] = &slv_spdm,
437 [SLAVE_QDSS_CFG] = &slv_qdss_cfg,
438 [SLAVE_CNOC_MNOC_CFG] = &slv_cnoc_mnoc_cfg,
439 [SLAVE_SNOC_CFG] = &slv_snoc_cfg,
440 [SLAVE_QM_CFG] = &slv_qm_cfg,
441 [SLAVE_CLK_CTL] = &slv_clk_ctl,
442 [SLAVE_MSS_CFG] = &slv_mss_cfg,
443 [SLAVE_TLMM_SOUTH] = &slv_tlmm_south,
444 [SLAVE_UFS_CFG] = &slv_ufs_cfg,
445 [SLAVE_A2NOC_CFG] = &slv_a2noc_cfg,
446 [SLAVE_A2NOC_SMMU_CFG] = &slv_a2noc_smmu_cfg,
447 [SLAVE_GPUSS_CFG] = &slv_gpuss_cfg,
448 [SLAVE_AHB2PHY] = &slv_ahb2phy,
449 [SLAVE_BLSP_1] = &slv_blsp_1,
450 [SLAVE_SDCC_1] = &slv_sdcc_1,
451 [SLAVE_SDCC_2] = &slv_sdcc_2,
452 [SLAVE_TLMM_CENTER] = &slv_tlmm_center,
453 [SLAVE_BLSP_2] = &slv_blsp_2,
454 [SLAVE_PDM] = &slv_pdm,
455 [SLAVE_CNOC_MNOC_MMSS_CFG] = &slv_cnoc_mnoc_mmss_cfg,
456 [SLAVE_USB_HS] = &slv_usb_hs,
457 [SLAVE_USB3_0] = &slv_usb3_0,
458 [SLAVE_SRVC_CNOC] = &slv_srvc_cnoc,
459};
460
461static const struct regmap_config sdm660_cnoc_regmap_config = {
462 .reg_bits = 32,
463 .reg_stride = 4,
464 .val_bits = 32,
465 .max_register = 0x10000,
466 .fast_io = true,
467};
468
469static struct qcom_icc_desc sdm660_cnoc = {
470 .nodes = sdm660_cnoc_nodes,
471 .num_nodes = ARRAY_SIZE(sdm660_cnoc_nodes),
472 .regmap_cfg = &sdm660_cnoc_regmap_config,
473};
474
475static struct qcom_icc_node *sdm660_gnoc_nodes[] = {
476 [MASTER_APSS_PROC] = &mas_apss_proc,
477 [SLAVE_GNOC_BIMC] = &slv_gnoc_bimc,
478 [SLAVE_GNOC_SNOC] = &slv_gnoc_snoc,
479};
480
481static const struct regmap_config sdm660_gnoc_regmap_config = {
482 .reg_bits = 32,
483 .reg_stride = 4,
484 .val_bits = 32,
485 .max_register = 0xe000,
486 .fast_io = true,
487};
488
489static struct qcom_icc_desc sdm660_gnoc = {
490 .nodes = sdm660_gnoc_nodes,
491 .num_nodes = ARRAY_SIZE(sdm660_gnoc_nodes),
492 .regmap_cfg = &sdm660_gnoc_regmap_config,
493};
494
495static struct qcom_icc_node *sdm660_mnoc_nodes[] = {
496 [MASTER_CPP] = &mas_cpp,
497 [MASTER_JPEG] = &mas_jpeg,
498 [MASTER_MDP_P0] = &mas_mdp_p0,
499 [MASTER_MDP_P1] = &mas_mdp_p1,
500 [MASTER_VENUS] = &mas_venus,
501 [MASTER_VFE] = &mas_vfe,
502 [MASTER_CNOC_MNOC_MMSS_CFG] = &mas_cnoc_mnoc_mmss_cfg,
503 [MASTER_CNOC_MNOC_CFG] = &mas_cnoc_mnoc_cfg,
504 [SLAVE_CAMERA_CFG] = &slv_camera_cfg,
505 [SLAVE_CAMERA_THROTTLE_CFG] = &slv_camera_throttle_cfg,
506 [SLAVE_MISC_CFG] = &slv_misc_cfg,
507 [SLAVE_VENUS_THROTTLE_CFG] = &slv_venus_throttle_cfg,
508 [SLAVE_VENUS_CFG] = &slv_venus_cfg,
509 [SLAVE_MMSS_CLK_XPU_CFG] = &slv_mmss_clk_xpu_cfg,
510 [SLAVE_MMSS_CLK_CFG] = &slv_mmss_clk_cfg,
511 [SLAVE_MNOC_MPU_CFG] = &slv_mnoc_mpu_cfg,
512 [SLAVE_DISPLAY_CFG] = &slv_display_cfg,
513 [SLAVE_CSI_PHY_CFG] = &slv_csi_phy_cfg,
514 [SLAVE_DISPLAY_THROTTLE_CFG] = &slv_display_throttle_cfg,
515 [SLAVE_SMMU_CFG] = &slv_smmu_cfg,
516 [SLAVE_SRVC_MNOC] = &slv_srvc_mnoc,
517 [SLAVE_MNOC_BIMC] = &slv_mnoc_bimc,
518};
519
520static const struct regmap_config sdm660_mnoc_regmap_config = {
521 .reg_bits = 32,
522 .reg_stride = 4,
523 .val_bits = 32,
524 .max_register = 0x10000,
525 .fast_io = true,
526};
527
528static struct qcom_icc_desc sdm660_mnoc = {
529 .nodes = sdm660_mnoc_nodes,
530 .num_nodes = ARRAY_SIZE(sdm660_mnoc_nodes),
531 .regmap_cfg = &sdm660_mnoc_regmap_config,
532};
533
534static struct qcom_icc_node *sdm660_snoc_nodes[] = {
535 [MASTER_QDSS_ETR] = &mas_qdss_etr,
536 [MASTER_QDSS_BAM] = &mas_qdss_bam,
537 [MASTER_SNOC_CFG] = &mas_snoc_cfg,
538 [MASTER_BIMC_SNOC] = &mas_bimc_snoc,
539 [MASTER_A2NOC_SNOC] = &mas_a2noc_snoc,
540 [MASTER_GNOC_SNOC] = &mas_gnoc_snoc,
541 [SLAVE_HMSS] = &slv_hmss,
542 [SLAVE_LPASS] = &slv_lpass,
543 [SLAVE_WLAN] = &slv_wlan,
544 [SLAVE_CDSP] = &slv_cdsp,
545 [SLAVE_IPA] = &slv_ipa,
546 [SLAVE_SNOC_BIMC] = &slv_snoc_bimc,
547 [SLAVE_SNOC_CNOC] = &slv_snoc_cnoc,
548 [SLAVE_IMEM] = &slv_imem,
549 [SLAVE_PIMEM] = &slv_pimem,
550 [SLAVE_QDSS_STM] = &slv_qdss_stm,
551 [SLAVE_SRVC_SNOC] = &slv_srvc_snoc,
552};
553
554static const struct regmap_config sdm660_snoc_regmap_config = {
555 .reg_bits = 32,
556 .reg_stride = 4,
557 .val_bits = 32,
558 .max_register = 0x20000,
559 .fast_io = true,
560};
561
562static struct qcom_icc_desc sdm660_snoc = {
563 .nodes = sdm660_snoc_nodes,
564 .num_nodes = ARRAY_SIZE(sdm660_snoc_nodes),
565 .regmap_cfg = &sdm660_snoc_regmap_config,
566};
567
568static int qcom_icc_bimc_set_qos_health(struct regmap *rmap,
569 struct qcom_icc_qos *qos,
570 int regnum)
571{
572 u32 val;
573 u32 mask;
574
575 val = qos->prio_level;
576 mask = M_BKE_HEALTH_CFG_PRIOLVL_MASK;
577
578 val |= qos->areq_prio << M_BKE_HEALTH_CFG_AREQPRIO_SHIFT;
579 mask |= M_BKE_HEALTH_CFG_AREQPRIO_MASK;
580
581
582 if (regnum != 3) {
583 val |= qos->limit_commands << M_BKE_HEALTH_CFG_LIMITCMDS_SHIFT;
584 mask |= M_BKE_HEALTH_CFG_LIMITCMDS_MASK;
585 }
586
587 return regmap_update_bits(rmap,
588 M_BKE_HEALTH_CFG_ADDR(regnum, qos->qos_port),
589 mask, val);
590}
591
592static int qcom_icc_set_bimc_qos(struct icc_node *src, u64 max_bw,
593 bool bypass_mode)
594{
595 struct qcom_icc_provider *qp;
596 struct qcom_icc_node *qn;
597 struct icc_provider *provider;
598 u32 mode = NOC_QOS_MODE_BYPASS;
599 u32 val = 0;
600 int i, rc = 0;
601
602 qn = src->data;
603 provider = src->provider;
604 qp = to_qcom_provider(provider);
605
606 if (qn->qos.qos_mode != -1)
607 mode = qn->qos.qos_mode;
608
609
610
611
612 if (mode != NOC_QOS_MODE_BYPASS) {
613 for (i = 3; i >= 0; i--) {
614 rc = qcom_icc_bimc_set_qos_health(qp->regmap,
615 &qn->qos, i);
616 if (rc)
617 return rc;
618 }
619
620
621 val = 1;
622 }
623
624 return regmap_update_bits(qp->regmap, M_BKE_EN_ADDR(qn->qos.qos_port),
625 M_BKE_EN_EN_BMASK, val);
626}
627
628static int qcom_icc_noc_set_qos_priority(struct regmap *rmap,
629 struct qcom_icc_qos *qos)
630{
631 u32 val;
632 int rc;
633
634
635 val = qos->areq_prio << NOC_QOS_PRIORITY_P1_SHIFT;
636 rc = regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
637 NOC_QOS_PRIORITY_P1_MASK, val);
638 if (rc)
639 return rc;
640
641 return regmap_update_bits(rmap, NOC_QOS_PRIORITYn_ADDR(qos->qos_port),
642 NOC_QOS_PRIORITY_P0_MASK, qos->prio_level);
643}
644
645static int qcom_icc_set_noc_qos(struct icc_node *src, u64 max_bw)
646{
647 struct qcom_icc_provider *qp;
648 struct qcom_icc_node *qn;
649 struct icc_provider *provider;
650 u32 mode = NOC_QOS_MODE_BYPASS;
651 int rc = 0;
652
653 qn = src->data;
654 provider = src->provider;
655 qp = to_qcom_provider(provider);
656
657 if (qn->qos.qos_port < 0) {
658 dev_dbg(src->provider->dev,
659 "NoC QoS: Skipping %s: vote aggregated on parent.\n",
660 qn->name);
661 return 0;
662 }
663
664 if (qn->qos.qos_mode != -1)
665 mode = qn->qos.qos_mode;
666
667 if (mode == NOC_QOS_MODE_FIXED) {
668 dev_dbg(src->provider->dev, "NoC QoS: %s: Set Fixed mode\n",
669 qn->name);
670 rc = qcom_icc_noc_set_qos_priority(qp->regmap, &qn->qos);
671 if (rc)
672 return rc;
673 } else if (mode == NOC_QOS_MODE_BYPASS) {
674 dev_dbg(src->provider->dev, "NoC QoS: %s: Set Bypass mode\n",
675 qn->name);
676 }
677
678 return regmap_update_bits(qp->regmap,
679 NOC_QOS_MODEn_ADDR(qn->qos.qos_port),
680 NOC_QOS_MODEn_MASK, mode);
681}
682
683static int qcom_icc_qos_set(struct icc_node *node, u64 sum_bw)
684{
685 struct qcom_icc_provider *qp = to_qcom_provider(node->provider);
686 struct qcom_icc_node *qn = node->data;
687
688 dev_dbg(node->provider->dev, "Setting QoS for %s\n", qn->name);
689
690 if (qp->is_bimc_node)
691 return qcom_icc_set_bimc_qos(node, sum_bw,
692 (qn->qos.qos_mode == NOC_QOS_MODE_BYPASS));
693
694 return qcom_icc_set_noc_qos(node, sum_bw);
695}
696
697static int qcom_icc_rpm_set(int mas_rpm_id, int slv_rpm_id, u64 sum_bw)
698{
699 int ret = 0;
700
701 if (mas_rpm_id != -1) {
702 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
703 RPM_BUS_MASTER_REQ,
704 mas_rpm_id,
705 sum_bw);
706 if (ret) {
707 pr_err("qcom_icc_rpm_smd_send mas %d error %d\n",
708 mas_rpm_id, ret);
709 return ret;
710 }
711 }
712
713 if (slv_rpm_id != -1) {
714 ret = qcom_icc_rpm_smd_send(QCOM_SMD_RPM_ACTIVE_STATE,
715 RPM_BUS_SLAVE_REQ,
716 slv_rpm_id,
717 sum_bw);
718 if (ret) {
719 pr_err("qcom_icc_rpm_smd_send slv %d error %d\n",
720 slv_rpm_id, ret);
721 return ret;
722 }
723 }
724
725 return ret;
726}
727
728static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
729{
730 struct qcom_icc_provider *qp;
731 struct qcom_icc_node *qn;
732 struct icc_provider *provider;
733 struct icc_node *n;
734 u64 sum_bw;
735 u64 max_peak_bw;
736 u64 rate;
737 u32 agg_avg = 0;
738 u32 agg_peak = 0;
739 int ret, i;
740
741 qn = src->data;
742 provider = src->provider;
743 qp = to_qcom_provider(provider);
744
745 list_for_each_entry(n, &provider->nodes, node_list)
746 provider->aggregate(n, 0, n->avg_bw, n->peak_bw,
747 &agg_avg, &agg_peak);
748
749 sum_bw = icc_units_to_bps(agg_avg);
750 max_peak_bw = icc_units_to_bps(agg_peak);
751
752 if (!qn->qos.ap_owned) {
753
754 ret = qcom_icc_rpm_set(qn->mas_rpm_id, qn->slv_rpm_id, sum_bw);
755 if (ret)
756 return ret;
757 } else if (qn->qos.qos_mode != -1) {
758
759 ret = qcom_icc_qos_set(src, sum_bw);
760 if (ret)
761 return ret;
762 }
763
764 rate = max(sum_bw, max_peak_bw);
765
766 do_div(rate, qn->buswidth);
767
768 if (qn->rate == rate)
769 return 0;
770
771 for (i = 0; i < qp->num_clks; i++) {
772 ret = clk_set_rate(qp->bus_clks[i].clk, rate);
773 if (ret) {
774 pr_err("%s clk_set_rate error: %d\n",
775 qp->bus_clks[i].id, ret);
776 return ret;
777 }
778 }
779
780 qn->rate = rate;
781
782 return 0;
783}
784
785static int qnoc_probe(struct platform_device *pdev)
786{
787 struct device *dev = &pdev->dev;
788 const struct qcom_icc_desc *desc;
789 struct icc_onecell_data *data;
790 struct icc_provider *provider;
791 struct qcom_icc_node **qnodes;
792 struct qcom_icc_provider *qp;
793 struct icc_node *node;
794 struct resource *res;
795 size_t num_nodes, i;
796 int ret;
797
798
799 if (!qcom_icc_rpm_smd_available())
800 return -EPROBE_DEFER;
801
802 desc = of_device_get_match_data(dev);
803 if (!desc)
804 return -EINVAL;
805
806 qnodes = desc->nodes;
807 num_nodes = desc->num_nodes;
808
809 qp = devm_kzalloc(dev, sizeof(*qp), GFP_KERNEL);
810 if (!qp)
811 return -ENOMEM;
812
813 data = devm_kzalloc(dev, struct_size(data, nodes, num_nodes),
814 GFP_KERNEL);
815 if (!data)
816 return -ENOMEM;
817
818 if (of_device_is_compatible(dev->of_node, "qcom,sdm660-mnoc")) {
819 qp->bus_clks = devm_kmemdup(dev, bus_mm_clocks,
820 sizeof(bus_mm_clocks), GFP_KERNEL);
821 qp->num_clks = ARRAY_SIZE(bus_mm_clocks);
822 } else if (of_device_is_compatible(dev->of_node, "qcom,sdm660-a2noc")) {
823 qp->bus_clks = devm_kmemdup(dev, bus_a2noc_clocks,
824 sizeof(bus_a2noc_clocks), GFP_KERNEL);
825 qp->num_clks = ARRAY_SIZE(bus_a2noc_clocks);
826 } else {
827 if (of_device_is_compatible(dev->of_node, "qcom,sdm660-bimc"))
828 qp->is_bimc_node = true;
829
830 qp->bus_clks = devm_kmemdup(dev, bus_clocks, sizeof(bus_clocks),
831 GFP_KERNEL);
832 qp->num_clks = ARRAY_SIZE(bus_clocks);
833 }
834 if (!qp->bus_clks)
835 return -ENOMEM;
836
837 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
838 if (!res)
839 return -ENODEV;
840
841 qp->mmio = devm_ioremap_resource(dev, res);
842 if (IS_ERR(qp->mmio)) {
843 dev_err(dev, "Cannot ioremap interconnect bus resource\n");
844 return PTR_ERR(qp->mmio);
845 }
846
847 qp->regmap = devm_regmap_init_mmio(dev, qp->mmio, desc->regmap_cfg);
848 if (IS_ERR(qp->regmap)) {
849 dev_err(dev, "Cannot regmap interconnect bus resource\n");
850 return PTR_ERR(qp->regmap);
851 }
852
853 ret = devm_clk_bulk_get(dev, qp->num_clks, qp->bus_clks);
854 if (ret)
855 return ret;
856
857 ret = clk_bulk_prepare_enable(qp->num_clks, qp->bus_clks);
858 if (ret)
859 return ret;
860
861 provider = &qp->provider;
862 INIT_LIST_HEAD(&provider->nodes);
863 provider->dev = dev;
864 provider->set = qcom_icc_set;
865 provider->aggregate = icc_std_aggregate;
866 provider->xlate = of_icc_xlate_onecell;
867 provider->data = data;
868
869 ret = icc_provider_add(provider);
870 if (ret) {
871 dev_err(dev, "error adding interconnect provider: %d\n", ret);
872 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
873 return ret;
874 }
875
876 for (i = 0; i < num_nodes; i++) {
877 size_t j;
878
879 node = icc_node_create(qnodes[i]->id);
880 if (IS_ERR(node)) {
881 ret = PTR_ERR(node);
882 goto err;
883 }
884
885 node->name = qnodes[i]->name;
886 node->data = qnodes[i];
887 icc_node_add(node, provider);
888
889 for (j = 0; j < qnodes[i]->num_links; j++)
890 icc_link_create(node, qnodes[i]->links[j]);
891
892 data->nodes[i] = node;
893 }
894 data->num_nodes = num_nodes;
895 platform_set_drvdata(pdev, qp);
896
897 return 0;
898err:
899 icc_nodes_remove(provider);
900 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
901 icc_provider_del(provider);
902
903 return ret;
904}
905
906static int qnoc_remove(struct platform_device *pdev)
907{
908 struct qcom_icc_provider *qp = platform_get_drvdata(pdev);
909
910 icc_nodes_remove(&qp->provider);
911 clk_bulk_disable_unprepare(qp->num_clks, qp->bus_clks);
912 return icc_provider_del(&qp->provider);
913}
914
915static const struct of_device_id sdm660_noc_of_match[] = {
916 { .compatible = "qcom,sdm660-a2noc", .data = &sdm660_a2noc },
917 { .compatible = "qcom,sdm660-bimc", .data = &sdm660_bimc },
918 { .compatible = "qcom,sdm660-cnoc", .data = &sdm660_cnoc },
919 { .compatible = "qcom,sdm660-gnoc", .data = &sdm660_gnoc },
920 { .compatible = "qcom,sdm660-mnoc", .data = &sdm660_mnoc },
921 { .compatible = "qcom,sdm660-snoc", .data = &sdm660_snoc },
922 { },
923};
924MODULE_DEVICE_TABLE(of, sdm660_noc_of_match);
925
926static struct platform_driver sdm660_noc_driver = {
927 .probe = qnoc_probe,
928 .remove = qnoc_remove,
929 .driver = {
930 .name = "qnoc-sdm660",
931 .of_match_table = sdm660_noc_of_match,
932 },
933};
934module_platform_driver(sdm660_noc_driver);
935MODULE_DESCRIPTION("Qualcomm sdm660 NoC driver");
936MODULE_LICENSE("GPL v2");
937
