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10#include <linux/device.h>
11#include <linux/interconnect.h>
12#include <linux/interconnect-provider.h>
13#include <linux/module.h>
14#include <linux/of_platform.h>
15#include <dt-bindings/interconnect/qcom,sdx55.h>
16
17#include "bcm-voter.h"
18#include "icc-rpmh.h"
19#include "sdx55.h"
20
21DEFINE_QNODE(ipa_core_master, SDX55_MASTER_IPA_CORE, 1, 8, SDX55_SLAVE_IPA_CORE);
22DEFINE_QNODE(llcc_mc, SDX55_MASTER_LLCC, 4, 4, SDX55_SLAVE_EBI_CH0);
23DEFINE_QNODE(acm_tcu, SDX55_MASTER_TCU_0, 1, 8, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
24DEFINE_QNODE(qnm_snoc_gc, SDX55_MASTER_SNOC_GC_MEM_NOC, 1, 8, SDX55_SLAVE_LLCC);
25DEFINE_QNODE(xm_apps_rdwr, SDX55_MASTER_AMPSS_M0, 1, 16, SDX55_SLAVE_LLCC, SDX55_SLAVE_MEM_NOC_SNOC, SDX55_SLAVE_MEM_NOC_PCIE_SNOC);
26DEFINE_QNODE(qhm_audio, SDX55_MASTER_AUDIO, 1, 4, SDX55_SLAVE_ANOC_SNOC);
27DEFINE_QNODE(qhm_blsp1, SDX55_MASTER_BLSP_1, 1, 4, SDX55_SLAVE_ANOC_SNOC);
28DEFINE_QNODE(qhm_qdss_bam, SDX55_MASTER_QDSS_BAM, 1, 4, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
29DEFINE_QNODE(qhm_qpic, SDX55_MASTER_QPIC, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
30DEFINE_QNODE(qhm_snoc_cfg, SDX55_MASTER_SNOC_CFG, 1, 4, SDX55_SLAVE_SERVICE_SNOC);
31DEFINE_QNODE(qhm_spmi_fetcher1, SDX55_MASTER_SPMI_FETCHER, 1, 4, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP);
32DEFINE_QNODE(qnm_aggre_noc, SDX55_MASTER_ANOC_SNOC, 1, 8, SDX55_SLAVE_PCIE_0, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_USB3, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
33DEFINE_QNODE(qnm_ipa, SDX55_MASTER_IPA, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_TLMM, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
34DEFINE_QNODE(qnm_memnoc, SDX55_MASTER_MEM_NOC_SNOC, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_TLMM, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QDSS_STM, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_APPSS, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
35DEFINE_QNODE(qnm_memnoc_pcie, SDX55_MASTER_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_SLAVE_PCIE_0);
36DEFINE_QNODE(qxm_crypto, SDX55_MASTER_CRYPTO_CORE_0, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP);
37DEFINE_QNODE(xm_emac, SDX55_MASTER_EMAC, 1, 8, SDX55_SLAVE_ANOC_SNOC);
38DEFINE_QNODE(xm_ipa2pcie_slv, SDX55_MASTER_IPA_PCIE, 1, 8, SDX55_SLAVE_PCIE_0);
39DEFINE_QNODE(xm_pcie, SDX55_MASTER_PCIE, 1, 8, SDX55_SLAVE_ANOC_SNOC);
40DEFINE_QNODE(xm_qdss_etr, SDX55_MASTER_QDSS_ETR, 1, 8, SDX55_SLAVE_SNOC_CFG, SDX55_SLAVE_EMAC_CFG, SDX55_SLAVE_USB3, SDX55_SLAVE_AOSS, SDX55_SLAVE_SPMI_FETCHER, SDX55_SLAVE_QDSS_CFG, SDX55_SLAVE_PDM, SDX55_SLAVE_SNOC_MEM_NOC_GC, SDX55_SLAVE_TCSR, SDX55_SLAVE_CNOC_DDRSS, SDX55_SLAVE_SPMI_VGI_COEX, SDX55_SLAVE_QPIC, SDX55_SLAVE_OCIMEM, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_USB3_PHY_CFG, SDX55_SLAVE_AOP, SDX55_SLAVE_BLSP_1, SDX55_SLAVE_SDCC_1, SDX55_SLAVE_CNOC_MSS, SDX55_SLAVE_PCIE_PARF, SDX55_SLAVE_ECC_CFG, SDX55_SLAVE_AUDIO, SDX55_SLAVE_AOSS, SDX55_SLAVE_PRNG, SDX55_SLAVE_CRYPTO_0_CFG, SDX55_SLAVE_TCU, SDX55_SLAVE_CLK_CTL, SDX55_SLAVE_IMEM_CFG);
41DEFINE_QNODE(xm_sdc1, SDX55_MASTER_SDCC_1, 1, 8, SDX55_SLAVE_AOSS, SDX55_SLAVE_IPA_CFG, SDX55_SLAVE_ANOC_SNOC, SDX55_SLAVE_AOP, SDX55_SLAVE_AUDIO);
42DEFINE_QNODE(xm_usb3, SDX55_MASTER_USB3, 1, 8, SDX55_SLAVE_ANOC_SNOC);
43DEFINE_QNODE(ipa_core_slave, SDX55_SLAVE_IPA_CORE, 1, 8);
44DEFINE_QNODE(ebi, SDX55_SLAVE_EBI_CH0, 1, 4);
45DEFINE_QNODE(qns_llcc, SDX55_SLAVE_LLCC, 1, 16, SDX55_SLAVE_EBI_CH0);
46DEFINE_QNODE(qns_memnoc_snoc, SDX55_SLAVE_MEM_NOC_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_SNOC);
47DEFINE_QNODE(qns_sys_pcie, SDX55_SLAVE_MEM_NOC_PCIE_SNOC, 1, 8, SDX55_MASTER_MEM_NOC_PCIE_SNOC);
48DEFINE_QNODE(qhs_aop, SDX55_SLAVE_AOP, 1, 4);
49DEFINE_QNODE(qhs_aoss, SDX55_SLAVE_AOSS, 1, 4);
50DEFINE_QNODE(qhs_apss, SDX55_SLAVE_APPSS, 1, 4);
51DEFINE_QNODE(qhs_audio, SDX55_SLAVE_AUDIO, 1, 4);
52DEFINE_QNODE(qhs_blsp1, SDX55_SLAVE_BLSP_1, 1, 4);
53DEFINE_QNODE(qhs_clk_ctl, SDX55_SLAVE_CLK_CTL, 1, 4);
54DEFINE_QNODE(qhs_crypto0_cfg, SDX55_SLAVE_CRYPTO_0_CFG, 1, 4);
55DEFINE_QNODE(qhs_ddrss_cfg, SDX55_SLAVE_CNOC_DDRSS, 1, 4);
56DEFINE_QNODE(qhs_ecc_cfg, SDX55_SLAVE_ECC_CFG, 1, 4);
57DEFINE_QNODE(qhs_emac_cfg, SDX55_SLAVE_EMAC_CFG, 1, 4);
58DEFINE_QNODE(qhs_imem_cfg, SDX55_SLAVE_IMEM_CFG, 1, 4);
59DEFINE_QNODE(qhs_ipa, SDX55_SLAVE_IPA_CFG, 1, 4);
60DEFINE_QNODE(qhs_mss_cfg, SDX55_SLAVE_CNOC_MSS, 1, 4);
61DEFINE_QNODE(qhs_pcie_parf, SDX55_SLAVE_PCIE_PARF, 1, 4);
62DEFINE_QNODE(qhs_pdm, SDX55_SLAVE_PDM, 1, 4);
63DEFINE_QNODE(qhs_prng, SDX55_SLAVE_PRNG, 1, 4);
64DEFINE_QNODE(qhs_qdss_cfg, SDX55_SLAVE_QDSS_CFG, 1, 4);
65DEFINE_QNODE(qhs_qpic, SDX55_SLAVE_QPIC, 1, 4);
66DEFINE_QNODE(qhs_sdc1, SDX55_SLAVE_SDCC_1, 1, 4);
67DEFINE_QNODE(qhs_snoc_cfg, SDX55_SLAVE_SNOC_CFG, 1, 4, SDX55_MASTER_SNOC_CFG);
68DEFINE_QNODE(qhs_spmi_fetcher, SDX55_SLAVE_SPMI_FETCHER, 1, 4);
69DEFINE_QNODE(qhs_spmi_vgi_coex, SDX55_SLAVE_SPMI_VGI_COEX, 1, 4);
70DEFINE_QNODE(qhs_tcsr, SDX55_SLAVE_TCSR, 1, 4);
71DEFINE_QNODE(qhs_tlmm, SDX55_SLAVE_TLMM, 1, 4);
72DEFINE_QNODE(qhs_usb3, SDX55_SLAVE_USB3, 1, 4);
73DEFINE_QNODE(qhs_usb3_phy, SDX55_SLAVE_USB3_PHY_CFG, 1, 4);
74DEFINE_QNODE(qns_aggre_noc, SDX55_SLAVE_ANOC_SNOC, 1, 8, SDX55_MASTER_ANOC_SNOC);
75DEFINE_QNODE(qns_snoc_memnoc, SDX55_SLAVE_SNOC_MEM_NOC_GC, 1, 8, SDX55_MASTER_SNOC_GC_MEM_NOC);
76DEFINE_QNODE(qxs_imem, SDX55_SLAVE_OCIMEM, 1, 8);
77DEFINE_QNODE(srvc_snoc, SDX55_SLAVE_SERVICE_SNOC, 1, 4);
78DEFINE_QNODE(xs_pcie, SDX55_SLAVE_PCIE_0, 1, 8);
79DEFINE_QNODE(xs_qdss_stm, SDX55_SLAVE_QDSS_STM, 1, 4);
80DEFINE_QNODE(xs_sys_tcu_cfg, SDX55_SLAVE_TCU, 1, 8);
81
82DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
83DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
84DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
85DEFINE_QBCM(bcm_ip0, "IP0", false, &ipa_core_slave);
86DEFINE_QBCM(bcm_pn0, "PN0", false, &qhm_snoc_cfg);
87DEFINE_QBCM(bcm_sh3, "SH3", false, &xm_apps_rdwr);
88DEFINE_QBCM(bcm_sh4, "SH4", false, &qns_memnoc_snoc, &qns_sys_pcie);
89DEFINE_QBCM(bcm_sn0, "SN0", true, &qns_snoc_memnoc);
90DEFINE_QBCM(bcm_sn1, "SN1", false, &qxs_imem);
91DEFINE_QBCM(bcm_pn1, "PN1", false, &xm_sdc1);
92DEFINE_QBCM(bcm_pn2, "PN2", false, &qhm_audio, &qhm_spmi_fetcher1);
93DEFINE_QBCM(bcm_sn3, "SN3", false, &xs_qdss_stm);
94DEFINE_QBCM(bcm_pn3, "PN3", false, &qhm_blsp1, &qhm_qpic);
95DEFINE_QBCM(bcm_sn4, "SN4", false, &xs_sys_tcu_cfg);
96DEFINE_QBCM(bcm_pn5, "PN5", false, &qxm_crypto);
97DEFINE_QBCM(bcm_sn6, "SN6", false, &xs_pcie);
98DEFINE_QBCM(bcm_sn7, "SN7", false, &qnm_aggre_noc, &xm_emac, &xm_emac, &xm_usb3,
99 &qns_aggre_noc);
100DEFINE_QBCM(bcm_sn8, "SN8", false, &qhm_qdss_bam, &xm_qdss_etr);
101DEFINE_QBCM(bcm_sn9, "SN9", false, &qnm_memnoc);
102DEFINE_QBCM(bcm_sn10, "SN10", false, &qnm_memnoc_pcie);
103DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_ipa, &xm_ipa2pcie_slv);
104
105static struct qcom_icc_bcm *mc_virt_bcms[] = {
106 &bcm_mc0,
107};
108
109static struct qcom_icc_node *mc_virt_nodes[] = {
110 [MASTER_LLCC] = &llcc_mc,
111 [SLAVE_EBI_CH0] = &ebi,
112};
113
114static const struct qcom_icc_desc sdx55_mc_virt = {
115 .nodes = mc_virt_nodes,
116 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
117 .bcms = mc_virt_bcms,
118 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
119};
120
121static struct qcom_icc_bcm *mem_noc_bcms[] = {
122 &bcm_sh0,
123 &bcm_sh3,
124 &bcm_sh4,
125};
126
127static struct qcom_icc_node *mem_noc_nodes[] = {
128 [MASTER_TCU_0] = &acm_tcu,
129 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
130 [MASTER_AMPSS_M0] = &xm_apps_rdwr,
131 [SLAVE_LLCC] = &qns_llcc,
132 [SLAVE_MEM_NOC_SNOC] = &qns_memnoc_snoc,
133 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_sys_pcie,
134};
135
136static const struct qcom_icc_desc sdx55_mem_noc = {
137 .nodes = mem_noc_nodes,
138 .num_nodes = ARRAY_SIZE(mem_noc_nodes),
139 .bcms = mem_noc_bcms,
140 .num_bcms = ARRAY_SIZE(mem_noc_bcms),
141};
142
143static struct qcom_icc_bcm *system_noc_bcms[] = {
144 &bcm_ce0,
145 &bcm_pn0,
146 &bcm_pn1,
147 &bcm_pn2,
148 &bcm_pn3,
149 &bcm_pn5,
150 &bcm_sn0,
151 &bcm_sn1,
152 &bcm_sn3,
153 &bcm_sn4,
154 &bcm_sn6,
155 &bcm_sn7,
156 &bcm_sn8,
157 &bcm_sn9,
158 &bcm_sn10,
159 &bcm_sn11,
160};
161
162static struct qcom_icc_node *system_noc_nodes[] = {
163 [MASTER_AUDIO] = &qhm_audio,
164 [MASTER_BLSP_1] = &qhm_blsp1,
165 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
166 [MASTER_QPIC] = &qhm_qpic,
167 [MASTER_SNOC_CFG] = &qhm_snoc_cfg,
168 [MASTER_SPMI_FETCHER] = &qhm_spmi_fetcher1,
169 [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
170 [MASTER_IPA] = &qnm_ipa,
171 [MASTER_MEM_NOC_SNOC] = &qnm_memnoc,
172 [MASTER_MEM_NOC_PCIE_SNOC] = &qnm_memnoc_pcie,
173 [MASTER_CRYPTO_CORE_0] = &qxm_crypto,
174 [MASTER_EMAC] = &xm_emac,
175 [MASTER_IPA_PCIE] = &xm_ipa2pcie_slv,
176 [MASTER_PCIE] = &xm_pcie,
177 [MASTER_QDSS_ETR] = &xm_qdss_etr,
178 [MASTER_SDCC_1] = &xm_sdc1,
179 [MASTER_USB3] = &xm_usb3,
180 [SLAVE_AOP] = &qhs_aop,
181 [SLAVE_AOSS] = &qhs_aoss,
182 [SLAVE_APPSS] = &qhs_apss,
183 [SLAVE_AUDIO] = &qhs_audio,
184 [SLAVE_BLSP_1] = &qhs_blsp1,
185 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
186 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
187 [SLAVE_CNOC_DDRSS] = &qhs_ddrss_cfg,
188 [SLAVE_ECC_CFG] = &qhs_ecc_cfg,
189 [SLAVE_EMAC_CFG] = &qhs_emac_cfg,
190 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
191 [SLAVE_IPA_CFG] = &qhs_ipa,
192 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
193 [SLAVE_PCIE_PARF] = &qhs_pcie_parf,
194 [SLAVE_PDM] = &qhs_pdm,
195 [SLAVE_PRNG] = &qhs_prng,
196 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
197 [SLAVE_QPIC] = &qhs_qpic,
198 [SLAVE_SDCC_1] = &qhs_sdc1,
199 [SLAVE_SNOC_CFG] = &qhs_snoc_cfg,
200 [SLAVE_SPMI_FETCHER] = &qhs_spmi_fetcher,
201 [SLAVE_SPMI_VGI_COEX] = &qhs_spmi_vgi_coex,
202 [SLAVE_TCSR] = &qhs_tcsr,
203 [SLAVE_TLMM] = &qhs_tlmm,
204 [SLAVE_USB3] = &qhs_usb3,
205 [SLAVE_USB3_PHY_CFG] = &qhs_usb3_phy,
206 [SLAVE_ANOC_SNOC] = &qns_aggre_noc,
207 [SLAVE_SNOC_MEM_NOC_GC] = &qns_snoc_memnoc,
208 [SLAVE_OCIMEM] = &qxs_imem,
209 [SLAVE_SERVICE_SNOC] = &srvc_snoc,
210 [SLAVE_PCIE_0] = &xs_pcie,
211 [SLAVE_QDSS_STM] = &xs_qdss_stm,
212 [SLAVE_TCU] = &xs_sys_tcu_cfg,
213};
214
215static const struct qcom_icc_desc sdx55_system_noc = {
216 .nodes = system_noc_nodes,
217 .num_nodes = ARRAY_SIZE(system_noc_nodes),
218 .bcms = system_noc_bcms,
219 .num_bcms = ARRAY_SIZE(system_noc_bcms),
220};
221
222static struct qcom_icc_bcm *ipa_virt_bcms[] = {
223 &bcm_ip0,
224};
225
226static struct qcom_icc_node *ipa_virt_nodes[] = {
227 [MASTER_IPA_CORE] = &ipa_core_master,
228 [SLAVE_IPA_CORE] = &ipa_core_slave,
229};
230
231static const struct qcom_icc_desc sdx55_ipa_virt = {
232 .nodes = ipa_virt_nodes,
233 .num_nodes = ARRAY_SIZE(ipa_virt_nodes),
234 .bcms = ipa_virt_bcms,
235 .num_bcms = ARRAY_SIZE(ipa_virt_bcms),
236};
237
238static const struct of_device_id qnoc_of_match[] = {
239 { .compatible = "qcom,sdx55-mc-virt",
240 .data = &sdx55_mc_virt},
241 { .compatible = "qcom,sdx55-mem-noc",
242 .data = &sdx55_mem_noc},
243 { .compatible = "qcom,sdx55-system-noc",
244 .data = &sdx55_system_noc},
245 { .compatible = "qcom,sdx55-ipa-virt",
246 .data = &sdx55_ipa_virt},
247 { }
248};
249MODULE_DEVICE_TABLE(of, qnoc_of_match);
250
251static struct platform_driver qnoc_driver = {
252 .probe = qcom_icc_rpmh_probe,
253 .remove = qcom_icc_rpmh_remove,
254 .driver = {
255 .name = "qnoc-sdx55",
256 .of_match_table = qnoc_of_match,
257 .sync_state = icc_sync_state,
258 },
259};
260module_platform_driver(qnoc_driver);
261
262MODULE_DESCRIPTION("Qualcomm SDX55 NoC driver");
263MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
264MODULE_LICENSE("GPL v2");
265
