LXR linux/drivers/iommu/mtk

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2015-2016 MediaTek Inc.
   4 * Author: Honghui Zhang <honghui.zhang@mediatek.com>
   5 */
   6
   7#ifndef _MTK_IOMMU_H_
   8#define _MTK_IOMMU_H_
   9
  10#include <linux/clk.h>
  11#include <linux/component.h>
  12#include <linux/device.h>
  13#include <linux/io.h>
  14#include <linux/io-pgtable.h>
  15#include <linux/iommu.h>
  16#include <linux/list.h>
  17#include <linux/spinlock.h>
  18#include <linux/dma-mapping.h>
  19#include <soc/mediatek/smi.h>
  20#include <dt-bindings/memory/mtk-memory-port.h>
  21
  22#define MTK_LARB_COM_MAX        8
  23#define MTK_LARB_SUBCOM_MAX     4
  24
  25#define MTK_IOMMU_GROUP_MAX     8
  26
  27struct mtk_iommu_suspend_reg {
  28        union {
  29                u32                     standard_axi_mode;/* v1 */
  30                u32                     misc_ctrl;/* v2 */
  31        };
  32        u32                             dcm_dis;
  33        u32                             ctrl_reg;
  34        u32                             int_control0;
  35        u32                             int_main_control;
  36        u32                             ivrp_paddr;
  37        u32                             vld_pa_rng;
  38        u32                             wr_len_ctrl;
  39};
  40
  41enum mtk_iommu_plat {
  42        M4U_MT2701,
  43        M4U_MT2712,
  44        M4U_MT6779,
  45        M4U_MT8167,
  46        M4U_MT8173,
  47        M4U_MT8183,
  48        M4U_MT8192,
  49};
  50
  51struct mtk_iommu_iova_region;
  52
  53struct mtk_iommu_plat_data {
  54        enum mtk_iommu_plat m4u_plat;
  55        u32                 flags;
  56        u32                 inv_sel_reg;
  57
  58        unsigned int                            iova_region_nr;
  59        const struct mtk_iommu_iova_region      *iova_region;
  60        unsigned char       larbid_remap[MTK_LARB_COM_MAX][MTK_LARB_SUBCOM_MAX];
  61};
  62
  63struct mtk_iommu_domain;
  64
  65struct mtk_iommu_data {
  66        void __iomem                    *base;
  67        int                             irq;
  68        struct device                   *dev;
  69        struct clk                      *bclk;
  70        phys_addr_t                     protect_base; /* protect memory base */
  71        struct mtk_iommu_suspend_reg    reg;
  72        struct mtk_iommu_domain         *m4u_dom;
  73        struct iommu_group              *m4u_group[MTK_IOMMU_GROUP_MAX];
  74        bool                            enable_4GB;
  75        spinlock_t                      tlb_lock; /* lock for tlb range flush */
  76
  77        struct iommu_device             iommu;
  78        const struct mtk_iommu_plat_data *plat_data;
  79        struct device                   *smicomm_dev;
  80
  81        struct dma_iommu_mapping        *mapping; /* For mtk_iommu_v1.c */
  82
  83        struct list_head                list;
  84        struct mtk_smi_larb_iommu       larb_imu[MTK_LARB_NR_MAX];
  85};
  86
  87static inline int compare_of(struct device *dev, void *data)
  88{
  89        return dev->of_node == data;
  90}
  91
  92static inline void release_of(struct device *dev, void *data)
  93{
  94        of_node_put(data);
  95}
  96
  97static inline int mtk_iommu_bind(struct device *dev)
  98{
  99        struct mtk_iommu_data *data = dev_get_drvdata(dev);
 100
 101        return component_bind_all(dev, &data->larb_imu);
 102}
 103
 104static inline void mtk_iommu_unbind(struct device *dev)
 105{
 106        struct mtk_iommu_data *data = dev_get_drvdata(dev);
 107
 108        component_unbind_all(dev, &data->larb_imu);
 109}
 110
 111#endif
 112