LXR linux/drivers/ipack/devices/scc2698.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * scc2698.h
   4 *
   5 * driver for the IPOCTAL boards
   6 *
   7 * Copyright (C) 2009-2012 CERN (www.cern.ch)
   8 * Author: Nicolas Serafini, EIC2 SA
   9 * Author: Samuel Iglesias Gonsalvez <siglesias@igalia.com>
  10 */
  11
  12#ifndef SCC2698_H_
  13#define SCC2698_H_
  14
  15/*
  16 * union scc2698_channel - Channel access to scc2698 IO
  17 *
  18 * dn value are only spacer.
  19 *
  20 */
  21union scc2698_channel {
  22        struct {
  23                u8 d0, mr;  /* Mode register 1/2*/
  24                u8 d1, sr;  /* Status register */
  25                u8 d2, r1;  /* reserved */
  26                u8 d3, rhr; /* Receive holding register (R) */
  27                u8 junk[8]; /* other crap for block control */
  28        } __packed r; /* Read access */
  29        struct {
  30                u8 d0, mr;  /* Mode register 1/2 */
  31                u8 d1, csr; /* Clock select register */
  32                u8 d2, cr;  /* Command register */
  33                u8 d3, thr; /* Transmit holding register */
  34                u8 junk[8]; /* other crap for block control */
  35        } __packed w; /* Write access */
  36};
  37
  38/*
  39 * union scc2698_block - Block access to scc2698 IO
  40 *
  41 * The scc2698 contain 4 block.
  42 * Each block containt two channel a and b.
  43 * dn value are only spacer.
  44 *
  45 */
  46union scc2698_block {
  47        struct {
  48                u8 d0, mra;  /* Mode register 1/2 (a) */
  49                u8 d1, sra;  /* Status register (a) */
  50                u8 d2, r1;   /* reserved */
  51                u8 d3, rhra; /* Receive holding register (a) */
  52                u8 d4, ipcr; /* Input port change register of block */
  53                u8 d5, isr;  /* Interrupt status register of block */
  54                u8 d6, ctur; /* Counter timer upper register of block */
  55                u8 d7, ctlr; /* Counter timer lower register of block */
  56                u8 d8, mrb;  /* Mode register 1/2 (b) */
  57                u8 d9, srb;  /* Status register (b) */
  58                u8 da, r2;   /* reserved */
  59                u8 db, rhrb; /* Receive holding register (b) */
  60                u8 dc, r3;   /* reserved */
  61                u8 dd, ip;   /* Input port register of block */
  62                u8 de, ctg;  /* Start counter timer of block */
  63                u8 df, cts;  /* Stop counter timer of block */
  64        } __packed r; /* Read access */
  65        struct {
  66                u8 d0, mra;  /* Mode register 1/2 (a) */
  67                u8 d1, csra; /* Clock select register (a) */
  68                u8 d2, cra;  /* Command register (a) */
  69                u8 d3, thra; /* Transmit holding register (a) */
  70                u8 d4, acr;  /* Auxiliary control register of block */
  71                u8 d5, imr;  /* Interrupt mask register of block  */
  72                u8 d6, ctu;  /* Counter timer upper register of block */
  73                u8 d7, ctl;  /* Counter timer lower register of block */
  74                u8 d8, mrb;  /* Mode register 1/2 (b) */
  75                u8 d9, csrb; /* Clock select register (a) */
  76                u8 da, crb;  /* Command register (b) */
  77                u8 db, thrb; /* Transmit holding register (b) */
  78                u8 dc, r1;   /* reserved */
  79                u8 dd, opcr; /* Output port configuration register of block */
  80                u8 de, r2;   /* reserved */
  81                u8 df, r3;   /* reserved */
  82        } __packed w; /* Write access */
  83};
  84
  85#define MR1_CHRL_5_BITS             (0x0 << 0)
  86#define MR1_CHRL_6_BITS             (0x1 << 0)
  87#define MR1_CHRL_7_BITS             (0x2 << 0)
  88#define MR1_CHRL_8_BITS             (0x3 << 0)
  89#define MR1_PARITY_EVEN             (0x1 << 2)
  90#define MR1_PARITY_ODD              (0x0 << 2)
  91#define MR1_PARITY_ON               (0x0 << 3)
  92#define MR1_PARITY_FORCE            (0x1 << 3)
  93#define MR1_PARITY_OFF              (0x2 << 3)
  94#define MR1_PARITY_SPECIAL          (0x3 << 3)
  95#define MR1_ERROR_CHAR              (0x0 << 5)
  96#define MR1_ERROR_BLOCK             (0x1 << 5)
  97#define MR1_RxINT_RxRDY             (0x0 << 6)
  98#define MR1_RxINT_FFULL             (0x1 << 6)
  99#define MR1_RxRTS_CONTROL_ON        (0x1 << 7)
 100#define MR1_RxRTS_CONTROL_OFF       (0x0 << 7)
 101
 102#define MR2_STOP_BITS_LENGTH_1      (0x7 << 0)
 103#define MR2_STOP_BITS_LENGTH_2      (0xF << 0)
 104#define MR2_CTS_ENABLE_TX_ON        (0x1 << 4)
 105#define MR2_CTS_ENABLE_TX_OFF       (0x0 << 4)
 106#define MR2_TxRTS_CONTROL_ON        (0x1 << 5)
 107#define MR2_TxRTS_CONTROL_OFF       (0x0 << 5)
 108#define MR2_CH_MODE_NORMAL          (0x0 << 6)
 109#define MR2_CH_MODE_ECHO            (0x1 << 6)
 110#define MR2_CH_MODE_LOCAL           (0x2 << 6)
 111#define MR2_CH_MODE_REMOTE          (0x3 << 6)
 112
 113#define CR_ENABLE_RX                (0x1 << 0)
 114#define CR_DISABLE_RX               (0x1 << 1)
 115#define CR_ENABLE_TX                (0x1 << 2)
 116#define CR_DISABLE_TX               (0x1 << 3)
 117#define CR_CMD_RESET_MR             (0x1 << 4)
 118#define CR_CMD_RESET_RX             (0x2 << 4)
 119#define CR_CMD_RESET_TX             (0x3 << 4)
 120#define CR_CMD_RESET_ERR_STATUS     (0x4 << 4)
 121#define CR_CMD_RESET_BREAK_CHANGE   (0x5 << 4)
 122#define CR_CMD_START_BREAK          (0x6 << 4)
 123#define CR_CMD_STOP_BREAK           (0x7 << 4)
 124#define CR_CMD_ASSERT_RTSN          (0x8 << 4)
 125#define CR_CMD_NEGATE_RTSN          (0x9 << 4)
 126#define CR_CMD_SET_TIMEOUT_MODE     (0xA << 4)
 127#define CR_CMD_DISABLE_TIMEOUT_MODE (0xC << 4)
 128
 129#define SR_RX_READY                 (0x1 << 0)
 130#define SR_FIFO_FULL                (0x1 << 1)
 131#define SR_TX_READY                 (0x1 << 2)
 132#define SR_TX_EMPTY                 (0x1 << 3)
 133#define SR_OVERRUN_ERROR            (0x1 << 4)
 134#define SR_PARITY_ERROR             (0x1 << 5)
 135#define SR_FRAMING_ERROR            (0x1 << 6)
 136#define SR_RECEIVED_BREAK           (0x1 << 7)
 137
 138#define SR_ERROR                    (0xF0)
 139
 140#define ACR_DELTA_IP0_IRQ_EN        (0x1 << 0)
 141#define ACR_DELTA_IP1_IRQ_EN        (0x1 << 1)
 142#define ACR_DELTA_IP2_IRQ_EN        (0x1 << 2)
 143#define ACR_DELTA_IP3_IRQ_EN        (0x1 << 3)
 144#define ACR_CT_Mask                 (0x7 << 4)
 145#define ACR_CExt                    (0x0 << 4)
 146#define ACR_CTxCA                   (0x1 << 4)
 147#define ACR_CTxCB                   (0x2 << 4)
 148#define ACR_CClk16                  (0x3 << 4)
 149#define ACR_TExt                    (0x4 << 4)
 150#define ACR_TExt16                  (0x5 << 4)
 151#define ACR_TClk                    (0x6 << 4)
 152#define ACR_TClk16                  (0x7 << 4)
 153#define ACR_BRG_SET1                (0x0 << 7)
 154#define ACR_BRG_SET2                (0x1 << 7)
 155
 156#define TX_CLK_75                   (0x0 << 0)
 157#define TX_CLK_110                  (0x1 << 0)
 158#define TX_CLK_38400                (0x2 << 0)
 159#define TX_CLK_150                  (0x3 << 0)
 160#define TX_CLK_300                  (0x4 << 0)
 161#define TX_CLK_600                  (0x5 << 0)
 162#define TX_CLK_1200                 (0x6 << 0)
 163#define TX_CLK_2000                 (0x7 << 0)
 164#define TX_CLK_2400                 (0x8 << 0)
 165#define TX_CLK_4800                 (0x9 << 0)
 166#define TX_CLK_1800                 (0xA << 0)
 167#define TX_CLK_9600                 (0xB << 0)
 168#define TX_CLK_19200                (0xC << 0)
 169#define RX_CLK_75                   (0x0 << 4)
 170#define RX_CLK_110                  (0x1 << 4)
 171#define RX_CLK_38400                (0x2 << 4)
 172#define RX_CLK_150                  (0x3 << 4)
 173#define RX_CLK_300                  (0x4 << 4)
 174#define RX_CLK_600                  (0x5 << 4)
 175#define RX_CLK_1200                 (0x6 << 4)
 176#define RX_CLK_2000                 (0x7 << 4)
 177#define RX_CLK_2400                 (0x8 << 4)
 178#define RX_CLK_4800                 (0x9 << 4)
 179#define RX_CLK_1800                 (0xA << 4)
 180#define RX_CLK_9600                 (0xB << 4)
 181#define RX_CLK_19200                (0xC << 4)
 182
 183#define OPCR_MPOa_RTSN              (0x0 << 0)
 184#define OPCR_MPOa_C_TO              (0x1 << 0)
 185#define OPCR_MPOa_TxC1X             (0x2 << 0)
 186#define OPCR_MPOa_TxC16X            (0x3 << 0)
 187#define OPCR_MPOa_RxC1X             (0x4 << 0)
 188#define OPCR_MPOa_RxC16X            (0x5 << 0)
 189#define OPCR_MPOa_TxRDY             (0x6 << 0)
 190#define OPCR_MPOa_RxRDY_FF          (0x7 << 0)
 191
 192#define OPCR_MPOb_RTSN              (0x0 << 4)
 193#define OPCR_MPOb_C_TO              (0x1 << 4)
 194#define OPCR_MPOb_TxC1X             (0x2 << 4)
 195#define OPCR_MPOb_TxC16X            (0x3 << 4)
 196#define OPCR_MPOb_RxC1X             (0x4 << 4)
 197#define OPCR_MPOb_RxC16X            (0x5 << 4)
 198#define OPCR_MPOb_TxRDY             (0x6 << 4)
 199#define OPCR_MPOb_RxRDY_FF          (0x7 << 4)
 200
 201#define OPCR_MPP_INPUT              (0x0 << 7)
 202#define OPCR_MPP_OUTPUT             (0x1 << 7)
 203
 204#define IMR_TxRDY_A                 (0x1 << 0)
 205#define IMR_RxRDY_FFULL_A           (0x1 << 1)
 206#define IMR_DELTA_BREAK_A           (0x1 << 2)
 207#define IMR_COUNTER_READY           (0x1 << 3)
 208#define IMR_TxRDY_B                 (0x1 << 4)
 209#define IMR_RxRDY_FFULL_B           (0x1 << 5)
 210#define IMR_DELTA_BREAK_B           (0x1 << 6)
 211#define IMR_INPUT_PORT_CHANGE       (0x1 << 7)
 212
 213#define ISR_TxRDY_A                 (0x1 << 0)
 214#define ISR_RxRDY_FFULL_A           (0x1 << 1)
 215#define ISR_DELTA_BREAK_A           (0x1 << 2)
 216#define ISR_COUNTER_READY           (0x1 << 3)
 217#define ISR_TxRDY_B                 (0x1 << 4)
 218#define ISR_RxRDY_FFULL_B           (0x1 << 5)
 219#define ISR_DELTA_BREAK_B           (0x1 << 6)
 220#define ISR_INPUT_PORT_CHANGE       (0x1 << 7)
 221
 222#define ACK_INT_REQ0                    0
 223#define ACK_INT_REQ1                    2
 224
 225#endif /* SCC2698_H_ */
 226