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9#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11#include <linux/bitops.h>
12#include <linux/kernel.h>
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/io.h>
16#include <linux/ioport.h>
17#include <linux/irq.h>
18#include <linux/irqdomain.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
23#include <linux/of_platform.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/smp.h>
27#include <linux/types.h>
28#include <linux/irqchip.h>
29#include <linux/irqchip/chained_irq.h>
30#include <linux/syscore_ops.h>
31#ifdef CONFIG_ARM
32#include <asm/smp_plat.h>
33#endif
34
35#define IRQS_PER_WORD 32
36#define REG_BYTES_PER_IRQ_WORD (sizeof(u32) * 4)
37#define MAX_WORDS 8
38
39struct bcm7038_l1_cpu;
40
41struct bcm7038_l1_chip {
42 raw_spinlock_t lock;
43 unsigned int n_words;
44 struct irq_domain *domain;
45 struct bcm7038_l1_cpu *cpus[NR_CPUS];
46#ifdef CONFIG_PM_SLEEP
47 struct list_head list;
48 u32 wake_mask[MAX_WORDS];
49#endif
50 u32 irq_fwd_mask[MAX_WORDS];
51 u8 affinity[MAX_WORDS * IRQS_PER_WORD];
52};
53
54struct bcm7038_l1_cpu {
55 void __iomem *map_base;
56 u32 mask_cache[];
57};
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83static inline unsigned int reg_status(struct bcm7038_l1_chip *intc,
84 unsigned int word)
85{
86 return (0 * intc->n_words + word) * sizeof(u32);
87}
88
89static inline unsigned int reg_mask_status(struct bcm7038_l1_chip *intc,
90 unsigned int word)
91{
92 return (1 * intc->n_words + word) * sizeof(u32);
93}
94
95static inline unsigned int reg_mask_set(struct bcm7038_l1_chip *intc,
96 unsigned int word)
97{
98 return (2 * intc->n_words + word) * sizeof(u32);
99}
100
101static inline unsigned int reg_mask_clr(struct bcm7038_l1_chip *intc,
102 unsigned int word)
103{
104 return (3 * intc->n_words + word) * sizeof(u32);
105}
106
107static inline u32 l1_readl(void __iomem *reg)
108{
109 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
110 return ioread32be(reg);
111 else
112 return readl(reg);
113}
114
115static inline void l1_writel(u32 val, void __iomem *reg)
116{
117 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
118 iowrite32be(val, reg);
119 else
120 writel(val, reg);
121}
122
123static void bcm7038_l1_irq_handle(struct irq_desc *desc)
124{
125 struct bcm7038_l1_chip *intc = irq_desc_get_handler_data(desc);
126 struct bcm7038_l1_cpu *cpu;
127 struct irq_chip *chip = irq_desc_get_chip(desc);
128 unsigned int idx;
129
130#ifdef CONFIG_SMP
131 cpu = intc->cpus[cpu_logical_map(smp_processor_id())];
132#else
133 cpu = intc->cpus[0];
134#endif
135
136 chained_irq_enter(chip, desc);
137
138 for (idx = 0; idx < intc->n_words; idx++) {
139 int base = idx * IRQS_PER_WORD;
140 unsigned long pending, flags;
141 int hwirq;
142
143 raw_spin_lock_irqsave(&intc->lock, flags);
144 pending = l1_readl(cpu->map_base + reg_status(intc, idx)) &
145 ~cpu->mask_cache[idx];
146 raw_spin_unlock_irqrestore(&intc->lock, flags);
147
148 for_each_set_bit(hwirq, &pending, IRQS_PER_WORD)
149 generic_handle_domain_irq(intc->domain, base + hwirq);
150 }
151
152 chained_irq_exit(chip, desc);
153}
154
155static void __bcm7038_l1_unmask(struct irq_data *d, unsigned int cpu_idx)
156{
157 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
158 u32 word = d->hwirq / IRQS_PER_WORD;
159 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
160
161 intc->cpus[cpu_idx]->mask_cache[word] &= ~mask;
162 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
163 reg_mask_clr(intc, word));
164}
165
166static void __bcm7038_l1_mask(struct irq_data *d, unsigned int cpu_idx)
167{
168 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
169 u32 word = d->hwirq / IRQS_PER_WORD;
170 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
171
172 intc->cpus[cpu_idx]->mask_cache[word] |= mask;
173 l1_writel(mask, intc->cpus[cpu_idx]->map_base +
174 reg_mask_set(intc, word));
175}
176
177static void bcm7038_l1_unmask(struct irq_data *d)
178{
179 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
180 unsigned long flags;
181
182 raw_spin_lock_irqsave(&intc->lock, flags);
183 __bcm7038_l1_unmask(d, intc->affinity[d->hwirq]);
184 raw_spin_unlock_irqrestore(&intc->lock, flags);
185}
186
187static void bcm7038_l1_mask(struct irq_data *d)
188{
189 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
190 unsigned long flags;
191
192 raw_spin_lock_irqsave(&intc->lock, flags);
193 __bcm7038_l1_mask(d, intc->affinity[d->hwirq]);
194 raw_spin_unlock_irqrestore(&intc->lock, flags);
195}
196
197static int bcm7038_l1_set_affinity(struct irq_data *d,
198 const struct cpumask *dest,
199 bool force)
200{
201 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
202 unsigned long flags;
203 irq_hw_number_t hw = d->hwirq;
204 u32 word = hw / IRQS_PER_WORD;
205 u32 mask = BIT(hw % IRQS_PER_WORD);
206 unsigned int first_cpu = cpumask_any_and(dest, cpu_online_mask);
207 bool was_disabled;
208
209 raw_spin_lock_irqsave(&intc->lock, flags);
210
211 was_disabled = !!(intc->cpus[intc->affinity[hw]]->mask_cache[word] &
212 mask);
213 __bcm7038_l1_mask(d, intc->affinity[hw]);
214 intc->affinity[hw] = first_cpu;
215 if (!was_disabled)
216 __bcm7038_l1_unmask(d, first_cpu);
217
218 raw_spin_unlock_irqrestore(&intc->lock, flags);
219 irq_data_update_effective_affinity(d, cpumask_of(first_cpu));
220
221 return 0;
222}
223
224#ifdef CONFIG_SMP
225static void bcm7038_l1_cpu_offline(struct irq_data *d)
226{
227 struct cpumask *mask = irq_data_get_affinity_mask(d);
228 int cpu = smp_processor_id();
229 cpumask_t new_affinity;
230
231
232 if (!cpumask_test_cpu(cpu, mask))
233 return;
234
235 if (cpumask_weight(mask) > 1) {
236
237
238
239
240 cpumask_copy(&new_affinity, mask);
241 cpumask_clear_cpu(cpu, &new_affinity);
242 } else {
243
244 cpumask_clear(&new_affinity);
245 cpumask_set_cpu(cpumask_first(cpu_online_mask), &new_affinity);
246 }
247 irq_set_affinity_locked(d, &new_affinity, false);
248}
249#endif
250
251static int __init bcm7038_l1_init_one(struct device_node *dn,
252 unsigned int idx,
253 struct bcm7038_l1_chip *intc)
254{
255 struct resource res;
256 resource_size_t sz;
257 struct bcm7038_l1_cpu *cpu;
258 unsigned int i, n_words, parent_irq;
259 int ret;
260
261 if (of_address_to_resource(dn, idx, &res))
262 return -EINVAL;
263 sz = resource_size(&res);
264 n_words = sz / REG_BYTES_PER_IRQ_WORD;
265
266 if (n_words > MAX_WORDS)
267 return -EINVAL;
268 else if (!intc->n_words)
269 intc->n_words = n_words;
270 else if (intc->n_words != n_words)
271 return -EINVAL;
272
273 ret = of_property_read_u32_array(dn , "brcm,int-fwd-mask",
274 intc->irq_fwd_mask, n_words);
275 if (ret != 0 && ret != -EINVAL) {
276
277 pr_err("invalid brcm,int-fwd-mask property\n");
278 return -EINVAL;
279 }
280
281 cpu = intc->cpus[idx] = kzalloc(sizeof(*cpu) + n_words * sizeof(u32),
282 GFP_KERNEL);
283 if (!cpu)
284 return -ENOMEM;
285
286 cpu->map_base = ioremap(res.start, sz);
287 if (!cpu->map_base)
288 return -ENOMEM;
289
290 for (i = 0; i < n_words; i++) {
291 l1_writel(~intc->irq_fwd_mask[i],
292 cpu->map_base + reg_mask_set(intc, i));
293 l1_writel(intc->irq_fwd_mask[i],
294 cpu->map_base + reg_mask_clr(intc, i));
295 cpu->mask_cache[i] = ~intc->irq_fwd_mask[i];
296 }
297
298 parent_irq = irq_of_parse_and_map(dn, idx);
299 if (!parent_irq) {
300 pr_err("failed to map parent interrupt %d\n", parent_irq);
301 return -EINVAL;
302 }
303
304 if (of_property_read_bool(dn, "brcm,irq-can-wake"))
305 enable_irq_wake(parent_irq);
306
307 irq_set_chained_handler_and_data(parent_irq, bcm7038_l1_irq_handle,
308 intc);
309
310 return 0;
311}
312
313#ifdef CONFIG_PM_SLEEP
314
315
316
317
318
319
320
321static LIST_HEAD(bcm7038_l1_intcs_list);
322static DEFINE_RAW_SPINLOCK(bcm7038_l1_intcs_lock);
323
324static int bcm7038_l1_suspend(void)
325{
326 struct bcm7038_l1_chip *intc;
327 int boot_cpu, word;
328 u32 val;
329
330
331#ifdef CONFIG_SMP
332 boot_cpu = cpu_logical_map(0);
333#else
334 boot_cpu = 0;
335#endif
336
337 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
338 for (word = 0; word < intc->n_words; word++) {
339 val = intc->wake_mask[word] | intc->irq_fwd_mask[word];
340 l1_writel(~val,
341 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
342 l1_writel(val,
343 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
344 }
345 }
346
347 return 0;
348}
349
350static void bcm7038_l1_resume(void)
351{
352 struct bcm7038_l1_chip *intc;
353 int boot_cpu, word;
354
355#ifdef CONFIG_SMP
356 boot_cpu = cpu_logical_map(0);
357#else
358 boot_cpu = 0;
359#endif
360
361 list_for_each_entry(intc, &bcm7038_l1_intcs_list, list) {
362 for (word = 0; word < intc->n_words; word++) {
363 l1_writel(intc->cpus[boot_cpu]->mask_cache[word],
364 intc->cpus[boot_cpu]->map_base + reg_mask_set(intc, word));
365 l1_writel(~intc->cpus[boot_cpu]->mask_cache[word],
366 intc->cpus[boot_cpu]->map_base + reg_mask_clr(intc, word));
367 }
368 }
369}
370
371static struct syscore_ops bcm7038_l1_syscore_ops = {
372 .suspend = bcm7038_l1_suspend,
373 .resume = bcm7038_l1_resume,
374};
375
376static int bcm7038_l1_set_wake(struct irq_data *d, unsigned int on)
377{
378 struct bcm7038_l1_chip *intc = irq_data_get_irq_chip_data(d);
379 unsigned long flags;
380 u32 word = d->hwirq / IRQS_PER_WORD;
381 u32 mask = BIT(d->hwirq % IRQS_PER_WORD);
382
383 raw_spin_lock_irqsave(&intc->lock, flags);
384 if (on)
385 intc->wake_mask[word] |= mask;
386 else
387 intc->wake_mask[word] &= ~mask;
388 raw_spin_unlock_irqrestore(&intc->lock, flags);
389
390 return 0;
391}
392#endif
393
394static struct irq_chip bcm7038_l1_irq_chip = {
395 .name = "bcm7038-l1",
396 .irq_mask = bcm7038_l1_mask,
397 .irq_unmask = bcm7038_l1_unmask,
398 .irq_set_affinity = bcm7038_l1_set_affinity,
399#ifdef CONFIG_SMP
400 .irq_cpu_offline = bcm7038_l1_cpu_offline,
401#endif
402#ifdef CONFIG_PM_SLEEP
403 .irq_set_wake = bcm7038_l1_set_wake,
404#endif
405};
406
407static int bcm7038_l1_map(struct irq_domain *d, unsigned int virq,
408 irq_hw_number_t hw_irq)
409{
410 struct bcm7038_l1_chip *intc = d->host_data;
411 u32 mask = BIT(hw_irq % IRQS_PER_WORD);
412 u32 word = hw_irq / IRQS_PER_WORD;
413
414 if (intc->irq_fwd_mask[word] & mask)
415 return -EPERM;
416
417 irq_set_chip_and_handler(virq, &bcm7038_l1_irq_chip, handle_level_irq);
418 irq_set_chip_data(virq, d->host_data);
419 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(virq)));
420 return 0;
421}
422
423static const struct irq_domain_ops bcm7038_l1_domain_ops = {
424 .xlate = irq_domain_xlate_onecell,
425 .map = bcm7038_l1_map,
426};
427
428static int __init bcm7038_l1_of_init(struct device_node *dn,
429 struct device_node *parent)
430{
431 struct bcm7038_l1_chip *intc;
432 int idx, ret;
433
434 intc = kzalloc(sizeof(*intc), GFP_KERNEL);
435 if (!intc)
436 return -ENOMEM;
437
438 raw_spin_lock_init(&intc->lock);
439 for_each_possible_cpu(idx) {
440 ret = bcm7038_l1_init_one(dn, idx, intc);
441 if (ret < 0) {
442 if (idx)
443 break;
444 pr_err("failed to remap intc L1 registers\n");
445 goto out_free;
446 }
447 }
448
449 intc->domain = irq_domain_add_linear(dn, IRQS_PER_WORD * intc->n_words,
450 &bcm7038_l1_domain_ops,
451 intc);
452 if (!intc->domain) {
453 ret = -ENOMEM;
454 goto out_unmap;
455 }
456
457#ifdef CONFIG_PM_SLEEP
458
459 raw_spin_lock(&bcm7038_l1_intcs_lock);
460 list_add_tail(&intc->list, &bcm7038_l1_intcs_list);
461 raw_spin_unlock(&bcm7038_l1_intcs_lock);
462
463 if (list_is_singular(&bcm7038_l1_intcs_list))
464 register_syscore_ops(&bcm7038_l1_syscore_ops);
465#endif
466
467 pr_info("registered BCM7038 L1 intc (%pOF, IRQs: %d)\n",
468 dn, IRQS_PER_WORD * intc->n_words);
469
470 return 0;
471
472out_unmap:
473 for_each_possible_cpu(idx) {
474 struct bcm7038_l1_cpu *cpu = intc->cpus[idx];
475
476 if (cpu) {
477 if (cpu->map_base)
478 iounmap(cpu->map_base);
479 kfree(cpu);
480 }
481 }
482out_free:
483 kfree(intc);
484 return ret;
485}
486
487IRQCHIP_DECLARE(bcm7038_l1, "brcm,bcm7038-l1-intc", bcm7038_l1_of_init);
488
