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7#include <linux/clk.h>
8#include <linux/interrupt.h>
9#include <linux/irq.h>
10#include <linux/irqchip/chained_irq.h>
11#include <linux/irqdomain.h>
12#include <linux/kernel.h>
13#include <linux/of_irq.h>
14#include <linux/of_platform.h>
15#include <linux/spinlock.h>
16
17#define CTRL_STRIDE_OFF(_t, _r) (_t * 4 * _r)
18#define CHANCTRL 0x0
19#define CHANMASK(n, t) (CTRL_STRIDE_OFF(t, 0) + 0x4 * (n) + 0x4)
20#define CHANSET(n, t) (CTRL_STRIDE_OFF(t, 1) + 0x4 * (n) + 0x4)
21#define CHANSTATUS(n, t) (CTRL_STRIDE_OFF(t, 2) + 0x4 * (n) + 0x4)
22#define CHAN_MINTDIS(t) (CTRL_STRIDE_OFF(t, 3) + 0x4)
23#define CHAN_MASTRSTAT(t) (CTRL_STRIDE_OFF(t, 3) + 0x8)
24
25#define CHAN_MAX_OUTPUT_INT 0x8
26
27struct irqsteer_data {
28 void __iomem *regs;
29 struct clk *ipg_clk;
30 int irq[CHAN_MAX_OUTPUT_INT];
31 int irq_count;
32 raw_spinlock_t lock;
33 int reg_num;
34 int channel;
35 struct irq_domain *domain;
36 u32 *saved_reg;
37};
38
39static int imx_irqsteer_get_reg_index(struct irqsteer_data *data,
40 unsigned long irqnum)
41{
42 return (data->reg_num - irqnum / 32 - 1);
43}
44
45static void imx_irqsteer_irq_unmask(struct irq_data *d)
46{
47 struct irqsteer_data *data = d->chip_data;
48 int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
49 unsigned long flags;
50 u32 val;
51
52 raw_spin_lock_irqsave(&data->lock, flags);
53 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
54 val |= BIT(d->hwirq % 32);
55 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
56 raw_spin_unlock_irqrestore(&data->lock, flags);
57}
58
59static void imx_irqsteer_irq_mask(struct irq_data *d)
60{
61 struct irqsteer_data *data = d->chip_data;
62 int idx = imx_irqsteer_get_reg_index(data, d->hwirq);
63 unsigned long flags;
64 u32 val;
65
66 raw_spin_lock_irqsave(&data->lock, flags);
67 val = readl_relaxed(data->regs + CHANMASK(idx, data->reg_num));
68 val &= ~BIT(d->hwirq % 32);
69 writel_relaxed(val, data->regs + CHANMASK(idx, data->reg_num));
70 raw_spin_unlock_irqrestore(&data->lock, flags);
71}
72
73static struct irq_chip imx_irqsteer_irq_chip = {
74 .name = "irqsteer",
75 .irq_mask = imx_irqsteer_irq_mask,
76 .irq_unmask = imx_irqsteer_irq_unmask,
77};
78
79static int imx_irqsteer_irq_map(struct irq_domain *h, unsigned int irq,
80 irq_hw_number_t hwirq)
81{
82 irq_set_status_flags(irq, IRQ_LEVEL);
83 irq_set_chip_data(irq, h->host_data);
84 irq_set_chip_and_handler(irq, &imx_irqsteer_irq_chip, handle_level_irq);
85
86 return 0;
87}
88
89static const struct irq_domain_ops imx_irqsteer_domain_ops = {
90 .map = imx_irqsteer_irq_map,
91 .xlate = irq_domain_xlate_onecell,
92};
93
94static int imx_irqsteer_get_hwirq_base(struct irqsteer_data *data, u32 irq)
95{
96 int i;
97
98 for (i = 0; i < data->irq_count; i++) {
99 if (data->irq[i] == irq)
100 return i * 64;
101 }
102
103 return -EINVAL;
104}
105
106static void imx_irqsteer_irq_handler(struct irq_desc *desc)
107{
108 struct irqsteer_data *data = irq_desc_get_handler_data(desc);
109 int hwirq;
110 int irq, i;
111
112 chained_irq_enter(irq_desc_get_chip(desc), desc);
113
114 irq = irq_desc_get_irq(desc);
115 hwirq = imx_irqsteer_get_hwirq_base(data, irq);
116 if (hwirq < 0) {
117 pr_warn("%s: unable to get hwirq base for irq %d\n",
118 __func__, irq);
119 return;
120 }
121
122 for (i = 0; i < 2; i++, hwirq += 32) {
123 int idx = imx_irqsteer_get_reg_index(data, hwirq);
124 unsigned long irqmap;
125 int pos;
126
127 if (hwirq >= data->reg_num * 32)
128 break;
129
130 irqmap = readl_relaxed(data->regs +
131 CHANSTATUS(idx, data->reg_num));
132
133 for_each_set_bit(pos, &irqmap, 32)
134 generic_handle_domain_irq(data->domain, pos + hwirq);
135 }
136
137 chained_irq_exit(irq_desc_get_chip(desc), desc);
138}
139
140static int imx_irqsteer_probe(struct platform_device *pdev)
141{
142 struct device_node *np = pdev->dev.of_node;
143 struct irqsteer_data *data;
144 u32 irqs_num;
145 int i, ret;
146
147 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
148 if (!data)
149 return -ENOMEM;
150
151 data->regs = devm_platform_ioremap_resource(pdev, 0);
152 if (IS_ERR(data->regs)) {
153 dev_err(&pdev->dev, "failed to initialize reg\n");
154 return PTR_ERR(data->regs);
155 }
156
157 data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
158 if (IS_ERR(data->ipg_clk))
159 return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
160 "failed to get ipg clk\n");
161
162 raw_spin_lock_init(&data->lock);
163
164 ret = of_property_read_u32(np, "fsl,num-irqs", &irqs_num);
165 if (ret)
166 return ret;
167 ret = of_property_read_u32(np, "fsl,channel", &data->channel);
168 if (ret)
169 return ret;
170
171
172
173
174
175 data->irq_count = DIV_ROUND_UP(irqs_num, 64);
176 data->reg_num = irqs_num / 32;
177
178 if (IS_ENABLED(CONFIG_PM_SLEEP)) {
179 data->saved_reg = devm_kzalloc(&pdev->dev,
180 sizeof(u32) * data->reg_num,
181 GFP_KERNEL);
182 if (!data->saved_reg)
183 return -ENOMEM;
184 }
185
186 ret = clk_prepare_enable(data->ipg_clk);
187 if (ret) {
188 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
189 return ret;
190 }
191
192
193 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
194
195 data->domain = irq_domain_add_linear(np, data->reg_num * 32,
196 &imx_irqsteer_domain_ops, data);
197 if (!data->domain) {
198 dev_err(&pdev->dev, "failed to create IRQ domain\n");
199 ret = -ENOMEM;
200 goto out;
201 }
202
203 if (!data->irq_count || data->irq_count > CHAN_MAX_OUTPUT_INT) {
204 ret = -EINVAL;
205 goto out;
206 }
207
208 for (i = 0; i < data->irq_count; i++) {
209 data->irq[i] = irq_of_parse_and_map(np, i);
210 if (!data->irq[i]) {
211 ret = -EINVAL;
212 goto out;
213 }
214
215 irq_set_chained_handler_and_data(data->irq[i],
216 imx_irqsteer_irq_handler,
217 data);
218 }
219
220 platform_set_drvdata(pdev, data);
221
222 return 0;
223out:
224 clk_disable_unprepare(data->ipg_clk);
225 return ret;
226}
227
228static int imx_irqsteer_remove(struct platform_device *pdev)
229{
230 struct irqsteer_data *irqsteer_data = platform_get_drvdata(pdev);
231 int i;
232
233 for (i = 0; i < irqsteer_data->irq_count; i++)
234 irq_set_chained_handler_and_data(irqsteer_data->irq[i],
235 NULL, NULL);
236
237 irq_domain_remove(irqsteer_data->domain);
238
239 clk_disable_unprepare(irqsteer_data->ipg_clk);
240
241 return 0;
242}
243
244#ifdef CONFIG_PM_SLEEP
245static void imx_irqsteer_save_regs(struct irqsteer_data *data)
246{
247 int i;
248
249 for (i = 0; i < data->reg_num; i++)
250 data->saved_reg[i] = readl_relaxed(data->regs +
251 CHANMASK(i, data->reg_num));
252}
253
254static void imx_irqsteer_restore_regs(struct irqsteer_data *data)
255{
256 int i;
257
258 writel_relaxed(BIT(data->channel), data->regs + CHANCTRL);
259 for (i = 0; i < data->reg_num; i++)
260 writel_relaxed(data->saved_reg[i],
261 data->regs + CHANMASK(i, data->reg_num));
262}
263
264static int imx_irqsteer_suspend(struct device *dev)
265{
266 struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
267
268 imx_irqsteer_save_regs(irqsteer_data);
269 clk_disable_unprepare(irqsteer_data->ipg_clk);
270
271 return 0;
272}
273
274static int imx_irqsteer_resume(struct device *dev)
275{
276 struct irqsteer_data *irqsteer_data = dev_get_drvdata(dev);
277 int ret;
278
279 ret = clk_prepare_enable(irqsteer_data->ipg_clk);
280 if (ret) {
281 dev_err(dev, "failed to enable ipg clk: %d\n", ret);
282 return ret;
283 }
284 imx_irqsteer_restore_regs(irqsteer_data);
285
286 return 0;
287}
288#endif
289
290static const struct dev_pm_ops imx_irqsteer_pm_ops = {
291 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx_irqsteer_suspend, imx_irqsteer_resume)
292};
293
294static const struct of_device_id imx_irqsteer_dt_ids[] = {
295 { .compatible = "fsl,imx-irqsteer", },
296 {},
297};
298
299static struct platform_driver imx_irqsteer_driver = {
300 .driver = {
301 .name = "imx-irqsteer",
302 .of_match_table = imx_irqsteer_dt_ids,
303 .pm = &imx_irqsteer_pm_ops,
304 },
305 .probe = imx_irqsteer_probe,
306 .remove = imx_irqsteer_remove,
307};
308builtin_platform_driver(imx_irqsteer_driver);
309
