LXR linux/drivers/irqchip/irq-renesas-intc-irqpin.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Renesas INTC External IRQ Pin Driver
   4 *
   5 *  Copyright (C) 2013 Magnus Damm
   6 */
   7
   8#include <linux/init.h>
   9#include <linux/of.h>
  10#include <linux/platform_device.h>
  11#include <linux/spinlock.h>
  12#include <linux/interrupt.h>
  13#include <linux/ioport.h>
  14#include <linux/io.h>
  15#include <linux/irq.h>
  16#include <linux/irqdomain.h>
  17#include <linux/err.h>
  18#include <linux/slab.h>
  19#include <linux/module.h>
  20#include <linux/of_device.h>
  21#include <linux/pm_runtime.h>
  22
  23#define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */
  24
  25#define INTC_IRQPIN_REG_SENSE 0 /* ICRn */
  26#define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */
  27#define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */
  28#define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */
  29#define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */
  30#define INTC_IRQPIN_REG_NR_MANDATORY 5
  31#define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */
  32#define INTC_IRQPIN_REG_NR 6
  33
  34/* INTC external IRQ PIN hardware register access:
  35 *
  36 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
  37 * PRIO is read-write 32-bit with 4-bits per IRQ (**)
  38 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
  39 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  40 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
  41 *
  42 * (*) May be accessed by more than one driver instance - lock needed
  43 * (**) Read-modify-write access by one driver instance - lock needed
  44 * (***) Accessed by one driver instance only - no locking needed
  45 */
  46
  47struct intc_irqpin_iomem {
  48        void __iomem *iomem;
  49        unsigned long (*read)(void __iomem *iomem);
  50        void (*write)(void __iomem *iomem, unsigned long data);
  51        int width;
  52};
  53
  54struct intc_irqpin_irq {
  55        int hw_irq;
  56        int requested_irq;
  57        int domain_irq;
  58        struct intc_irqpin_priv *p;
  59};
  60
  61struct intc_irqpin_priv {
  62        struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
  63        struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
  64        unsigned int sense_bitfield_width;
  65        struct platform_device *pdev;
  66        struct irq_chip irq_chip;
  67        struct irq_domain *irq_domain;
  68        atomic_t wakeup_path;
  69        unsigned shared_irqs:1;
  70        u8 shared_irq_mask;
  71};
  72
  73struct intc_irqpin_config {
  74        int irlm_bit;           /* -1 if non-existent */
  75};
  76
  77static unsigned long intc_irqpin_read32(void __iomem *iomem)
  78{
  79        return ioread32(iomem);
  80}
  81
  82static unsigned long intc_irqpin_read8(void __iomem *iomem)
  83{
  84        return ioread8(iomem);
  85}
  86
  87static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
  88{
  89        iowrite32(data, iomem);
  90}
  91
  92static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
  93{
  94        iowrite8(data, iomem);
  95}
  96
  97static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
  98                                             int reg)
  99{
 100        struct intc_irqpin_iomem *i = &p->iomem[reg];
 101
 102        return i->read(i->iomem);
 103}
 104
 105static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
 106                                     int reg, unsigned long data)
 107{
 108        struct intc_irqpin_iomem *i = &p->iomem[reg];
 109
 110        i->write(i->iomem, data);
 111}
 112
 113static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
 114                                                   int reg, int hw_irq)
 115{
 116        return BIT((p->iomem[reg].width - 1) - hw_irq);
 117}
 118
 119static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
 120                                               int reg, int hw_irq)
 121{
 122        intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
 123}
 124
 125static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */
 126
 127static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
 128                                          int reg, int shift,
 129                                          int width, int value)
 130{
 131        unsigned long flags;
 132        unsigned long tmp;
 133
 134        raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
 135
 136        tmp = intc_irqpin_read(p, reg);
 137        tmp &= ~(((1 << width) - 1) << shift);
 138        tmp |= value << shift;
 139        intc_irqpin_write(p, reg, tmp);
 140
 141        raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
 142}
 143
 144static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
 145                                         int irq, int do_mask)
 146{
 147        /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */
 148        int bitfield_width = 4;
 149        int shift = 32 - (irq + 1) * bitfield_width;
 150
 151        intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
 152                                      shift, bitfield_width,
 153                                      do_mask ? 0 : (1 << bitfield_width) - 1);
 154}
 155
 156static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
 157{
 158        /* The SENSE register is assumed to be 32-bit. */
 159        int bitfield_width = p->sense_bitfield_width;
 160        int shift = 32 - (irq + 1) * bitfield_width;
 161
 162        dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
 163
 164        if (value >= (1 << bitfield_width))
 165                return -EINVAL;
 166
 167        intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
 168                                      bitfield_width, value);
 169        return 0;
 170}
 171
 172static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
 173{
 174        dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
 175                str, i->requested_irq, i->hw_irq, i->domain_irq);
 176}
 177
 178static void intc_irqpin_irq_enable(struct irq_data *d)
 179{
 180        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 181        int hw_irq = irqd_to_hwirq(d);
 182
 183        intc_irqpin_dbg(&p->irq[hw_irq], "enable");
 184        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
 185}
 186
 187static void intc_irqpin_irq_disable(struct irq_data *d)
 188{
 189        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 190        int hw_irq = irqd_to_hwirq(d);
 191
 192        intc_irqpin_dbg(&p->irq[hw_irq], "disable");
 193        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
 194}
 195
 196static void intc_irqpin_shared_irq_enable(struct irq_data *d)
 197{
 198        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 199        int hw_irq = irqd_to_hwirq(d);
 200
 201        intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
 202        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
 203
 204        p->shared_irq_mask &= ~BIT(hw_irq);
 205}
 206
 207static void intc_irqpin_shared_irq_disable(struct irq_data *d)
 208{
 209        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 210        int hw_irq = irqd_to_hwirq(d);
 211
 212        intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
 213        intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
 214
 215        p->shared_irq_mask |= BIT(hw_irq);
 216}
 217
 218static void intc_irqpin_irq_enable_force(struct irq_data *d)
 219{
 220        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 221        int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
 222
 223        intc_irqpin_irq_enable(d);
 224
 225        /* enable interrupt through parent interrupt controller,
 226         * assumes non-shared interrupt with 1:1 mapping
 227         * needed for busted IRQs on some SoCs like sh73a0
 228         */
 229        irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
 230}
 231
 232static void intc_irqpin_irq_disable_force(struct irq_data *d)
 233{
 234        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 235        int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
 236
 237        /* disable interrupt through parent interrupt controller,
 238         * assumes non-shared interrupt with 1:1 mapping
 239         * needed for busted IRQs on some SoCs like sh73a0
 240         */
 241        irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
 242        intc_irqpin_irq_disable(d);
 243}
 244
 245#define INTC_IRQ_SENSE_VALID 0x10
 246#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
 247
 248static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
 249        [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
 250        [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
 251        [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
 252        [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
 253        [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
 254};
 255
 256static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
 257{
 258        unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
 259        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 260
 261        if (!(value & INTC_IRQ_SENSE_VALID))
 262                return -EINVAL;
 263
 264        return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
 265                                     value ^ INTC_IRQ_SENSE_VALID);
 266}
 267
 268static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
 269{
 270        struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
 271        int hw_irq = irqd_to_hwirq(d);
 272
 273        irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
 274        if (on)
 275                atomic_inc(&p->wakeup_path);
 276        else
 277                atomic_dec(&p->wakeup_path);
 278
 279        return 0;
 280}
 281
 282static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
 283{
 284        struct intc_irqpin_irq *i = dev_id;
 285        struct intc_irqpin_priv *p = i->p;
 286        unsigned long bit;
 287
 288        intc_irqpin_dbg(i, "demux1");
 289        bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
 290
 291        if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
 292                intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
 293                intc_irqpin_dbg(i, "demux2");
 294                generic_handle_irq(i->domain_irq);
 295                return IRQ_HANDLED;
 296        }
 297        return IRQ_NONE;
 298}
 299
 300static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
 301{
 302        struct intc_irqpin_priv *p = dev_id;
 303        unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
 304        irqreturn_t status = IRQ_NONE;
 305        int k;
 306
 307        for (k = 0; k < 8; k++) {
 308                if (reg_source & BIT(7 - k)) {
 309                        if (BIT(k) & p->shared_irq_mask)
 310                                continue;
 311
 312                        status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
 313                }
 314        }
 315
 316        return status;
 317}
 318
 319/*
 320 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a
 321 * different category than their parents, so it won't report false recursion.
 322 */
 323static struct lock_class_key intc_irqpin_irq_lock_class;
 324
 325/* And this is for the request mutex */
 326static struct lock_class_key intc_irqpin_irq_request_class;
 327
 328static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
 329                                      irq_hw_number_t hw)
 330{
 331        struct intc_irqpin_priv *p = h->host_data;
 332
 333        p->irq[hw].domain_irq = virq;
 334        p->irq[hw].hw_irq = hw;
 335
 336        intc_irqpin_dbg(&p->irq[hw], "map");
 337        irq_set_chip_data(virq, h->host_data);
 338        irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
 339                              &intc_irqpin_irq_request_class);
 340        irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
 341        return 0;
 342}
 343
 344static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
 345        .map    = intc_irqpin_irq_domain_map,
 346        .xlate  = irq_domain_xlate_twocell,
 347};
 348
 349static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
 350        .irlm_bit = 23, /* ICR0.IRLM0 */
 351};
 352
 353static const struct intc_irqpin_config intc_irqpin_rmobile = {
 354        .irlm_bit = -1,
 355};
 356
 357static const struct of_device_id intc_irqpin_dt_ids[] = {
 358        { .compatible = "renesas,intc-irqpin", },
 359        { .compatible = "renesas,intc-irqpin-r8a7778",
 360          .data = &intc_irqpin_irlm_r8a777x },
 361        { .compatible = "renesas,intc-irqpin-r8a7779",
 362          .data = &intc_irqpin_irlm_r8a777x },
 363        { .compatible = "renesas,intc-irqpin-r8a7740",
 364          .data = &intc_irqpin_rmobile },
 365        { .compatible = "renesas,intc-irqpin-sh73a0",
 366          .data = &intc_irqpin_rmobile },
 367        {},
 368};
 369MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
 370
 371static int intc_irqpin_probe(struct platform_device *pdev)
 372{
 373        const struct intc_irqpin_config *config;
 374        struct device *dev = &pdev->dev;
 375        struct intc_irqpin_priv *p;
 376        struct intc_irqpin_iomem *i;
 377        struct resource *io[INTC_IRQPIN_REG_NR];
 378        struct resource *irq;
 379        struct irq_chip *irq_chip;
 380        void (*enable_fn)(struct irq_data *d);
 381        void (*disable_fn)(struct irq_data *d);
 382        const char *name = dev_name(dev);
 383        bool control_parent;
 384        unsigned int nirqs;
 385        int ref_irq;
 386        int ret;
 387        int k;
 388
 389        p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
 390        if (!p)
 391                return -ENOMEM;
 392
 393        /* deal with driver instance configuration */
 394        of_property_read_u32(dev->of_node, "sense-bitfield-width",
 395                             &p->sense_bitfield_width);
 396        control_parent = of_property_read_bool(dev->of_node, "control-parent");
 397        if (!p->sense_bitfield_width)
 398                p->sense_bitfield_width = 4; /* default to 4 bits */
 399
 400        p->pdev = pdev;
 401        platform_set_drvdata(pdev, p);
 402
 403        config = of_device_get_match_data(dev);
 404
 405        pm_runtime_enable(dev);
 406        pm_runtime_get_sync(dev);
 407
 408        /* get hold of register banks */
 409        memset(io, 0, sizeof(io));
 410        for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
 411                io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
 412                if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
 413                        dev_err(dev, "not enough IOMEM resources\n");
 414                        ret = -EINVAL;
 415                        goto err0;
 416                }
 417        }
 418
 419        /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */
 420        for (k = 0; k < INTC_IRQPIN_MAX; k++) {
 421                irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
 422                if (!irq)
 423                        break;
 424
 425                p->irq[k].p = p;
 426                p->irq[k].requested_irq = irq->start;
 427        }
 428
 429        nirqs = k;
 430        if (nirqs < 1) {
 431                dev_err(dev, "not enough IRQ resources\n");
 432                ret = -EINVAL;
 433                goto err0;
 434        }
 435
 436        /* ioremap IOMEM and setup read/write callbacks */
 437        for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
 438                i = &p->iomem[k];
 439
 440                /* handle optional registers */
 441                if (!io[k])
 442                        continue;
 443
 444                switch (resource_size(io[k])) {
 445                case 1:
 446                        i->width = 8;
 447                        i->read = intc_irqpin_read8;
 448                        i->write = intc_irqpin_write8;
 449                        break;
 450                case 4:
 451                        i->width = 32;
 452                        i->read = intc_irqpin_read32;
 453                        i->write = intc_irqpin_write32;
 454                        break;
 455                default:
 456                        dev_err(dev, "IOMEM size mismatch\n");
 457                        ret = -EINVAL;
 458                        goto err0;
 459                }
 460
 461                i->iomem = devm_ioremap(dev, io[k]->start,
 462                                        resource_size(io[k]));
 463                if (!i->iomem) {
 464                        dev_err(dev, "failed to remap IOMEM\n");
 465                        ret = -ENXIO;
 466                        goto err0;
 467                }
 468        }
 469
 470        /* configure "individual IRQ mode" where needed */
 471        if (config && config->irlm_bit >= 0) {
 472                if (io[INTC_IRQPIN_REG_IRLM])
 473                        intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
 474                                                      config->irlm_bit, 1, 1);
 475                else
 476                        dev_warn(dev, "unable to select IRLM mode\n");
 477        }
 478
 479        /* mask all interrupts using priority */
 480        for (k = 0; k < nirqs; k++)
 481                intc_irqpin_mask_unmask_prio(p, k, 1);
 482
 483        /* clear all pending interrupts */
 484        intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
 485
 486        /* scan for shared interrupt lines */
 487        ref_irq = p->irq[0].requested_irq;
 488        p->shared_irqs = 1;
 489        for (k = 1; k < nirqs; k++) {
 490                if (ref_irq != p->irq[k].requested_irq) {
 491                        p->shared_irqs = 0;
 492                        break;
 493                }
 494        }
 495
 496        /* use more severe masking method if requested */
 497        if (control_parent) {
 498                enable_fn = intc_irqpin_irq_enable_force;
 499                disable_fn = intc_irqpin_irq_disable_force;
 500        } else if (!p->shared_irqs) {
 501                enable_fn = intc_irqpin_irq_enable;
 502                disable_fn = intc_irqpin_irq_disable;
 503        } else {
 504                enable_fn = intc_irqpin_shared_irq_enable;
 505                disable_fn = intc_irqpin_shared_irq_disable;
 506        }
 507
 508        irq_chip = &p->irq_chip;
 509        irq_chip->name = "intc-irqpin";
 510        irq_chip->parent_device = dev;
 511        irq_chip->irq_mask = disable_fn;
 512        irq_chip->irq_unmask = enable_fn;
 513        irq_chip->irq_set_type = intc_irqpin_irq_set_type;
 514        irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
 515        irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
 516
 517        p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
 518                                              &intc_irqpin_irq_domain_ops, p);
 519        if (!p->irq_domain) {
 520                ret = -ENXIO;
 521                dev_err(dev, "cannot initialize irq domain\n");
 522                goto err0;
 523        }
 524
 525        if (p->shared_irqs) {
 526                /* request one shared interrupt */
 527                if (devm_request_irq(dev, p->irq[0].requested_irq,
 528                                intc_irqpin_shared_irq_handler,
 529                                IRQF_SHARED, name, p)) {
 530                        dev_err(dev, "failed to request low IRQ\n");
 531                        ret = -ENOENT;
 532                        goto err1;
 533                }
 534        } else {
 535                /* request interrupts one by one */
 536                for (k = 0; k < nirqs; k++) {
 537                        if (devm_request_irq(dev, p->irq[k].requested_irq,
 538                                             intc_irqpin_irq_handler, 0, name,
 539                                             &p->irq[k])) {
 540                                dev_err(dev, "failed to request low IRQ\n");
 541                                ret = -ENOENT;
 542                                goto err1;
 543                        }
 544                }
 545        }
 546
 547        /* unmask all interrupts on prio level */
 548        for (k = 0; k < nirqs; k++)
 549                intc_irqpin_mask_unmask_prio(p, k, 0);
 550
 551        dev_info(dev, "driving %d irqs\n", nirqs);
 552
 553        return 0;
 554
 555err1:
 556        irq_domain_remove(p->irq_domain);
 557err0:
 558        pm_runtime_put(dev);
 559        pm_runtime_disable(dev);
 560        return ret;
 561}
 562
 563static int intc_irqpin_remove(struct platform_device *pdev)
 564{
 565        struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
 566
 567        irq_domain_remove(p->irq_domain);
 568        pm_runtime_put(&pdev->dev);
 569        pm_runtime_disable(&pdev->dev);
 570        return 0;
 571}
 572
 573static int __maybe_unused intc_irqpin_suspend(struct device *dev)
 574{
 575        struct intc_irqpin_priv *p = dev_get_drvdata(dev);
 576
 577        if (atomic_read(&p->wakeup_path))
 578                device_set_wakeup_path(dev);
 579
 580        return 0;
 581}
 582
 583static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
 584
 585static struct platform_driver intc_irqpin_device_driver = {
 586        .probe          = intc_irqpin_probe,
 587        .remove         = intc_irqpin_remove,
 588        .driver         = {
 589                .name   = "renesas_intc_irqpin",
 590                .of_match_table = intc_irqpin_dt_ids,
 591                .pm     = &intc_irqpin_pm_ops,
 592        }
 593};
 594
 595static int __init intc_irqpin_init(void)
 596{
 597        return platform_driver_register(&intc_irqpin_device_driver);
 598}
 599postcore_initcall(intc_irqpin_init);
 600
 601static void __exit intc_irqpin_exit(void)
 602{
 603        platform_driver_unregister(&intc_irqpin_device_driver);
 604}
 605module_exit(intc_irqpin_exit);
 606
 607MODULE_AUTHOR("Magnus Damm");
 608MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
 609MODULE_LICENSE("GPL v2");
 610