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18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/hdmi.h>
21#include <linux/i2c.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of_graph.h>
25#include <linux/slab.h>
26#include <linux/v4l2-dv-timings.h>
27#include <linux/videodev2.h>
28#include <linux/workqueue.h>
29#include <linux/regmap.h>
30#include <linux/interrupt.h>
31
32#include <media/i2c/adv7604.h>
33#include <media/cec.h>
34#include <media/v4l2-ctrls.h>
35#include <media/v4l2-device.h>
36#include <media/v4l2-event.h>
37#include <media/v4l2-dv-timings.h>
38#include <media/v4l2-fwnode.h>
39
40static int debug;
41module_param(debug, int, 0644);
42MODULE_PARM_DESC(debug, "debug level (0-2)");
43
44MODULE_DESCRIPTION("Analog Devices ADV7604 video decoder driver");
45MODULE_AUTHOR("Hans Verkuil <hans.verkuil@cisco.com>");
46MODULE_AUTHOR("Mats Randgaard <mats.randgaard@cisco.com>");
47MODULE_LICENSE("GPL");
48
49
50#define ADV76XX_FSC (28636360)
51
52#define ADV76XX_RGB_OUT (1 << 1)
53
54#define ADV76XX_OP_FORMAT_SEL_8BIT (0 << 0)
55#define ADV7604_OP_FORMAT_SEL_10BIT (1 << 0)
56#define ADV76XX_OP_FORMAT_SEL_12BIT (2 << 0)
57
58#define ADV76XX_OP_MODE_SEL_SDR_422 (0 << 5)
59#define ADV7604_OP_MODE_SEL_DDR_422 (1 << 5)
60#define ADV76XX_OP_MODE_SEL_SDR_444 (2 << 5)
61#define ADV7604_OP_MODE_SEL_DDR_444 (3 << 5)
62#define ADV76XX_OP_MODE_SEL_SDR_422_2X (4 << 5)
63#define ADV7604_OP_MODE_SEL_ADI_CM (5 << 5)
64
65#define ADV76XX_OP_CH_SEL_GBR (0 << 5)
66#define ADV76XX_OP_CH_SEL_GRB (1 << 5)
67#define ADV76XX_OP_CH_SEL_BGR (2 << 5)
68#define ADV76XX_OP_CH_SEL_RGB (3 << 5)
69#define ADV76XX_OP_CH_SEL_BRG (4 << 5)
70#define ADV76XX_OP_CH_SEL_RBG (5 << 5)
71
72#define ADV76XX_OP_SWAP_CB_CR (1 << 0)
73
74#define ADV76XX_MAX_ADDRS (3)
75
76#define ADV76XX_MAX_EDID_BLOCKS 4
77
78enum adv76xx_type {
79 ADV7604,
80 ADV7611,
81 ADV7612,
82};
83
84struct adv76xx_reg_seq {
85 unsigned int reg;
86 u8 val;
87};
88
89struct adv76xx_format_info {
90 u32 code;
91 u8 op_ch_sel;
92 bool rgb_out;
93 bool swap_cb_cr;
94 u8 op_format_sel;
95};
96
97struct adv76xx_cfg_read_infoframe {
98 const char *desc;
99 u8 present_mask;
100 u8 head_addr;
101 u8 payload_addr;
102};
103
104struct adv76xx_chip_info {
105 enum adv76xx_type type;
106
107 bool has_afe;
108 unsigned int max_port;
109 unsigned int num_dv_ports;
110
111 unsigned int edid_enable_reg;
112 unsigned int edid_status_reg;
113 unsigned int edid_segment_reg;
114 unsigned int edid_segment_mask;
115 unsigned int edid_spa_loc_reg;
116 unsigned int edid_spa_loc_msb_mask;
117 unsigned int edid_spa_port_b_reg;
118 unsigned int lcf_reg;
119
120 unsigned int cable_det_mask;
121 unsigned int tdms_lock_mask;
122 unsigned int fmt_change_digital_mask;
123 unsigned int cp_csc;
124
125 unsigned int cec_irq_status;
126 unsigned int cec_rx_enable;
127 unsigned int cec_rx_enable_mask;
128 bool cec_irq_swap;
129
130 const struct adv76xx_format_info *formats;
131 unsigned int nformats;
132
133 void (*set_termination)(struct v4l2_subdev *sd, bool enable);
134 void (*setup_irqs)(struct v4l2_subdev *sd);
135 unsigned int (*read_hdmi_pixelclock)(struct v4l2_subdev *sd);
136 unsigned int (*read_cable_det)(struct v4l2_subdev *sd);
137
138
139 const struct adv76xx_reg_seq *recommended_settings[2];
140 unsigned int num_recommended_settings[2];
141
142 unsigned long page_mask;
143
144
145 unsigned int linewidth_mask;
146 unsigned int field0_height_mask;
147 unsigned int field1_height_mask;
148 unsigned int hfrontporch_mask;
149 unsigned int hsync_mask;
150 unsigned int hbackporch_mask;
151 unsigned int field0_vfrontporch_mask;
152 unsigned int field1_vfrontporch_mask;
153 unsigned int field0_vsync_mask;
154 unsigned int field1_vsync_mask;
155 unsigned int field0_vbackporch_mask;
156 unsigned int field1_vbackporch_mask;
157};
158
159
160
161
162
163
164
165
166
167struct adv76xx_state {
168 const struct adv76xx_chip_info *info;
169 struct adv76xx_platform_data pdata;
170
171 struct gpio_desc *hpd_gpio[4];
172 struct gpio_desc *reset_gpio;
173
174 struct v4l2_subdev sd;
175 struct media_pad pads[ADV76XX_PAD_MAX];
176 unsigned int source_pad;
177
178 struct v4l2_ctrl_handler hdl;
179
180 enum adv76xx_pad selected_input;
181
182 struct v4l2_dv_timings timings;
183 const struct adv76xx_format_info *format;
184
185 struct {
186 u8 edid[ADV76XX_MAX_EDID_BLOCKS * 128];
187 u32 present;
188 unsigned blocks;
189 } edid;
190 u16 spa_port_a[2];
191 struct v4l2_fract aspect_ratio;
192 u32 rgb_quantization_range;
193 struct delayed_work delayed_work_enable_hotplug;
194 bool restart_stdi_once;
195
196
197 struct cec_adapter *cec_adap;
198 u8 cec_addr[ADV76XX_MAX_ADDRS];
199 u8 cec_valid_addrs;
200 bool cec_enabled_adap;
201
202
203 struct i2c_client *i2c_clients[ADV76XX_PAGE_MAX];
204
205
206 struct regmap *regmap[ADV76XX_PAGE_MAX];
207
208
209 struct v4l2_ctrl *detect_tx_5v_ctrl;
210 struct v4l2_ctrl *analog_sampling_phase_ctrl;
211 struct v4l2_ctrl *free_run_color_manual_ctrl;
212 struct v4l2_ctrl *free_run_color_ctrl;
213 struct v4l2_ctrl *rgb_quantization_range_ctrl;
214};
215
216static bool adv76xx_has_afe(struct adv76xx_state *state)
217{
218 return state->info->has_afe;
219}
220
221
222static const struct v4l2_dv_timings adv76xx_timings_exceptions[] = {
223 V4L2_DV_BT_CEA_1280X720P30,
224 { }
225};
226
227static bool adv76xx_check_dv_timings(const struct v4l2_dv_timings *t, void *hdl)
228{
229 int i;
230
231 for (i = 0; adv76xx_timings_exceptions[i].bt.width; i++)
232 if (v4l2_match_dv_timings(t, adv76xx_timings_exceptions + i, 0, false))
233 return false;
234 return true;
235}
236
237struct adv76xx_video_standards {
238 struct v4l2_dv_timings timings;
239 u8 vid_std;
240 u8 v_freq;
241};
242
243
244static const struct adv76xx_video_standards adv7604_prim_mode_comp[] = {
245
246 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
247 { V4L2_DV_BT_CEA_1280X720P50, 0x19, 0x01 },
248 { V4L2_DV_BT_CEA_1280X720P60, 0x19, 0x00 },
249 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
250 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
251 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
252 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
253 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
254
255 { },
256};
257
258
259static const struct adv76xx_video_standards adv7604_prim_mode_gr[] = {
260 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
261 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
262 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
263 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
264 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
265 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
266 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
267 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
268 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
269 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
270 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
271 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
272 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
273 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
274 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
275 { V4L2_DV_BT_DMT_1360X768P60, 0x12, 0x00 },
276 { V4L2_DV_BT_DMT_1366X768P60, 0x13, 0x00 },
277 { V4L2_DV_BT_DMT_1400X1050P60, 0x14, 0x00 },
278 { V4L2_DV_BT_DMT_1400X1050P75, 0x15, 0x00 },
279 { V4L2_DV_BT_DMT_1600X1200P60, 0x16, 0x00 },
280
281 { V4L2_DV_BT_DMT_1680X1050P60, 0x18, 0x00 },
282 { V4L2_DV_BT_DMT_1920X1200P60_RB, 0x19, 0x00 },
283 { },
284};
285
286
287static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_comp[] = {
288 { V4L2_DV_BT_CEA_720X480P59_94, 0x0a, 0x00 },
289 { V4L2_DV_BT_CEA_720X576P50, 0x0b, 0x00 },
290 { V4L2_DV_BT_CEA_1280X720P50, 0x13, 0x01 },
291 { V4L2_DV_BT_CEA_1280X720P60, 0x13, 0x00 },
292 { V4L2_DV_BT_CEA_1920X1080P24, 0x1e, 0x04 },
293 { V4L2_DV_BT_CEA_1920X1080P25, 0x1e, 0x03 },
294 { V4L2_DV_BT_CEA_1920X1080P30, 0x1e, 0x02 },
295 { V4L2_DV_BT_CEA_1920X1080P50, 0x1e, 0x01 },
296 { V4L2_DV_BT_CEA_1920X1080P60, 0x1e, 0x00 },
297 { },
298};
299
300
301static const struct adv76xx_video_standards adv76xx_prim_mode_hdmi_gr[] = {
302 { V4L2_DV_BT_DMT_640X480P60, 0x08, 0x00 },
303 { V4L2_DV_BT_DMT_640X480P72, 0x09, 0x00 },
304 { V4L2_DV_BT_DMT_640X480P75, 0x0a, 0x00 },
305 { V4L2_DV_BT_DMT_640X480P85, 0x0b, 0x00 },
306 { V4L2_DV_BT_DMT_800X600P56, 0x00, 0x00 },
307 { V4L2_DV_BT_DMT_800X600P60, 0x01, 0x00 },
308 { V4L2_DV_BT_DMT_800X600P72, 0x02, 0x00 },
309 { V4L2_DV_BT_DMT_800X600P75, 0x03, 0x00 },
310 { V4L2_DV_BT_DMT_800X600P85, 0x04, 0x00 },
311 { V4L2_DV_BT_DMT_1024X768P60, 0x0c, 0x00 },
312 { V4L2_DV_BT_DMT_1024X768P70, 0x0d, 0x00 },
313 { V4L2_DV_BT_DMT_1024X768P75, 0x0e, 0x00 },
314 { V4L2_DV_BT_DMT_1024X768P85, 0x0f, 0x00 },
315 { V4L2_DV_BT_DMT_1280X1024P60, 0x05, 0x00 },
316 { V4L2_DV_BT_DMT_1280X1024P75, 0x06, 0x00 },
317 { },
318};
319
320static const struct v4l2_event adv76xx_ev_fmt = {
321 .type = V4L2_EVENT_SOURCE_CHANGE,
322 .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
323};
324
325
326
327static inline struct adv76xx_state *to_state(struct v4l2_subdev *sd)
328{
329 return container_of(sd, struct adv76xx_state, sd);
330}
331
332static inline unsigned htotal(const struct v4l2_bt_timings *t)
333{
334 return V4L2_DV_BT_FRAME_WIDTH(t);
335}
336
337static inline unsigned vtotal(const struct v4l2_bt_timings *t)
338{
339 return V4L2_DV_BT_FRAME_HEIGHT(t);
340}
341
342
343
344static int adv76xx_read_check(struct adv76xx_state *state,
345 int client_page, u8 reg)
346{
347 struct i2c_client *client = state->i2c_clients[client_page];
348 int err;
349 unsigned int val;
350
351 err = regmap_read(state->regmap[client_page], reg, &val);
352
353 if (err) {
354 v4l_err(client, "error reading %02x, %02x\n",
355 client->addr, reg);
356 return err;
357 }
358 return val;
359}
360
361
362
363
364
365
366
367static int adv76xx_write_block(struct adv76xx_state *state, int client_page,
368 unsigned int init_reg, const void *val,
369 size_t val_len)
370{
371 struct regmap *regmap = state->regmap[client_page];
372
373 if (val_len > I2C_SMBUS_BLOCK_MAX)
374 val_len = I2C_SMBUS_BLOCK_MAX;
375
376 return regmap_raw_write(regmap, init_reg, val, val_len);
377}
378
379
380
381static inline int io_read(struct v4l2_subdev *sd, u8 reg)
382{
383 struct adv76xx_state *state = to_state(sd);
384
385 return adv76xx_read_check(state, ADV76XX_PAGE_IO, reg);
386}
387
388static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)
389{
390 struct adv76xx_state *state = to_state(sd);
391
392 return regmap_write(state->regmap[ADV76XX_PAGE_IO], reg, val);
393}
394
395static inline int io_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
396 u8 val)
397{
398 return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);
399}
400
401static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)
402{
403 struct adv76xx_state *state = to_state(sd);
404
405 return adv76xx_read_check(state, ADV7604_PAGE_AVLINK, reg);
406}
407
408static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)
409{
410 struct adv76xx_state *state = to_state(sd);
411
412 return regmap_write(state->regmap[ADV7604_PAGE_AVLINK], reg, val);
413}
414
415static inline int cec_read(struct v4l2_subdev *sd, u8 reg)
416{
417 struct adv76xx_state *state = to_state(sd);
418
419 return adv76xx_read_check(state, ADV76XX_PAGE_CEC, reg);
420}
421
422static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)
423{
424 struct adv76xx_state *state = to_state(sd);
425
426 return regmap_write(state->regmap[ADV76XX_PAGE_CEC], reg, val);
427}
428
429static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask,
430 u8 val)
431{
432 return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);
433}
434
435static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)
436{
437 struct adv76xx_state *state = to_state(sd);
438
439 return adv76xx_read_check(state, ADV76XX_PAGE_INFOFRAME, reg);
440}
441
442static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
443{
444 struct adv76xx_state *state = to_state(sd);
445
446 return regmap_write(state->regmap[ADV76XX_PAGE_INFOFRAME], reg, val);
447}
448
449static inline int afe_read(struct v4l2_subdev *sd, u8 reg)
450{
451 struct adv76xx_state *state = to_state(sd);
452
453 return adv76xx_read_check(state, ADV76XX_PAGE_AFE, reg);
454}
455
456static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)
457{
458 struct adv76xx_state *state = to_state(sd);
459
460 return regmap_write(state->regmap[ADV76XX_PAGE_AFE], reg, val);
461}
462
463static inline int rep_read(struct v4l2_subdev *sd, u8 reg)
464{
465 struct adv76xx_state *state = to_state(sd);
466
467 return adv76xx_read_check(state, ADV76XX_PAGE_REP, reg);
468}
469
470static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)
471{
472 struct adv76xx_state *state = to_state(sd);
473
474 return regmap_write(state->regmap[ADV76XX_PAGE_REP], reg, val);
475}
476
477static inline int rep_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
478{
479 return rep_write(sd, reg, (rep_read(sd, reg) & ~mask) | val);
480}
481
482static inline int edid_read(struct v4l2_subdev *sd, u8 reg)
483{
484 struct adv76xx_state *state = to_state(sd);
485
486 return adv76xx_read_check(state, ADV76XX_PAGE_EDID, reg);
487}
488
489static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)
490{
491 struct adv76xx_state *state = to_state(sd);
492
493 return regmap_write(state->regmap[ADV76XX_PAGE_EDID], reg, val);
494}
495
496static inline int edid_write_block(struct v4l2_subdev *sd,
497 unsigned int total_len, const u8 *val)
498{
499 struct adv76xx_state *state = to_state(sd);
500 int err = 0;
501 int i = 0;
502 int len = 0;
503
504 v4l2_dbg(2, debug, sd, "%s: write EDID block (%d byte)\n",
505 __func__, total_len);
506
507 while (!err && i < total_len) {
508 len = (total_len - i) > I2C_SMBUS_BLOCK_MAX ?
509 I2C_SMBUS_BLOCK_MAX :
510 (total_len - i);
511
512 err = adv76xx_write_block(state, ADV76XX_PAGE_EDID,
513 i, val + i, len);
514 i += len;
515 }
516
517 return err;
518}
519
520static void adv76xx_set_hpd(struct adv76xx_state *state, unsigned int hpd)
521{
522 const struct adv76xx_chip_info *info = state->info;
523 unsigned int i;
524
525 if (info->type == ADV7604) {
526 for (i = 0; i < state->info->num_dv_ports; ++i)
527 gpiod_set_value_cansleep(state->hpd_gpio[i], hpd & BIT(i));
528 } else {
529 for (i = 0; i < state->info->num_dv_ports; ++i)
530 io_write_clr_set(&state->sd, 0x20, 0x80 >> i,
531 (!!(hpd & BIT(i))) << (7 - i));
532 }
533
534 v4l2_subdev_notify(&state->sd, ADV76XX_HOTPLUG, &hpd);
535}
536
537static void adv76xx_delayed_work_enable_hotplug(struct work_struct *work)
538{
539 struct delayed_work *dwork = to_delayed_work(work);
540 struct adv76xx_state *state = container_of(dwork, struct adv76xx_state,
541 delayed_work_enable_hotplug);
542 struct v4l2_subdev *sd = &state->sd;
543
544 v4l2_dbg(2, debug, sd, "%s: enable hotplug\n", __func__);
545
546 adv76xx_set_hpd(state, state->edid.present);
547}
548
549static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)
550{
551 struct adv76xx_state *state = to_state(sd);
552
553 return adv76xx_read_check(state, ADV76XX_PAGE_HDMI, reg);
554}
555
556static u16 hdmi_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
557{
558 return ((hdmi_read(sd, reg) << 8) | hdmi_read(sd, reg + 1)) & mask;
559}
560
561static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)
562{
563 struct adv76xx_state *state = to_state(sd);
564
565 return regmap_write(state->regmap[ADV76XX_PAGE_HDMI], reg, val);
566}
567
568static inline int hdmi_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
569{
570 return hdmi_write(sd, reg, (hdmi_read(sd, reg) & ~mask) | val);
571}
572
573static inline int test_write(struct v4l2_subdev *sd, u8 reg, u8 val)
574{
575 struct adv76xx_state *state = to_state(sd);
576
577 return regmap_write(state->regmap[ADV76XX_PAGE_TEST], reg, val);
578}
579
580static inline int cp_read(struct v4l2_subdev *sd, u8 reg)
581{
582 struct adv76xx_state *state = to_state(sd);
583
584 return adv76xx_read_check(state, ADV76XX_PAGE_CP, reg);
585}
586
587static u16 cp_read16(struct v4l2_subdev *sd, u8 reg, u16 mask)
588{
589 return ((cp_read(sd, reg) << 8) | cp_read(sd, reg + 1)) & mask;
590}
591
592static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
593{
594 struct adv76xx_state *state = to_state(sd);
595
596 return regmap_write(state->regmap[ADV76XX_PAGE_CP], reg, val);
597}
598
599static inline int cp_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)
600{
601 return cp_write(sd, reg, (cp_read(sd, reg) & ~mask) | val);
602}
603
604static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)
605{
606 struct adv76xx_state *state = to_state(sd);
607
608 return adv76xx_read_check(state, ADV7604_PAGE_VDP, reg);
609}
610
611static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)
612{
613 struct adv76xx_state *state = to_state(sd);
614
615 return regmap_write(state->regmap[ADV7604_PAGE_VDP], reg, val);
616}
617
618#define ADV76XX_REG(page, offset) (((page) << 8) | (offset))
619#define ADV76XX_REG_SEQ_TERM 0xffff
620
621#ifdef CONFIG_VIDEO_ADV_DEBUG
622static int adv76xx_read_reg(struct v4l2_subdev *sd, unsigned int reg)
623{
624 struct adv76xx_state *state = to_state(sd);
625 unsigned int page = reg >> 8;
626 unsigned int val;
627 int err;
628
629 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
630 return -EINVAL;
631
632 reg &= 0xff;
633 err = regmap_read(state->regmap[page], reg, &val);
634
635 return err ? err : val;
636}
637#endif
638
639static int adv76xx_write_reg(struct v4l2_subdev *sd, unsigned int reg, u8 val)
640{
641 struct adv76xx_state *state = to_state(sd);
642 unsigned int page = reg >> 8;
643
644 if (page >= ADV76XX_PAGE_MAX || !(BIT(page) & state->info->page_mask))
645 return -EINVAL;
646
647 reg &= 0xff;
648
649 return regmap_write(state->regmap[page], reg, val);
650}
651
652static void adv76xx_write_reg_seq(struct v4l2_subdev *sd,
653 const struct adv76xx_reg_seq *reg_seq)
654{
655 unsigned int i;
656
657 for (i = 0; reg_seq[i].reg != ADV76XX_REG_SEQ_TERM; i++)
658 adv76xx_write_reg(sd, reg_seq[i].reg, reg_seq[i].val);
659}
660
661
662
663
664
665static const struct adv76xx_format_info adv7604_formats[] = {
666 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
667 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
668 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
669 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
670 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
671 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
672 { MEDIA_BUS_FMT_YUYV10_2X10, ADV76XX_OP_CH_SEL_RGB, false, false,
673 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
674 { MEDIA_BUS_FMT_YVYU10_2X10, ADV76XX_OP_CH_SEL_RGB, false, true,
675 ADV76XX_OP_MODE_SEL_SDR_422 | ADV7604_OP_FORMAT_SEL_10BIT },
676 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
677 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
678 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
679 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
680 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
681 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
682 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
683 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
684 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
685 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
686 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
687 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
688 { MEDIA_BUS_FMT_UYVY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, false,
689 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
690 { MEDIA_BUS_FMT_VYUY10_1X20, ADV76XX_OP_CH_SEL_RBG, false, true,
691 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
692 { MEDIA_BUS_FMT_YUYV10_1X20, ADV76XX_OP_CH_SEL_RGB, false, false,
693 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
694 { MEDIA_BUS_FMT_YVYU10_1X20, ADV76XX_OP_CH_SEL_RGB, false, true,
695 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV7604_OP_FORMAT_SEL_10BIT },
696 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
697 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
698 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
699 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
700 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
701 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
702 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
703 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
704};
705
706static const struct adv76xx_format_info adv7611_formats[] = {
707 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
708 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
709 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
710 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
711 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
712 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
713 { MEDIA_BUS_FMT_YUYV12_2X12, ADV76XX_OP_CH_SEL_RGB, false, false,
714 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
715 { MEDIA_BUS_FMT_YVYU12_2X12, ADV76XX_OP_CH_SEL_RGB, false, true,
716 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_12BIT },
717 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
718 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
719 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
720 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
721 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
722 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
723 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
724 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
725 { MEDIA_BUS_FMT_UYVY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, false,
726 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
727 { MEDIA_BUS_FMT_VYUY12_1X24, ADV76XX_OP_CH_SEL_RBG, false, true,
728 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
729 { MEDIA_BUS_FMT_YUYV12_1X24, ADV76XX_OP_CH_SEL_RGB, false, false,
730 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
731 { MEDIA_BUS_FMT_YVYU12_1X24, ADV76XX_OP_CH_SEL_RGB, false, true,
732 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_12BIT },
733};
734
735static const struct adv76xx_format_info adv7612_formats[] = {
736 { MEDIA_BUS_FMT_RGB888_1X24, ADV76XX_OP_CH_SEL_RGB, true, false,
737 ADV76XX_OP_MODE_SEL_SDR_444 | ADV76XX_OP_FORMAT_SEL_8BIT },
738 { MEDIA_BUS_FMT_YUYV8_2X8, ADV76XX_OP_CH_SEL_RGB, false, false,
739 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
740 { MEDIA_BUS_FMT_YVYU8_2X8, ADV76XX_OP_CH_SEL_RGB, false, true,
741 ADV76XX_OP_MODE_SEL_SDR_422 | ADV76XX_OP_FORMAT_SEL_8BIT },
742 { MEDIA_BUS_FMT_UYVY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, false,
743 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
744 { MEDIA_BUS_FMT_VYUY8_1X16, ADV76XX_OP_CH_SEL_RBG, false, true,
745 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
746 { MEDIA_BUS_FMT_YUYV8_1X16, ADV76XX_OP_CH_SEL_RGB, false, false,
747 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
748 { MEDIA_BUS_FMT_YVYU8_1X16, ADV76XX_OP_CH_SEL_RGB, false, true,
749 ADV76XX_OP_MODE_SEL_SDR_422_2X | ADV76XX_OP_FORMAT_SEL_8BIT },
750};
751
752static const struct adv76xx_format_info *
753adv76xx_format_info(struct adv76xx_state *state, u32 code)
754{
755 unsigned int i;
756
757 for (i = 0; i < state->info->nformats; ++i) {
758 if (state->info->formats[i].code == code)
759 return &state->info->formats[i];
760 }
761
762 return NULL;
763}
764
765
766
767static inline bool is_analog_input(struct v4l2_subdev *sd)
768{
769 struct adv76xx_state *state = to_state(sd);
770
771 return state->selected_input == ADV7604_PAD_VGA_RGB ||
772 state->selected_input == ADV7604_PAD_VGA_COMP;
773}
774
775static inline bool is_digital_input(struct v4l2_subdev *sd)
776{
777 struct adv76xx_state *state = to_state(sd);
778
779 return state->selected_input == ADV76XX_PAD_HDMI_PORT_A ||
780 state->selected_input == ADV7604_PAD_HDMI_PORT_B ||
781 state->selected_input == ADV7604_PAD_HDMI_PORT_C ||
782 state->selected_input == ADV7604_PAD_HDMI_PORT_D;
783}
784
785static const struct v4l2_dv_timings_cap adv7604_timings_cap_analog = {
786 .type = V4L2_DV_BT_656_1120,
787
788 .reserved = { 0 },
789 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 170000000,
790 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
791 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
792 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
793 V4L2_DV_BT_CAP_CUSTOM)
794};
795
796static const struct v4l2_dv_timings_cap adv76xx_timings_cap_digital = {
797 .type = V4L2_DV_BT_656_1120,
798
799 .reserved = { 0 },
800 V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 25000000, 225000000,
801 V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
802 V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
803 V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
804 V4L2_DV_BT_CAP_CUSTOM)
805};
806
807
808
809
810
811static const struct v4l2_dv_timings_cap *
812adv76xx_get_dv_timings_cap(struct v4l2_subdev *sd, int pad)
813{
814 if (pad == -1) {
815 struct adv76xx_state *state = to_state(sd);
816
817 pad = state->selected_input;
818 }
819
820 switch (pad) {
821 case ADV76XX_PAD_HDMI_PORT_A:
822 case ADV7604_PAD_HDMI_PORT_B:
823 case ADV7604_PAD_HDMI_PORT_C:
824 case ADV7604_PAD_HDMI_PORT_D:
825 return &adv76xx_timings_cap_digital;
826
827 case ADV7604_PAD_VGA_RGB:
828 case ADV7604_PAD_VGA_COMP:
829 default:
830 return &adv7604_timings_cap_analog;
831 }
832}
833
834
835
836
837#ifdef CONFIG_VIDEO_ADV_DEBUG
838static void adv76xx_inv_register(struct v4l2_subdev *sd)
839{
840 v4l2_info(sd, "0x000-0x0ff: IO Map\n");
841 v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");
842 v4l2_info(sd, "0x200-0x2ff: CEC Map\n");
843 v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");
844 v4l2_info(sd, "0x400-0x4ff: ESDP Map\n");
845 v4l2_info(sd, "0x500-0x5ff: DPP Map\n");
846 v4l2_info(sd, "0x600-0x6ff: AFE Map\n");
847 v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");
848 v4l2_info(sd, "0x800-0x8ff: EDID Map\n");
849 v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");
850 v4l2_info(sd, "0xa00-0xaff: Test Map\n");
851 v4l2_info(sd, "0xb00-0xbff: CP Map\n");
852 v4l2_info(sd, "0xc00-0xcff: VDP Map\n");
853}
854
855static int adv76xx_g_register(struct v4l2_subdev *sd,
856 struct v4l2_dbg_register *reg)
857{
858 int ret;
859
860 ret = adv76xx_read_reg(sd, reg->reg);
861 if (ret < 0) {
862 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
863 adv76xx_inv_register(sd);
864 return ret;
865 }
866
867 reg->size = 1;
868 reg->val = ret;
869
870 return 0;
871}
872
873static int adv76xx_s_register(struct v4l2_subdev *sd,
874 const struct v4l2_dbg_register *reg)
875{
876 int ret;
877
878 ret = adv76xx_write_reg(sd, reg->reg, reg->val);
879 if (ret < 0) {
880 v4l2_info(sd, "Register %03llx not supported\n", reg->reg);
881 adv76xx_inv_register(sd);
882 return ret;
883 }
884
885 return 0;
886}
887#endif
888
889static unsigned int adv7604_read_cable_det(struct v4l2_subdev *sd)
890{
891 u8 value = io_read(sd, 0x6f);
892
893 return ((value & 0x10) >> 4)
894 | ((value & 0x08) >> 2)
895 | ((value & 0x04) << 0)
896 | ((value & 0x02) << 2);
897}
898
899static unsigned int adv7611_read_cable_det(struct v4l2_subdev *sd)
900{
901 u8 value = io_read(sd, 0x6f);
902
903 return value & 1;
904}
905
906static unsigned int adv7612_read_cable_det(struct v4l2_subdev *sd)
907{
908
909
910
911 u8 value = io_read(sd, 0x6f);
912
913 return value & 1;
914}
915
916static int adv76xx_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)
917{
918 struct adv76xx_state *state = to_state(sd);
919 const struct adv76xx_chip_info *info = state->info;
920 u16 cable_det = info->read_cable_det(sd);
921
922 return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);
923}
924
925static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,
926 u8 prim_mode,
927 const struct adv76xx_video_standards *predef_vid_timings,
928 const struct v4l2_dv_timings *timings)
929{
930 int i;
931
932 for (i = 0; predef_vid_timings[i].timings.bt.width; i++) {
933 if (!v4l2_match_dv_timings(timings, &predef_vid_timings[i].timings,
934 is_digital_input(sd) ? 250000 : 1000000, false))
935 continue;
936 io_write(sd, 0x00, predef_vid_timings[i].vid_std);
937 io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) +
938 prim_mode);
939 return 0;
940 }
941
942 return -1;
943}
944
945static int configure_predefined_video_timings(struct v4l2_subdev *sd,
946 struct v4l2_dv_timings *timings)
947{
948 struct adv76xx_state *state = to_state(sd);
949 int err;
950
951 v4l2_dbg(1, debug, sd, "%s", __func__);
952
953 if (adv76xx_has_afe(state)) {
954
955 io_write(sd, 0x16, 0x43);
956 io_write(sd, 0x17, 0x5a);
957 }
958
959 cp_write_clr_set(sd, 0x81, 0x10, 0x00);
960 cp_write(sd, 0x8f, 0x00);
961 cp_write(sd, 0x90, 0x00);
962 cp_write(sd, 0xa2, 0x00);
963 cp_write(sd, 0xa3, 0x00);
964 cp_write(sd, 0xa4, 0x00);
965 cp_write(sd, 0xa5, 0x00);
966 cp_write(sd, 0xa6, 0x00);
967 cp_write(sd, 0xa7, 0x00);
968 cp_write(sd, 0xab, 0x00);
969 cp_write(sd, 0xac, 0x00);
970
971 if (is_analog_input(sd)) {
972 err = find_and_set_predefined_video_timings(sd,
973 0x01, adv7604_prim_mode_comp, timings);
974 if (err)
975 err = find_and_set_predefined_video_timings(sd,
976 0x02, adv7604_prim_mode_gr, timings);
977 } else if (is_digital_input(sd)) {
978 err = find_and_set_predefined_video_timings(sd,
979 0x05, adv76xx_prim_mode_hdmi_comp, timings);
980 if (err)
981 err = find_and_set_predefined_video_timings(sd,
982 0x06, adv76xx_prim_mode_hdmi_gr, timings);
983 } else {
984 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
985 __func__, state->selected_input);
986 err = -1;
987 }
988
989
990 return err;
991}
992
993static void configure_custom_video_timings(struct v4l2_subdev *sd,
994 const struct v4l2_bt_timings *bt)
995{
996 struct adv76xx_state *state = to_state(sd);
997 u32 width = htotal(bt);
998 u32 height = vtotal(bt);
999 u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;
1000 u16 cp_start_eav = width - bt->hfrontporch;
1001 u16 cp_start_vbi = height - bt->vfrontporch;
1002 u16 cp_end_vbi = bt->vsync + bt->vbackporch;
1003 u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?
1004 ((width * (ADV76XX_FSC / 100)) / ((u32)bt->pixelclock / 100)) : 0;
1005 const u8 pll[2] = {
1006 0xc0 | ((width >> 8) & 0x1f),
1007 width & 0xff
1008 };
1009
1010 v4l2_dbg(2, debug, sd, "%s\n", __func__);
1011
1012 if (is_analog_input(sd)) {
1013
1014 io_write(sd, 0x00, 0x07);
1015 io_write(sd, 0x01, 0x02);
1016
1017 cp_write_clr_set(sd, 0x81, 0x10, 0x10);
1018
1019
1020
1021
1022 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_IO],
1023 0x16, pll, 2))
1024 v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");
1025
1026
1027 cp_write(sd, 0xa2, (cp_start_sav >> 4) & 0xff);
1028 cp_write(sd, 0xa3, ((cp_start_sav & 0x0f) << 4) |
1029 ((cp_start_eav >> 8) & 0x0f));
1030 cp_write(sd, 0xa4, cp_start_eav & 0xff);
1031
1032
1033 cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);
1034 cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |
1035 ((cp_end_vbi >> 8) & 0xf));
1036 cp_write(sd, 0xa7, cp_end_vbi & 0xff);
1037 } else if (is_digital_input(sd)) {
1038
1039
1040 io_write(sd, 0x00, 0x02);
1041 io_write(sd, 0x01, 0x06);
1042 } else {
1043 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1044 __func__, state->selected_input);
1045 }
1046
1047 cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);
1048 cp_write(sd, 0x90, ch1_fr_ll & 0xff);
1049 cp_write(sd, 0xab, (height >> 4) & 0xff);
1050 cp_write(sd, 0xac, (height & 0x0f) << 4);
1051}
1052
1053static void adv76xx_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b, u16 offset_c)
1054{
1055 struct adv76xx_state *state = to_state(sd);
1056 u8 offset_buf[4];
1057
1058 if (auto_offset) {
1059 offset_a = 0x3ff;
1060 offset_b = 0x3ff;
1061 offset_c = 0x3ff;
1062 }
1063
1064 v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",
1065 __func__, auto_offset ? "Auto" : "Manual",
1066 offset_a, offset_b, offset_c);
1067
1068 offset_buf[0] = (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);
1069 offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);
1070 offset_buf[2] = ((offset_b & 0x03f) << 2) | ((offset_c & 0x300) >> 8);
1071 offset_buf[3] = offset_c & 0x0ff;
1072
1073
1074 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1075 0x77, offset_buf, 4))
1076 v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);
1077}
1078
1079static void adv76xx_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 gain_c)
1080{
1081 struct adv76xx_state *state = to_state(sd);
1082 u8 gain_buf[4];
1083 u8 gain_man = 1;
1084 u8 agc_mode_man = 1;
1085
1086 if (auto_gain) {
1087 gain_man = 0;
1088 agc_mode_man = 0;
1089 gain_a = 0x100;
1090 gain_b = 0x100;
1091 gain_c = 0x100;
1092 }
1093
1094 v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",
1095 __func__, auto_gain ? "Auto" : "Manual",
1096 gain_a, gain_b, gain_c);
1097
1098 gain_buf[0] = ((gain_man << 7) | (agc_mode_man << 6) | ((gain_a & 0x3f0) >> 4));
1099 gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));
1100 gain_buf[2] = (((gain_b & 0x03f) << 2) | ((gain_c & 0x300) >> 8));
1101 gain_buf[3] = ((gain_c & 0x0ff));
1102
1103
1104 if (regmap_raw_write(state->regmap[ADV76XX_PAGE_CP],
1105 0x73, gain_buf, 4))
1106 v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);
1107}
1108
1109static void set_rgb_quantization_range(struct v4l2_subdev *sd)
1110{
1111 struct adv76xx_state *state = to_state(sd);
1112 bool rgb_output = io_read(sd, 0x02) & 0x02;
1113 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1114 u8 y = HDMI_COLORSPACE_RGB;
1115
1116 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1117 y = infoframe_read(sd, 0x01) >> 5;
1118
1119 v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",
1120 __func__, state->rgb_quantization_range,
1121 rgb_output, hdmi_signal);
1122
1123 adv76xx_set_gain(sd, true, 0x0, 0x0, 0x0);
1124 adv76xx_set_offset(sd, true, 0x0, 0x0, 0x0);
1125 io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);
1126
1127 switch (state->rgb_quantization_range) {
1128 case V4L2_DV_RGB_RANGE_AUTO:
1129 if (state->selected_input == ADV7604_PAD_VGA_RGB) {
1130
1131
1132 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1133 break;
1134 }
1135
1136 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1137
1138
1139 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1140 break;
1141 }
1142
1143 if (hdmi_signal) {
1144
1145
1146 io_write_clr_set(sd, 0x02, 0xf0, 0xf0);
1147 break;
1148 }
1149
1150
1151
1152
1153 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {
1154
1155 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1156 } else {
1157
1158 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1159
1160 if (is_digital_input(sd) && rgb_output) {
1161 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1162 } else {
1163 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1164 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1165 }
1166 }
1167 break;
1168 case V4L2_DV_RGB_RANGE_LIMITED:
1169 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1170
1171 io_write_clr_set(sd, 0x02, 0xf0, 0x20);
1172 break;
1173 }
1174
1175 if (y != HDMI_COLORSPACE_RGB)
1176 break;
1177
1178
1179 io_write_clr_set(sd, 0x02, 0xf0, 0x00);
1180
1181 break;
1182 case V4L2_DV_RGB_RANGE_FULL:
1183 if (state->selected_input == ADV7604_PAD_VGA_COMP) {
1184
1185 io_write_clr_set(sd, 0x02, 0xf0, 0x60);
1186 break;
1187 }
1188
1189 if (y != HDMI_COLORSPACE_RGB)
1190 break;
1191
1192
1193 io_write_clr_set(sd, 0x02, 0xf0, 0x10);
1194
1195 if (is_analog_input(sd) || hdmi_signal)
1196 break;
1197
1198
1199 if (rgb_output) {
1200 adv76xx_set_offset(sd, false, 0x40, 0x40, 0x40);
1201 } else {
1202 adv76xx_set_gain(sd, false, 0xe0, 0xe0, 0xe0);
1203 adv76xx_set_offset(sd, false, 0x70, 0x70, 0x70);
1204 }
1205 break;
1206 }
1207}
1208
1209static int adv76xx_s_ctrl(struct v4l2_ctrl *ctrl)
1210{
1211 struct v4l2_subdev *sd =
1212 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1213
1214 struct adv76xx_state *state = to_state(sd);
1215
1216 switch (ctrl->id) {
1217 case V4L2_CID_BRIGHTNESS:
1218 cp_write(sd, 0x3c, ctrl->val);
1219 return 0;
1220 case V4L2_CID_CONTRAST:
1221 cp_write(sd, 0x3a, ctrl->val);
1222 return 0;
1223 case V4L2_CID_SATURATION:
1224 cp_write(sd, 0x3b, ctrl->val);
1225 return 0;
1226 case V4L2_CID_HUE:
1227 cp_write(sd, 0x3d, ctrl->val);
1228 return 0;
1229 case V4L2_CID_DV_RX_RGB_RANGE:
1230 state->rgb_quantization_range = ctrl->val;
1231 set_rgb_quantization_range(sd);
1232 return 0;
1233 case V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE:
1234 if (!adv76xx_has_afe(state))
1235 return -EINVAL;
1236
1237
1238
1239
1240 afe_write(sd, 0xc8, ctrl->val);
1241 return 0;
1242 case V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL:
1243
1244
1245 cp_write_clr_set(sd, 0xbf, 0x04, ctrl->val << 2);
1246 return 0;
1247 case V4L2_CID_ADV_RX_FREE_RUN_COLOR:
1248 cp_write(sd, 0xc0, (ctrl->val & 0xff0000) >> 16);
1249 cp_write(sd, 0xc1, (ctrl->val & 0x00ff00) >> 8);
1250 cp_write(sd, 0xc2, (u8)(ctrl->val & 0x0000ff));
1251 return 0;
1252 }
1253 return -EINVAL;
1254}
1255
1256static int adv76xx_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1257{
1258 struct v4l2_subdev *sd =
1259 &container_of(ctrl->handler, struct adv76xx_state, hdl)->sd;
1260
1261 if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {
1262 ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;
1263 if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))
1264 ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;
1265 return 0;
1266 }
1267 return -EINVAL;
1268}
1269
1270
1271
1272static inline bool no_power(struct v4l2_subdev *sd)
1273{
1274
1275 return io_read(sd, 0x0c) & 0x24;
1276}
1277
1278static inline bool no_signal_tmds(struct v4l2_subdev *sd)
1279{
1280 struct adv76xx_state *state = to_state(sd);
1281
1282 return !(io_read(sd, 0x6a) & (0x10 >> state->selected_input));
1283}
1284
1285static inline bool no_lock_tmds(struct v4l2_subdev *sd)
1286{
1287 struct adv76xx_state *state = to_state(sd);
1288 const struct adv76xx_chip_info *info = state->info;
1289
1290 return (io_read(sd, 0x6a) & info->tdms_lock_mask) != info->tdms_lock_mask;
1291}
1292
1293static inline bool is_hdmi(struct v4l2_subdev *sd)
1294{
1295 return hdmi_read(sd, 0x05) & 0x80;
1296}
1297
1298static inline bool no_lock_sspd(struct v4l2_subdev *sd)
1299{
1300 struct adv76xx_state *state = to_state(sd);
1301
1302
1303
1304
1305
1306 if (adv76xx_has_afe(state))
1307 return false;
1308
1309
1310 return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0);
1311}
1312
1313static inline bool no_lock_stdi(struct v4l2_subdev *sd)
1314{
1315
1316 return !(cp_read(sd, 0xb1) & 0x80);
1317}
1318
1319static inline bool no_signal(struct v4l2_subdev *sd)
1320{
1321 bool ret;
1322
1323 ret = no_power(sd);
1324
1325 ret |= no_lock_stdi(sd);
1326 ret |= no_lock_sspd(sd);
1327
1328 if (is_digital_input(sd)) {
1329 ret |= no_lock_tmds(sd);
1330 ret |= no_signal_tmds(sd);
1331 }
1332
1333 return ret;
1334}
1335
1336static inline bool no_lock_cp(struct v4l2_subdev *sd)
1337{
1338 struct adv76xx_state *state = to_state(sd);
1339
1340 if (!adv76xx_has_afe(state))
1341 return false;
1342
1343
1344
1345 return io_read(sd, 0x12) & 0x01;
1346}
1347
1348static inline bool in_free_run(struct v4l2_subdev *sd)
1349{
1350 return cp_read(sd, 0xff) & 0x10;
1351}
1352
1353static int adv76xx_g_input_status(struct v4l2_subdev *sd, u32 *status)
1354{
1355 *status = 0;
1356 *status |= no_power(sd) ? V4L2_IN_ST_NO_POWER : 0;
1357 *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
1358 if (!in_free_run(sd) && no_lock_cp(sd))
1359 *status |= is_digital_input(sd) ?
1360 V4L2_IN_ST_NO_SYNC : V4L2_IN_ST_NO_H_LOCK;
1361
1362 v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
1363
1364 return 0;
1365}
1366
1367
1368
1369struct stdi_readback {
1370 u16 bl, lcf, lcvs;
1371 u8 hs_pol, vs_pol;
1372 bool interlaced;
1373};
1374
1375static int stdi2dv_timings(struct v4l2_subdev *sd,
1376 struct stdi_readback *stdi,
1377 struct v4l2_dv_timings *timings)
1378{
1379 struct adv76xx_state *state = to_state(sd);
1380 u32 hfreq = (ADV76XX_FSC * 8) / stdi->bl;
1381 u32 pix_clk;
1382 int i;
1383
1384 for (i = 0; v4l2_dv_timings_presets[i].bt.width; i++) {
1385 const struct v4l2_bt_timings *bt = &v4l2_dv_timings_presets[i].bt;
1386
1387 if (!v4l2_valid_dv_timings(&v4l2_dv_timings_presets[i],
1388 adv76xx_get_dv_timings_cap(sd, -1),
1389 adv76xx_check_dv_timings, NULL))
1390 continue;
1391 if (vtotal(bt) != stdi->lcf + 1)
1392 continue;
1393 if (bt->vsync != stdi->lcvs)
1394 continue;
1395
1396 pix_clk = hfreq * htotal(bt);
1397
1398 if ((pix_clk < bt->pixelclock + 1000000) &&
1399 (pix_clk > bt->pixelclock - 1000000)) {
1400 *timings = v4l2_dv_timings_presets[i];
1401 return 0;
1402 }
1403 }
1404
1405 if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,
1406 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1407 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1408 false, timings))
1409 return 0;
1410 if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,
1411 (stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |
1412 (stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),
1413 false, state->aspect_ratio, timings))
1414 return 0;
1415
1416 v4l2_dbg(2, debug, sd,
1417 "%s: No format candidate found for lcvs = %d, lcf=%d, bl = %d, %chsync, %cvsync\n",
1418 __func__, stdi->lcvs, stdi->lcf, stdi->bl,
1419 stdi->hs_pol, stdi->vs_pol);
1420 return -1;
1421}
1422
1423
1424static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)
1425{
1426 struct adv76xx_state *state = to_state(sd);
1427 const struct adv76xx_chip_info *info = state->info;
1428 u8 polarity;
1429
1430 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1431 v4l2_dbg(2, debug, sd, "%s: STDI and/or SSPD not locked\n", __func__);
1432 return -1;
1433 }
1434
1435
1436 stdi->bl = cp_read16(sd, 0xb1, 0x3fff);
1437 stdi->lcf = cp_read16(sd, info->lcf_reg, 0x7ff);
1438 stdi->lcvs = cp_read(sd, 0xb3) >> 3;
1439 stdi->interlaced = io_read(sd, 0x12) & 0x10;
1440
1441 if (adv76xx_has_afe(state)) {
1442
1443 polarity = cp_read(sd, 0xb5);
1444 if ((polarity & 0x03) == 0x01) {
1445 stdi->hs_pol = polarity & 0x10
1446 ? (polarity & 0x08 ? '+' : '-') : 'x';
1447 stdi->vs_pol = polarity & 0x40
1448 ? (polarity & 0x20 ? '+' : '-') : 'x';
1449 } else {
1450 stdi->hs_pol = 'x';
1451 stdi->vs_pol = 'x';
1452 }
1453 } else {
1454 polarity = hdmi_read(sd, 0x05);
1455 stdi->hs_pol = polarity & 0x20 ? '+' : '-';
1456 stdi->vs_pol = polarity & 0x10 ? '+' : '-';
1457 }
1458
1459 if (no_lock_stdi(sd) || no_lock_sspd(sd)) {
1460 v4l2_dbg(2, debug, sd,
1461 "%s: signal lost during readout of STDI/SSPD\n", __func__);
1462 return -1;
1463 }
1464
1465 if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {
1466 v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);
1467 memset(stdi, 0, sizeof(struct stdi_readback));
1468 return -1;
1469 }
1470
1471 v4l2_dbg(2, debug, sd,
1472 "%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",
1473 __func__, stdi->lcf, stdi->bl, stdi->lcvs,
1474 stdi->hs_pol, stdi->vs_pol,
1475 stdi->interlaced ? "interlaced" : "progressive");
1476
1477 return 0;
1478}
1479
1480static int adv76xx_enum_dv_timings(struct v4l2_subdev *sd,
1481 struct v4l2_enum_dv_timings *timings)
1482{
1483 struct adv76xx_state *state = to_state(sd);
1484
1485 if (timings->pad >= state->source_pad)
1486 return -EINVAL;
1487
1488 return v4l2_enum_dv_timings_cap(timings,
1489 adv76xx_get_dv_timings_cap(sd, timings->pad),
1490 adv76xx_check_dv_timings, NULL);
1491}
1492
1493static int adv76xx_dv_timings_cap(struct v4l2_subdev *sd,
1494 struct v4l2_dv_timings_cap *cap)
1495{
1496 struct adv76xx_state *state = to_state(sd);
1497 unsigned int pad = cap->pad;
1498
1499 if (cap->pad >= state->source_pad)
1500 return -EINVAL;
1501
1502 *cap = *adv76xx_get_dv_timings_cap(sd, pad);
1503 cap->pad = pad;
1504
1505 return 0;
1506}
1507
1508
1509
1510static void adv76xx_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,
1511 struct v4l2_dv_timings *timings)
1512{
1513 v4l2_find_dv_timings_cap(timings, adv76xx_get_dv_timings_cap(sd, -1),
1514 is_digital_input(sd) ? 250000 : 1000000,
1515 adv76xx_check_dv_timings, NULL);
1516}
1517
1518static unsigned int adv7604_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1519{
1520 int a, b;
1521
1522 a = hdmi_read(sd, 0x06);
1523 b = hdmi_read(sd, 0x3b);
1524 if (a < 0 || b < 0)
1525 return 0;
1526
1527 return a * 1000000 + ((b & 0x30) >> 4) * 250000;
1528}
1529
1530static unsigned int adv7611_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1531{
1532 int a, b;
1533
1534 a = hdmi_read(sd, 0x51);
1535 b = hdmi_read(sd, 0x52);
1536 if (a < 0 || b < 0)
1537 return 0;
1538
1539 return ((a << 1) | (b >> 7)) * 1000000 + (b & 0x7f) * 1000000 / 128;
1540}
1541
1542static unsigned int adv76xx_read_hdmi_pixelclock(struct v4l2_subdev *sd)
1543{
1544 struct adv76xx_state *state = to_state(sd);
1545 const struct adv76xx_chip_info *info = state->info;
1546 unsigned int freq, bits_per_channel, pixelrepetition;
1547
1548 freq = info->read_hdmi_pixelclock(sd);
1549 if (is_hdmi(sd)) {
1550
1551 bits_per_channel = ((hdmi_read(sd, 0x0b) & 0x60) >> 4) + 8;
1552 pixelrepetition = (hdmi_read(sd, 0x05) & 0x0f) + 1;
1553
1554 freq = freq * 8 / bits_per_channel / pixelrepetition;
1555 }
1556
1557 return freq;
1558}
1559
1560static int adv76xx_query_dv_timings(struct v4l2_subdev *sd,
1561 struct v4l2_dv_timings *timings)
1562{
1563 struct adv76xx_state *state = to_state(sd);
1564 const struct adv76xx_chip_info *info = state->info;
1565 struct v4l2_bt_timings *bt = &timings->bt;
1566 struct stdi_readback stdi;
1567
1568 if (!timings)
1569 return -EINVAL;
1570
1571 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1572
1573 if (no_signal(sd)) {
1574 state->restart_stdi_once = true;
1575 v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
1576 return -ENOLINK;
1577 }
1578
1579
1580 if (read_stdi(sd, &stdi)) {
1581 v4l2_dbg(1, debug, sd, "%s: STDI/SSPD not locked\n", __func__);
1582 return -ENOLINK;
1583 }
1584 bt->interlaced = stdi.interlaced ?
1585 V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
1586
1587 if (is_digital_input(sd)) {
1588 bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;
1589 u8 vic = 0;
1590 u32 w, h;
1591
1592 w = hdmi_read16(sd, 0x07, info->linewidth_mask);
1593 h = hdmi_read16(sd, 0x09, info->field0_height_mask);
1594
1595 if (hdmi_signal && (io_read(sd, 0x60) & 1))
1596 vic = infoframe_read(sd, 0x04);
1597
1598 if (vic && v4l2_find_dv_timings_cea861_vic(timings, vic) &&
1599 bt->width == w && bt->height == h)
1600 goto found;
1601
1602 timings->type = V4L2_DV_BT_656_1120;
1603
1604 bt->width = w;
1605 bt->height = h;
1606 bt->pixelclock = adv76xx_read_hdmi_pixelclock(sd);
1607 bt->hfrontporch = hdmi_read16(sd, 0x20, info->hfrontporch_mask);
1608 bt->hsync = hdmi_read16(sd, 0x22, info->hsync_mask);
1609 bt->hbackporch = hdmi_read16(sd, 0x24, info->hbackporch_mask);
1610 bt->vfrontporch = hdmi_read16(sd, 0x2a,
1611 info->field0_vfrontporch_mask) / 2;
1612 bt->vsync = hdmi_read16(sd, 0x2e, info->field0_vsync_mask) / 2;
1613 bt->vbackporch = hdmi_read16(sd, 0x32,
1614 info->field0_vbackporch_mask) / 2;
1615 bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |
1616 ((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);
1617 if (bt->interlaced == V4L2_DV_INTERLACED) {
1618 bt->height += hdmi_read16(sd, 0x0b,
1619 info->field1_height_mask);
1620 bt->il_vfrontporch = hdmi_read16(sd, 0x2c,
1621 info->field1_vfrontporch_mask) / 2;
1622 bt->il_vsync = hdmi_read16(sd, 0x30,
1623 info->field1_vsync_mask) / 2;
1624 bt->il_vbackporch = hdmi_read16(sd, 0x34,
1625 info->field1_vbackporch_mask) / 2;
1626 }
1627 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1628 } else {
1629
1630
1631
1632
1633 if (!stdi2dv_timings(sd, &stdi, timings))
1634 goto found;
1635 stdi.lcvs += 1;
1636 v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);
1637 if (!stdi2dv_timings(sd, &stdi, timings))
1638 goto found;
1639 stdi.lcvs -= 2;
1640 v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);
1641 if (stdi2dv_timings(sd, &stdi, timings)) {
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651 if (state->restart_stdi_once) {
1652 v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);
1653
1654
1655 cp_write_clr_set(sd, 0x86, 0x06, 0x00);
1656
1657 cp_write_clr_set(sd, 0x86, 0x06, 0x04);
1658
1659 cp_write_clr_set(sd, 0x86, 0x06, 0x02);
1660 state->restart_stdi_once = false;
1661 return -ENOLINK;
1662 }
1663 v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);
1664 return -ERANGE;
1665 }
1666 state->restart_stdi_once = true;
1667 }
1668found:
1669
1670 if (no_signal(sd)) {
1671 v4l2_dbg(1, debug, sd, "%s: signal lost during readout\n", __func__);
1672 memset(timings, 0, sizeof(struct v4l2_dv_timings));
1673 return -ENOLINK;
1674 }
1675
1676 if ((is_analog_input(sd) && bt->pixelclock > 170000000) ||
1677 (is_digital_input(sd) && bt->pixelclock > 225000000)) {
1678 v4l2_dbg(1, debug, sd, "%s: pixelclock out of range %d\n",
1679 __func__, (u32)bt->pixelclock);
1680 return -ERANGE;
1681 }
1682
1683 if (debug > 1)
1684 v4l2_print_dv_timings(sd->name, "adv76xx_query_dv_timings: ",
1685 timings, true);
1686
1687 return 0;
1688}
1689
1690static int adv76xx_s_dv_timings(struct v4l2_subdev *sd,
1691 struct v4l2_dv_timings *timings)
1692{
1693 struct adv76xx_state *state = to_state(sd);
1694 struct v4l2_bt_timings *bt;
1695 int err;
1696
1697 if (!timings)
1698 return -EINVAL;
1699
1700 if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
1701 v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
1702 return 0;
1703 }
1704
1705 bt = &timings->bt;
1706
1707 if (!v4l2_valid_dv_timings(timings, adv76xx_get_dv_timings_cap(sd, -1),
1708 adv76xx_check_dv_timings, NULL))
1709 return -ERANGE;
1710
1711 adv76xx_fill_optional_dv_timings_fields(sd, timings);
1712
1713 state->timings = *timings;
1714
1715 cp_write_clr_set(sd, 0x91, 0x40, bt->interlaced ? 0x40 : 0x00);
1716
1717
1718 err = configure_predefined_video_timings(sd, timings);
1719 if (err) {
1720
1721
1722 configure_custom_video_timings(sd, bt);
1723 }
1724
1725 set_rgb_quantization_range(sd);
1726
1727 if (debug > 1)
1728 v4l2_print_dv_timings(sd->name, "adv76xx_s_dv_timings: ",
1729 timings, true);
1730 return 0;
1731}
1732
1733static int adv76xx_g_dv_timings(struct v4l2_subdev *sd,
1734 struct v4l2_dv_timings *timings)
1735{
1736 struct adv76xx_state *state = to_state(sd);
1737
1738 *timings = state->timings;
1739 return 0;
1740}
1741
1742static void adv7604_set_termination(struct v4l2_subdev *sd, bool enable)
1743{
1744 hdmi_write(sd, 0x01, enable ? 0x00 : 0x78);
1745}
1746
1747static void adv7611_set_termination(struct v4l2_subdev *sd, bool enable)
1748{
1749 hdmi_write(sd, 0x83, enable ? 0xfe : 0xff);
1750}
1751
1752static void enable_input(struct v4l2_subdev *sd)
1753{
1754 struct adv76xx_state *state = to_state(sd);
1755
1756 if (is_analog_input(sd)) {
1757 io_write(sd, 0x15, 0xb0);
1758 } else if (is_digital_input(sd)) {
1759 hdmi_write_clr_set(sd, 0x00, 0x03, state->selected_input);
1760 state->info->set_termination(sd, true);
1761 io_write(sd, 0x15, 0xa0);
1762 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x00);
1763 } else {
1764 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1765 __func__, state->selected_input);
1766 }
1767}
1768
1769static void disable_input(struct v4l2_subdev *sd)
1770{
1771 struct adv76xx_state *state = to_state(sd);
1772
1773 hdmi_write_clr_set(sd, 0x1a, 0x10, 0x10);
1774 msleep(16);
1775 io_write(sd, 0x15, 0xbe);
1776 state->info->set_termination(sd, false);
1777}
1778
1779static void select_input(struct v4l2_subdev *sd)
1780{
1781 struct adv76xx_state *state = to_state(sd);
1782 const struct adv76xx_chip_info *info = state->info;
1783
1784 if (is_analog_input(sd)) {
1785 adv76xx_write_reg_seq(sd, info->recommended_settings[0]);
1786
1787 afe_write(sd, 0x00, 0x08);
1788 afe_write(sd, 0x01, 0x06);
1789 afe_write(sd, 0xc8, 0x00);
1790 } else if (is_digital_input(sd)) {
1791 hdmi_write(sd, 0x00, state->selected_input & 0x03);
1792
1793 adv76xx_write_reg_seq(sd, info->recommended_settings[1]);
1794
1795 if (adv76xx_has_afe(state)) {
1796 afe_write(sd, 0x00, 0xff);
1797 afe_write(sd, 0x01, 0xfe);
1798 afe_write(sd, 0xc8, 0x40);
1799 }
1800
1801 cp_write(sd, 0x3e, 0x00);
1802 cp_write(sd, 0xc3, 0x39);
1803 cp_write(sd, 0x40, 0x80);
1804 } else {
1805 v4l2_dbg(2, debug, sd, "%s: Unknown port %d selected\n",
1806 __func__, state->selected_input);
1807 }
1808}
1809
1810static int adv76xx_s_routing(struct v4l2_subdev *sd,
1811 u32 input, u32 output, u32 config)
1812{
1813 struct adv76xx_state *state = to_state(sd);
1814
1815 v4l2_dbg(2, debug, sd, "%s: input %d, selected input %d",
1816 __func__, input, state->selected_input);
1817
1818 if (input == state->selected_input)
1819 return 0;
1820
1821 if (input > state->info->max_port)
1822 return -EINVAL;
1823
1824 state->selected_input = input;
1825
1826 disable_input(sd);
1827 select_input(sd);
1828 enable_input(sd);
1829
1830 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
1831
1832 return 0;
1833}
1834
1835static int adv76xx_enum_mbus_code(struct v4l2_subdev *sd,
1836 struct v4l2_subdev_state *sd_state,
1837 struct v4l2_subdev_mbus_code_enum *code)
1838{
1839 struct adv76xx_state *state = to_state(sd);
1840
1841 if (code->index >= state->info->nformats)
1842 return -EINVAL;
1843
1844 code->code = state->info->formats[code->index].code;
1845
1846 return 0;
1847}
1848
1849static void adv76xx_fill_format(struct adv76xx_state *state,
1850 struct v4l2_mbus_framefmt *format)
1851{
1852 memset(format, 0, sizeof(*format));
1853
1854 format->width = state->timings.bt.width;
1855 format->height = state->timings.bt.height;
1856 format->field = V4L2_FIELD_NONE;
1857 format->colorspace = V4L2_COLORSPACE_SRGB;
1858
1859 if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)
1860 format->colorspace = (state->timings.bt.height <= 576) ?
1861 V4L2_COLORSPACE_SMPTE170M : V4L2_COLORSPACE_REC709;
1862}
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882static unsigned int adv76xx_op_ch_sel(struct adv76xx_state *state)
1883{
1884#define _SEL(a,b,c,d,e,f) { \
1885 ADV76XX_OP_CH_SEL_##a, ADV76XX_OP_CH_SEL_##b, ADV76XX_OP_CH_SEL_##c, \
1886 ADV76XX_OP_CH_SEL_##d, ADV76XX_OP_CH_SEL_##e, ADV76XX_OP_CH_SEL_##f }
1887#define _BUS(x) [ADV7604_BUS_ORDER_##x]
1888
1889 static const unsigned int op_ch_sel[6][6] = {
1890 _BUS(RGB) = _SEL(GBR, GRB, BGR, RGB, BRG, RBG),
1891 _BUS(GRB) = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),
1892 _BUS(RBG) = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),
1893 _BUS(BGR) = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),
1894 _BUS(BRG) = _SEL(BRG, RBG, GRB, GBR, RGB, BGR),
1895 _BUS(GBR) = _SEL(RGB, BGR, RBG, BRG, GBR, GRB),
1896 };
1897
1898 return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];
1899}
1900
1901static void adv76xx_setup_format(struct adv76xx_state *state)
1902{
1903 struct v4l2_subdev *sd = &state->sd;
1904
1905 io_write_clr_set(sd, 0x02, 0x02,
1906 state->format->rgb_out ? ADV76XX_RGB_OUT : 0);
1907 io_write(sd, 0x03, state->format->op_format_sel |
1908 state->pdata.op_format_mode_sel);
1909 io_write_clr_set(sd, 0x04, 0xe0, adv76xx_op_ch_sel(state));
1910 io_write_clr_set(sd, 0x05, 0x01,
1911 state->format->swap_cb_cr ? ADV76XX_OP_SWAP_CB_CR : 0);
1912 set_rgb_quantization_range(sd);
1913}
1914
1915static int adv76xx_get_format(struct v4l2_subdev *sd,
1916 struct v4l2_subdev_state *sd_state,
1917 struct v4l2_subdev_format *format)
1918{
1919 struct adv76xx_state *state = to_state(sd);
1920
1921 if (format->pad != state->source_pad)
1922 return -EINVAL;
1923
1924 adv76xx_fill_format(state, &format->format);
1925
1926 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1927 struct v4l2_mbus_framefmt *fmt;
1928
1929 fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1930 format->format.code = fmt->code;
1931 } else {
1932 format->format.code = state->format->code;
1933 }
1934
1935 return 0;
1936}
1937
1938static int adv76xx_get_selection(struct v4l2_subdev *sd,
1939 struct v4l2_subdev_state *sd_state,
1940 struct v4l2_subdev_selection *sel)
1941{
1942 struct adv76xx_state *state = to_state(sd);
1943
1944 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1945 return -EINVAL;
1946
1947 if (sel->target > V4L2_SEL_TGT_CROP_BOUNDS)
1948 return -EINVAL;
1949
1950 sel->r.left = 0;
1951 sel->r.top = 0;
1952 sel->r.width = state->timings.bt.width;
1953 sel->r.height = state->timings.bt.height;
1954
1955 return 0;
1956}
1957
1958static int adv76xx_set_format(struct v4l2_subdev *sd,
1959 struct v4l2_subdev_state *sd_state,
1960 struct v4l2_subdev_format *format)
1961{
1962 struct adv76xx_state *state = to_state(sd);
1963 const struct adv76xx_format_info *info;
1964
1965 if (format->pad != state->source_pad)
1966 return -EINVAL;
1967
1968 info = adv76xx_format_info(state, format->format.code);
1969 if (!info)
1970 info = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
1971
1972 adv76xx_fill_format(state, &format->format);
1973 format->format.code = info->code;
1974
1975 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1976 struct v4l2_mbus_framefmt *fmt;
1977
1978 fmt = v4l2_subdev_get_try_format(sd, sd_state, format->pad);
1979 fmt->code = format->format.code;
1980 } else {
1981 state->format = info;
1982 adv76xx_setup_format(state);
1983 }
1984
1985 return 0;
1986}
1987
1988#if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
1989static void adv76xx_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)
1990{
1991 struct adv76xx_state *state = to_state(sd);
1992
1993 if ((cec_read(sd, 0x11) & 0x01) == 0) {
1994 v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);
1995 return;
1996 }
1997
1998 if (tx_raw_status & 0x02) {
1999 v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",
2000 __func__);
2001 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,
2002 1, 0, 0, 0);
2003 return;
2004 }
2005 if (tx_raw_status & 0x04) {
2006 u8 status;
2007 u8 nack_cnt;
2008 u8 low_drive_cnt;
2009
2010 v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);
2011
2012
2013
2014
2015 status = CEC_TX_STATUS_MAX_RETRIES;
2016 nack_cnt = cec_read(sd, 0x14) & 0xf;
2017 if (nack_cnt)
2018 status |= CEC_TX_STATUS_NACK;
2019 low_drive_cnt = cec_read(sd, 0x14) >> 4;
2020 if (low_drive_cnt)
2021 status |= CEC_TX_STATUS_LOW_DRIVE;
2022 cec_transmit_done(state->cec_adap, status,
2023 0, nack_cnt, low_drive_cnt, 0);
2024 return;
2025 }
2026 if (tx_raw_status & 0x01) {
2027 v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);
2028 cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);
2029 return;
2030 }
2031}
2032
2033static void adv76xx_cec_isr(struct v4l2_subdev *sd, bool *handled)
2034{
2035 struct adv76xx_state *state = to_state(sd);
2036 const struct adv76xx_chip_info *info = state->info;
2037 u8 cec_irq;
2038
2039
2040 cec_irq = io_read(sd, info->cec_irq_status) & 0x0f;
2041 if (!cec_irq)
2042 return;
2043
2044 v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);
2045 adv76xx_cec_tx_raw_status(sd, cec_irq);
2046 if (cec_irq & 0x08) {
2047 struct cec_msg msg;
2048
2049 msg.len = cec_read(sd, 0x25) & 0x1f;
2050 if (msg.len > 16)
2051 msg.len = 16;
2052
2053 if (msg.len) {
2054 u8 i;
2055
2056 for (i = 0; i < msg.len; i++)
2057 msg.msg[i] = cec_read(sd, i + 0x15);
2058 cec_write(sd, info->cec_rx_enable,
2059 info->cec_rx_enable_mask);
2060 cec_received_msg(state->cec_adap, &msg);
2061 }
2062 }
2063
2064 if (info->cec_irq_swap) {
2065
2066
2067
2068
2069 cec_irq = ((cec_irq & 0x08) >> 3) | ((cec_irq & 0x04) >> 1) |
2070 ((cec_irq & 0x02) << 1) | ((cec_irq & 0x01) << 3);
2071 }
2072 io_write(sd, info->cec_irq_status + 1, cec_irq);
2073
2074 if (handled)
2075 *handled = true;
2076}
2077
2078static int adv76xx_cec_adap_enable(struct cec_adapter *adap, bool enable)
2079{
2080 struct adv76xx_state *state = cec_get_drvdata(adap);
2081 const struct adv76xx_chip_info *info = state->info;
2082 struct v4l2_subdev *sd = &state->sd;
2083
2084 if (!state->cec_enabled_adap && enable) {
2085 cec_write_clr_set(sd, 0x2a, 0x01, 0x01);
2086 cec_write(sd, 0x2c, 0x01);
2087 cec_write_clr_set(sd, 0x11, 0x01, 0);
2088
2089
2090
2091
2092
2093 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x0f);
2094 cec_write(sd, info->cec_rx_enable, info->cec_rx_enable_mask);
2095 } else if (state->cec_enabled_adap && !enable) {
2096
2097 io_write_clr_set(sd, info->cec_irq_status + 3, 0x0f, 0x00);
2098
2099 cec_write_clr_set(sd, 0x27, 0x70, 0x00);
2100
2101 cec_write_clr_set(sd, 0x2a, 0x01, 0x00);
2102 state->cec_valid_addrs = 0;
2103 }
2104 state->cec_enabled_adap = enable;
2105 adv76xx_s_detect_tx_5v_ctrl(sd);
2106 return 0;
2107}
2108
2109static int adv76xx_cec_adap_log_addr(struct cec_adapter *adap, u8 addr)
2110{
2111 struct adv76xx_state *state = cec_get_drvdata(adap);
2112 struct v4l2_subdev *sd = &state->sd;
2113 unsigned int i, free_idx = ADV76XX_MAX_ADDRS;
2114
2115 if (!state->cec_enabled_adap)
2116 return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;
2117
2118 if (addr == CEC_LOG_ADDR_INVALID) {
2119 cec_write_clr_set(sd, 0x27, 0x70, 0);
2120 state->cec_valid_addrs = 0;
2121 return 0;
2122 }
2123
2124 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2125 bool is_valid = state->cec_valid_addrs & (1 << i);
2126
2127 if (free_idx == ADV76XX_MAX_ADDRS && !is_valid)
2128 free_idx = i;
2129 if (is_valid && state->cec_addr[i] == addr)
2130 return 0;
2131 }
2132 if (i == ADV76XX_MAX_ADDRS) {
2133 i = free_idx;
2134 if (i == ADV76XX_MAX_ADDRS)
2135 return -ENXIO;
2136 }
2137 state->cec_addr[i] = addr;
2138 state->cec_valid_addrs |= 1 << i;
2139
2140 switch (i) {
2141 case 0:
2142
2143 cec_write_clr_set(sd, 0x27, 0x10, 0x10);
2144
2145 cec_write_clr_set(sd, 0x28, 0x0f, addr);
2146 break;
2147 case 1:
2148
2149 cec_write_clr_set(sd, 0x27, 0x20, 0x20);
2150
2151 cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);
2152 break;
2153 case 2:
2154
2155 cec_write_clr_set(sd, 0x27, 0x40, 0x40);
2156
2157 cec_write_clr_set(sd, 0x29, 0x0f, addr);
2158 break;
2159 }
2160 return 0;
2161}
2162
2163static int adv76xx_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2164 u32 signal_free_time, struct cec_msg *msg)
2165{
2166 struct adv76xx_state *state = cec_get_drvdata(adap);
2167 struct v4l2_subdev *sd = &state->sd;
2168 u8 len = msg->len;
2169 unsigned int i;
2170
2171
2172
2173
2174
2175
2176 cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);
2177
2178 if (len > 16) {
2179 v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);
2180 return -EINVAL;
2181 }
2182
2183
2184 for (i = 0; i < len; i++)
2185 cec_write(sd, i, msg->msg[i]);
2186
2187
2188 cec_write(sd, 0x10, len);
2189
2190 cec_write(sd, 0x11, 0x01);
2191 return 0;
2192}
2193
2194static const struct cec_adap_ops adv76xx_cec_adap_ops = {
2195 .adap_enable = adv76xx_cec_adap_enable,
2196 .adap_log_addr = adv76xx_cec_adap_log_addr,
2197 .adap_transmit = adv76xx_cec_adap_transmit,
2198};
2199#endif
2200
2201static int adv76xx_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
2202{
2203 struct adv76xx_state *state = to_state(sd);
2204 const struct adv76xx_chip_info *info = state->info;
2205 const u8 irq_reg_0x43 = io_read(sd, 0x43);
2206 const u8 irq_reg_0x6b = io_read(sd, 0x6b);
2207 const u8 irq_reg_0x70 = io_read(sd, 0x70);
2208 u8 fmt_change_digital;
2209 u8 fmt_change;
2210 u8 tx_5v;
2211
2212 if (irq_reg_0x43)
2213 io_write(sd, 0x44, irq_reg_0x43);
2214 if (irq_reg_0x70)
2215 io_write(sd, 0x71, irq_reg_0x70);
2216 if (irq_reg_0x6b)
2217 io_write(sd, 0x6c, irq_reg_0x6b);
2218
2219 v4l2_dbg(2, debug, sd, "%s: ", __func__);
2220
2221
2222 fmt_change = irq_reg_0x43 & 0x98;
2223 fmt_change_digital = is_digital_input(sd)
2224 ? irq_reg_0x6b & info->fmt_change_digital_mask
2225 : 0;
2226
2227 if (fmt_change || fmt_change_digital) {
2228 v4l2_dbg(1, debug, sd,
2229 "%s: fmt_change = 0x%x, fmt_change_digital = 0x%x\n",
2230 __func__, fmt_change, fmt_change_digital);
2231
2232 v4l2_subdev_notify_event(sd, &adv76xx_ev_fmt);
2233
2234 if (handled)
2235 *handled = true;
2236 }
2237
2238 if (irq_reg_0x6b & 0x01) {
2239 v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,
2240 (io_read(sd, 0x6a) & 0x01) ? "HDMI" : "DVI");
2241 set_rgb_quantization_range(sd);
2242 if (handled)
2243 *handled = true;
2244 }
2245
2246#if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
2247
2248 adv76xx_cec_isr(sd, handled);
2249#endif
2250
2251
2252 tx_5v = irq_reg_0x70 & info->cable_det_mask;
2253 if (tx_5v) {
2254 v4l2_dbg(1, debug, sd, "%s: tx_5v: 0x%x\n", __func__, tx_5v);
2255 adv76xx_s_detect_tx_5v_ctrl(sd);
2256 if (handled)
2257 *handled = true;
2258 }
2259 return 0;
2260}
2261
2262static irqreturn_t adv76xx_irq_handler(int irq, void *dev_id)
2263{
2264 struct adv76xx_state *state = dev_id;
2265 bool handled = false;
2266
2267 adv76xx_isr(&state->sd, 0, &handled);
2268
2269 return handled ? IRQ_HANDLED : IRQ_NONE;
2270}
2271
2272static int adv76xx_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2273{
2274 struct adv76xx_state *state = to_state(sd);
2275 u8 *data = NULL;
2276
2277 memset(edid->reserved, 0, sizeof(edid->reserved));
2278
2279 switch (edid->pad) {
2280 case ADV76XX_PAD_HDMI_PORT_A:
2281 case ADV7604_PAD_HDMI_PORT_B:
2282 case ADV7604_PAD_HDMI_PORT_C:
2283 case ADV7604_PAD_HDMI_PORT_D:
2284 if (state->edid.present & (1 << edid->pad))
2285 data = state->edid.edid;
2286 break;
2287 default:
2288 return -EINVAL;
2289 }
2290
2291 if (edid->start_block == 0 && edid->blocks == 0) {
2292 edid->blocks = data ? state->edid.blocks : 0;
2293 return 0;
2294 }
2295
2296 if (!data)
2297 return -ENODATA;
2298
2299 if (edid->start_block >= state->edid.blocks)
2300 return -EINVAL;
2301
2302 if (edid->start_block + edid->blocks > state->edid.blocks)
2303 edid->blocks = state->edid.blocks - edid->start_block;
2304
2305 memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);
2306
2307 return 0;
2308}
2309
2310static int adv76xx_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)
2311{
2312 struct adv76xx_state *state = to_state(sd);
2313 const struct adv76xx_chip_info *info = state->info;
2314 unsigned int spa_loc;
2315 u16 pa, parent_pa;
2316 int err;
2317 int i;
2318
2319 memset(edid->reserved, 0, sizeof(edid->reserved));
2320
2321 if (edid->pad > ADV7604_PAD_HDMI_PORT_D)
2322 return -EINVAL;
2323 if (edid->start_block != 0)
2324 return -EINVAL;
2325 if (edid->blocks == 0) {
2326
2327 state->edid.present &= ~(1 << edid->pad);
2328 adv76xx_set_hpd(state, state->edid.present);
2329 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2330
2331
2332 state->aspect_ratio.numerator = 16;
2333 state->aspect_ratio.denominator = 9;
2334
2335 if (!state->edid.present) {
2336 state->edid.blocks = 0;
2337 cec_phys_addr_invalidate(state->cec_adap);
2338 }
2339
2340 v4l2_dbg(2, debug, sd, "%s: clear EDID pad %d, edid.present = 0x%x\n",
2341 __func__, edid->pad, state->edid.present);
2342 return 0;
2343 }
2344 if (edid->blocks > ADV76XX_MAX_EDID_BLOCKS) {
2345 edid->blocks = ADV76XX_MAX_EDID_BLOCKS;
2346 return -E2BIG;
2347 }
2348
2349 pa = v4l2_get_edid_phys_addr(edid->edid, edid->blocks * 128, &spa_loc);
2350 err = v4l2_phys_addr_validate(pa, &parent_pa, NULL);
2351 if (err)
2352 return err;
2353
2354 if (!spa_loc) {
2355
2356
2357
2358
2359 spa_loc = 128;
2360 pa = (edid->edid[spa_loc] << 8) | edid->edid[spa_loc + 1];
2361 }
2362
2363 v4l2_dbg(2, debug, sd, "%s: write EDID pad %d, edid.present = 0x%x\n",
2364 __func__, edid->pad, state->edid.present);
2365
2366
2367 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
2368 adv76xx_set_hpd(state, 0);
2369 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, 0x00);
2370
2371 switch (edid->pad) {
2372 case ADV76XX_PAD_HDMI_PORT_A:
2373 state->spa_port_a[0] = pa >> 8;
2374 state->spa_port_a[1] = pa & 0xff;
2375 break;
2376 case ADV7604_PAD_HDMI_PORT_B:
2377 rep_write(sd, info->edid_spa_port_b_reg, pa >> 8);
2378 rep_write(sd, info->edid_spa_port_b_reg + 1, pa & 0xff);
2379 break;
2380 case ADV7604_PAD_HDMI_PORT_C:
2381 rep_write(sd, info->edid_spa_port_b_reg + 2, pa >> 8);
2382 rep_write(sd, info->edid_spa_port_b_reg + 3, pa & 0xff);
2383 break;
2384 case ADV7604_PAD_HDMI_PORT_D:
2385 rep_write(sd, info->edid_spa_port_b_reg + 4, pa >> 8);
2386 rep_write(sd, info->edid_spa_port_b_reg + 5, pa & 0xff);
2387 break;
2388 default:
2389 return -EINVAL;
2390 }
2391
2392 if (info->edid_spa_loc_reg) {
2393 u8 mask = info->edid_spa_loc_msb_mask;
2394
2395 rep_write(sd, info->edid_spa_loc_reg, spa_loc & 0xff);
2396 rep_write_clr_set(sd, info->edid_spa_loc_reg + 1,
2397 mask, (spa_loc & 0x100) ? mask : 0);
2398 }
2399
2400 edid->edid[spa_loc] = state->spa_port_a[0];
2401 edid->edid[spa_loc + 1] = state->spa_port_a[1];
2402
2403 memcpy(state->edid.edid, edid->edid, 128 * edid->blocks);
2404 state->edid.blocks = edid->blocks;
2405 state->aspect_ratio = v4l2_calc_aspect_ratio(edid->edid[0x15],
2406 edid->edid[0x16]);
2407 state->edid.present |= 1 << edid->pad;
2408
2409 rep_write_clr_set(sd, info->edid_segment_reg,
2410 info->edid_segment_mask, 0);
2411 err = edid_write_block(sd, 128 * min(edid->blocks, 2U), state->edid.edid);
2412 if (err < 0) {
2413 v4l2_err(sd, "error %d writing edid pad %d\n", err, edid->pad);
2414 return err;
2415 }
2416 if (edid->blocks > 2) {
2417 rep_write_clr_set(sd, info->edid_segment_reg,
2418 info->edid_segment_mask,
2419 info->edid_segment_mask);
2420 err = edid_write_block(sd, 128 * (edid->blocks - 2),
2421 state->edid.edid + 256);
2422 if (err < 0) {
2423 v4l2_err(sd, "error %d writing edid pad %d\n",
2424 err, edid->pad);
2425 return err;
2426 }
2427 }
2428
2429
2430
2431 rep_write_clr_set(sd, info->edid_enable_reg, 0x0f, state->edid.present);
2432
2433 for (i = 0; i < 1000; i++) {
2434 if (rep_read(sd, info->edid_status_reg) & state->edid.present)
2435 break;
2436 mdelay(1);
2437 }
2438 if (i == 1000) {
2439 v4l2_err(sd, "error enabling edid (0x%x)\n", state->edid.present);
2440 return -EIO;
2441 }
2442 cec_s_phys_addr(state->cec_adap, parent_pa, false);
2443
2444
2445 schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
2446 return 0;
2447}
2448
2449
2450
2451static const struct adv76xx_cfg_read_infoframe adv76xx_cri[] = {
2452 { "AVI", 0x01, 0xe0, 0x00 },
2453 { "Audio", 0x02, 0xe3, 0x1c },
2454 { "SDP", 0x04, 0xe6, 0x2a },
2455 { "Vendor", 0x10, 0xec, 0x54 }
2456};
2457
2458static int adv76xx_read_infoframe(struct v4l2_subdev *sd, int index,
2459 union hdmi_infoframe *frame)
2460{
2461 uint8_t buffer[32];
2462 u8 len;
2463 int i;
2464
2465 if (!(io_read(sd, 0x60) & adv76xx_cri[index].present_mask)) {
2466 v4l2_info(sd, "%s infoframe not received\n",
2467 adv76xx_cri[index].desc);
2468 return -ENOENT;
2469 }
2470
2471 for (i = 0; i < 3; i++)
2472 buffer[i] = infoframe_read(sd,
2473 adv76xx_cri[index].head_addr + i);
2474
2475 len = buffer[2] + 1;
2476
2477 if (len + 3 > sizeof(buffer)) {
2478 v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__,
2479 adv76xx_cri[index].desc, len);
2480 return -ENOENT;
2481 }
2482
2483 for (i = 0; i < len; i++)
2484 buffer[i + 3] = infoframe_read(sd,
2485 adv76xx_cri[index].payload_addr + i);
2486
2487 if (hdmi_infoframe_unpack(frame, buffer, sizeof(buffer)) < 0) {
2488 v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__,
2489 adv76xx_cri[index].desc);
2490 return -ENOENT;
2491 }
2492 return 0;
2493}
2494
2495static void adv76xx_log_infoframes(struct v4l2_subdev *sd)
2496{
2497 int i;
2498
2499 if (!is_hdmi(sd)) {
2500 v4l2_info(sd, "receive DVI-D signal, no infoframes\n");
2501 return;
2502 }
2503
2504 for (i = 0; i < ARRAY_SIZE(adv76xx_cri); i++) {
2505 union hdmi_infoframe frame;
2506 struct i2c_client *client = v4l2_get_subdevdata(sd);
2507
2508 if (adv76xx_read_infoframe(sd, i, &frame))
2509 return;
2510 hdmi_infoframe_log(KERN_INFO, &client->dev, &frame);
2511 }
2512}
2513
2514static int adv76xx_log_status(struct v4l2_subdev *sd)
2515{
2516 struct adv76xx_state *state = to_state(sd);
2517 const struct adv76xx_chip_info *info = state->info;
2518 struct v4l2_dv_timings timings;
2519 struct stdi_readback stdi;
2520 u8 reg_io_0x02 = io_read(sd, 0x02);
2521 u8 edid_enabled;
2522 u8 cable_det;
2523
2524 static const char * const csc_coeff_sel_rb[16] = {
2525 "bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",
2526 "reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",
2527 "reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",
2528 "reserved", "reserved", "reserved", "reserved", "manual"
2529 };
2530 static const char * const input_color_space_txt[16] = {
2531 "RGB limited range (16-235)", "RGB full range (0-255)",
2532 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2533 "xvYCC Bt.601", "xvYCC Bt.709",
2534 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2535 "invalid", "invalid", "invalid", "invalid", "invalid",
2536 "invalid", "invalid", "automatic"
2537 };
2538 static const char * const hdmi_color_space_txt[16] = {
2539 "RGB limited range (16-235)", "RGB full range (0-255)",
2540 "YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",
2541 "xvYCC Bt.601", "xvYCC Bt.709",
2542 "YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",
2543 "sYCC", "opYCC 601", "opRGB", "invalid", "invalid",
2544 "invalid", "invalid", "invalid"
2545 };
2546 static const char * const rgb_quantization_range_txt[] = {
2547 "Automatic",
2548 "RGB limited range (16-235)",
2549 "RGB full range (0-255)",
2550 };
2551 static const char * const deep_color_mode_txt[4] = {
2552 "8-bits per channel",
2553 "10-bits per channel",
2554 "12-bits per channel",
2555 "16-bits per channel (not supported)"
2556 };
2557
2558 v4l2_info(sd, "-----Chip status-----\n");
2559 v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");
2560 edid_enabled = rep_read(sd, info->edid_status_reg);
2561 v4l2_info(sd, "EDID enabled port A: %s, B: %s, C: %s, D: %s\n",
2562 ((edid_enabled & 0x01) ? "Yes" : "No"),
2563 ((edid_enabled & 0x02) ? "Yes" : "No"),
2564 ((edid_enabled & 0x04) ? "Yes" : "No"),
2565 ((edid_enabled & 0x08) ? "Yes" : "No"));
2566 v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?
2567 "enabled" : "disabled");
2568 if (state->cec_enabled_adap) {
2569 int i;
2570
2571 for (i = 0; i < ADV76XX_MAX_ADDRS; i++) {
2572 bool is_valid = state->cec_valid_addrs & (1 << i);
2573
2574 if (is_valid)
2575 v4l2_info(sd, "CEC Logical Address: 0x%x\n",
2576 state->cec_addr[i]);
2577 }
2578 }
2579
2580 v4l2_info(sd, "-----Signal status-----\n");
2581 cable_det = info->read_cable_det(sd);
2582 v4l2_info(sd, "Cable detected (+5V power) port A: %s, B: %s, C: %s, D: %s\n",
2583 ((cable_det & 0x01) ? "Yes" : "No"),
2584 ((cable_det & 0x02) ? "Yes" : "No"),
2585 ((cable_det & 0x04) ? "Yes" : "No"),
2586 ((cable_det & 0x08) ? "Yes" : "No"));
2587 v4l2_info(sd, "TMDS signal detected: %s\n",
2588 no_signal_tmds(sd) ? "false" : "true");
2589 v4l2_info(sd, "TMDS signal locked: %s\n",
2590 no_lock_tmds(sd) ? "false" : "true");
2591 v4l2_info(sd, "SSPD locked: %s\n", no_lock_sspd(sd) ? "false" : "true");
2592 v4l2_info(sd, "STDI locked: %s\n", no_lock_stdi(sd) ? "false" : "true");
2593 v4l2_info(sd, "CP locked: %s\n", no_lock_cp(sd) ? "false" : "true");
2594 v4l2_info(sd, "CP free run: %s\n",
2595 (in_free_run(sd)) ? "on" : "off");
2596 v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",
2597 io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,
2598 (io_read(sd, 0x01) & 0x70) >> 4);
2599
2600 v4l2_info(sd, "-----Video Timings-----\n");
2601 if (read_stdi(sd, &stdi))
2602 v4l2_info(sd, "STDI: not locked\n");
2603 else
2604 v4l2_info(sd, "STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %s, %chsync, %cvsync\n",
2605 stdi.lcf, stdi.bl, stdi.lcvs,
2606 stdi.interlaced ? "interlaced" : "progressive",
2607 stdi.hs_pol, stdi.vs_pol);
2608 if (adv76xx_query_dv_timings(sd, &timings))
2609 v4l2_info(sd, "No video detected\n");
2610 else
2611 v4l2_print_dv_timings(sd->name, "Detected format: ",
2612 &timings, true);
2613 v4l2_print_dv_timings(sd->name, "Configured format: ",
2614 &state->timings, true);
2615
2616 if (no_signal(sd))
2617 return 0;
2618
2619 v4l2_info(sd, "-----Color space-----\n");
2620 v4l2_info(sd, "RGB quantization range ctrl: %s\n",
2621 rgb_quantization_range_txt[state->rgb_quantization_range]);
2622 v4l2_info(sd, "Input color space: %s\n",
2623 input_color_space_txt[reg_io_0x02 >> 4]);
2624 v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",
2625 (reg_io_0x02 & 0x02) ? "RGB" : "YCbCr",
2626 (((reg_io_0x02 >> 2) & 0x01) ^ (reg_io_0x02 & 0x01)) ?
2627 "(16-235)" : "(0-255)",
2628 (reg_io_0x02 & 0x08) ? "enabled" : "disabled");
2629 v4l2_info(sd, "Color space conversion: %s\n",
2630 csc_coeff_sel_rb[cp_read(sd, info->cp_csc) >> 4]);
2631
2632 if (!is_digital_input(sd))
2633 return 0;
2634
2635 v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
2636 v4l2_info(sd, "Digital video port selected: %c\n",
2637 (hdmi_read(sd, 0x00) & 0x03) + 'A');
2638 v4l2_info(sd, "HDCP encrypted content: %s\n",
2639 (hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");
2640 v4l2_info(sd, "HDCP keys read: %s%s\n",
2641 (hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",
2642 (hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");
2643 if (is_hdmi(sd)) {
2644 bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;
2645 bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;
2646 bool audio_mute = io_read(sd, 0x65) & 0x40;
2647
2648 v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",
2649 audio_pll_locked ? "locked" : "not locked",
2650 audio_sample_packet_detect ? "detected" : "not detected",
2651 audio_mute ? "muted" : "enabled");
2652 if (audio_pll_locked && audio_sample_packet_detect) {
2653 v4l2_info(sd, "Audio format: %s\n",
2654 (hdmi_read(sd, 0x07) & 0x20) ? "multi-channel" : "stereo");
2655 }
2656 v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +
2657 (hdmi_read(sd, 0x5c) << 8) +
2658 (hdmi_read(sd, 0x5d) & 0xf0));
2659 v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +
2660 (hdmi_read(sd, 0x5e) << 8) +
2661 hdmi_read(sd, 0x5f));
2662 v4l2_info(sd, "AV Mute: %s\n", (hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");
2663
2664 v4l2_info(sd, "Deep color mode: %s\n", deep_color_mode_txt[(hdmi_read(sd, 0x0b) & 0x60) >> 5]);
2665 v4l2_info(sd, "HDMI colorspace: %s\n", hdmi_color_space_txt[hdmi_read(sd, 0x53) & 0xf]);
2666
2667 adv76xx_log_infoframes(sd);
2668 }
2669
2670 return 0;
2671}
2672
2673static int adv76xx_subscribe_event(struct v4l2_subdev *sd,
2674 struct v4l2_fh *fh,
2675 struct v4l2_event_subscription *sub)
2676{
2677 switch (sub->type) {
2678 case V4L2_EVENT_SOURCE_CHANGE:
2679 return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
2680 case V4L2_EVENT_CTRL:
2681 return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
2682 default:
2683 return -EINVAL;
2684 }
2685}
2686
2687static int adv76xx_registered(struct v4l2_subdev *sd)
2688{
2689 struct adv76xx_state *state = to_state(sd);
2690 struct i2c_client *client = v4l2_get_subdevdata(sd);
2691 int err;
2692
2693 err = cec_register_adapter(state->cec_adap, &client->dev);
2694 if (err)
2695 cec_delete_adapter(state->cec_adap);
2696 return err;
2697}
2698
2699static void adv76xx_unregistered(struct v4l2_subdev *sd)
2700{
2701 struct adv76xx_state *state = to_state(sd);
2702
2703 cec_unregister_adapter(state->cec_adap);
2704}
2705
2706
2707
2708static const struct v4l2_ctrl_ops adv76xx_ctrl_ops = {
2709 .s_ctrl = adv76xx_s_ctrl,
2710 .g_volatile_ctrl = adv76xx_g_volatile_ctrl,
2711};
2712
2713static const struct v4l2_subdev_core_ops adv76xx_core_ops = {
2714 .log_status = adv76xx_log_status,
2715 .interrupt_service_routine = adv76xx_isr,
2716 .subscribe_event = adv76xx_subscribe_event,
2717 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
2718#ifdef CONFIG_VIDEO_ADV_DEBUG
2719 .g_register = adv76xx_g_register,
2720 .s_register = adv76xx_s_register,
2721#endif
2722};
2723
2724static const struct v4l2_subdev_video_ops adv76xx_video_ops = {
2725 .s_routing = adv76xx_s_routing,
2726 .g_input_status = adv76xx_g_input_status,
2727 .s_dv_timings = adv76xx_s_dv_timings,
2728 .g_dv_timings = adv76xx_g_dv_timings,
2729 .query_dv_timings = adv76xx_query_dv_timings,
2730};
2731
2732static const struct v4l2_subdev_pad_ops adv76xx_pad_ops = {
2733 .enum_mbus_code = adv76xx_enum_mbus_code,
2734 .get_selection = adv76xx_get_selection,
2735 .get_fmt = adv76xx_get_format,
2736 .set_fmt = adv76xx_set_format,
2737 .get_edid = adv76xx_get_edid,
2738 .set_edid = adv76xx_set_edid,
2739 .dv_timings_cap = adv76xx_dv_timings_cap,
2740 .enum_dv_timings = adv76xx_enum_dv_timings,
2741};
2742
2743static const struct v4l2_subdev_ops adv76xx_ops = {
2744 .core = &adv76xx_core_ops,
2745 .video = &adv76xx_video_ops,
2746 .pad = &adv76xx_pad_ops,
2747};
2748
2749static const struct v4l2_subdev_internal_ops adv76xx_int_ops = {
2750 .registered = adv76xx_registered,
2751 .unregistered = adv76xx_unregistered,
2752};
2753
2754
2755
2756static const struct v4l2_ctrl_config adv7604_ctrl_analog_sampling_phase = {
2757 .ops = &adv76xx_ctrl_ops,
2758 .id = V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE,
2759 .name = "Analog Sampling Phase",
2760 .type = V4L2_CTRL_TYPE_INTEGER,
2761 .min = 0,
2762 .max = 0x1f,
2763 .step = 1,
2764 .def = 0,
2765};
2766
2767static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color_manual = {
2768 .ops = &adv76xx_ctrl_ops,
2769 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL,
2770 .name = "Free Running Color, Manual",
2771 .type = V4L2_CTRL_TYPE_BOOLEAN,
2772 .min = false,
2773 .max = true,
2774 .step = 1,
2775 .def = false,
2776};
2777
2778static const struct v4l2_ctrl_config adv76xx_ctrl_free_run_color = {
2779 .ops = &adv76xx_ctrl_ops,
2780 .id = V4L2_CID_ADV_RX_FREE_RUN_COLOR,
2781 .name = "Free Running Color",
2782 .type = V4L2_CTRL_TYPE_INTEGER,
2783 .min = 0x0,
2784 .max = 0xffffff,
2785 .step = 0x1,
2786 .def = 0x0,
2787};
2788
2789
2790
2791struct adv76xx_register_map {
2792 const char *name;
2793 u8 default_addr;
2794};
2795
2796static const struct adv76xx_register_map adv76xx_default_addresses[] = {
2797 [ADV76XX_PAGE_IO] = { "main", 0x4c },
2798 [ADV7604_PAGE_AVLINK] = { "avlink", 0x42 },
2799 [ADV76XX_PAGE_CEC] = { "cec", 0x40 },
2800 [ADV76XX_PAGE_INFOFRAME] = { "infoframe", 0x3e },
2801 [ADV7604_PAGE_ESDP] = { "esdp", 0x38 },
2802 [ADV7604_PAGE_DPP] = { "dpp", 0x3c },
2803 [ADV76XX_PAGE_AFE] = { "afe", 0x26 },
2804 [ADV76XX_PAGE_REP] = { "rep", 0x32 },
2805 [ADV76XX_PAGE_EDID] = { "edid", 0x36 },
2806 [ADV76XX_PAGE_HDMI] = { "hdmi", 0x34 },
2807 [ADV76XX_PAGE_TEST] = { "test", 0x30 },
2808 [ADV76XX_PAGE_CP] = { "cp", 0x22 },
2809 [ADV7604_PAGE_VDP] = { "vdp", 0x24 },
2810};
2811
2812static int adv76xx_core_init(struct v4l2_subdev *sd)
2813{
2814 struct adv76xx_state *state = to_state(sd);
2815 const struct adv76xx_chip_info *info = state->info;
2816 struct adv76xx_platform_data *pdata = &state->pdata;
2817
2818 hdmi_write(sd, 0x48,
2819 (pdata->disable_pwrdnb ? 0x80 : 0) |
2820 (pdata->disable_cable_det_rst ? 0x40 : 0));
2821
2822 disable_input(sd);
2823
2824 if (pdata->default_input >= 0 &&
2825 pdata->default_input < state->source_pad) {
2826 state->selected_input = pdata->default_input;
2827 select_input(sd);
2828 enable_input(sd);
2829 }
2830
2831
2832 io_write(sd, 0x0c, 0x42);
2833 io_write(sd, 0x0b, 0x44);
2834 cp_write(sd, 0xcf, 0x01);
2835
2836
2837 if (info->type != ADV7604) {
2838
2839 io_write_clr_set(sd, 0x20, 0xc0, 0);
2840
2841
2842
2843
2844
2845 hdmi_write_clr_set(sd, 0x6c, 0xf6, 0x26);
2846 }
2847
2848
2849 io_write_clr_set(sd, 0x02, 0x0f, pdata->alt_gamma << 3);
2850 io_write_clr_set(sd, 0x05, 0x0e, pdata->blank_data << 3 |
2851 pdata->insert_av_codes << 2 |
2852 pdata->replicate_av_codes << 1);
2853 adv76xx_setup_format(state);
2854
2855 cp_write(sd, 0x69, 0x30);
2856
2857
2858 io_write(sd, 0x06, 0xa0 | pdata->inv_vs_pol << 2 |
2859 pdata->inv_hs_pol << 1 | pdata->inv_llc_pol);
2860
2861
2862 io_write(sd, 0x14, 0x40 | pdata->dr_str_data << 4 |
2863 pdata->dr_str_clk << 2 |
2864 pdata->dr_str_sync);
2865
2866 cp_write(sd, 0xba, (pdata->hdmi_free_run_mode << 1) | 0x01);
2867 cp_write(sd, 0xf3, 0xdc);
2868 cp_write(sd, 0xf9, 0x23);
2869
2870 cp_write(sd, 0x45, 0x23);
2871
2872 cp_write(sd, 0xc9, 0x2d);
2873
2874
2875
2876 hdmi_write_clr_set(sd, 0x15, 0x03, 0x03);
2877 hdmi_write_clr_set(sd, 0x1a, 0x0e, 0x08);
2878 hdmi_write_clr_set(sd, 0x68, 0x06, 0x06);
2879
2880
2881 afe_write(sd, 0xb5, 0x01);
2882
2883 if (adv76xx_has_afe(state)) {
2884 afe_write(sd, 0x02, pdata->ain_sel);
2885 io_write_clr_set(sd, 0x30, 1 << 4, pdata->output_bus_lsb_to_msb << 4);
2886 }
2887
2888
2889 io_write(sd, 0x40, 0xc0 | pdata->int1_config);
2890 io_write(sd, 0x46, 0x98);
2891 io_write(sd, 0x6e, info->fmt_change_digital_mask);
2892 io_write(sd, 0x73, info->cable_det_mask);
2893 info->setup_irqs(sd);
2894
2895 return v4l2_ctrl_handler_setup(sd->ctrl_handler);
2896}
2897
2898static void adv7604_setup_irqs(struct v4l2_subdev *sd)
2899{
2900 io_write(sd, 0x41, 0xd7);
2901}
2902
2903static void adv7611_setup_irqs(struct v4l2_subdev *sd)
2904{
2905 io_write(sd, 0x41, 0xd0);
2906}
2907
2908static void adv7612_setup_irqs(struct v4l2_subdev *sd)
2909{
2910 io_write(sd, 0x41, 0xd0);
2911}
2912
2913static void adv76xx_unregister_clients(struct adv76xx_state *state)
2914{
2915 unsigned int i;
2916
2917 for (i = 1; i < ARRAY_SIZE(state->i2c_clients); ++i)
2918 i2c_unregister_device(state->i2c_clients[i]);
2919}
2920
2921static struct i2c_client *adv76xx_dummy_client(struct v4l2_subdev *sd,
2922 unsigned int page)
2923{
2924 struct i2c_client *client = v4l2_get_subdevdata(sd);
2925 struct adv76xx_state *state = to_state(sd);
2926 struct adv76xx_platform_data *pdata = &state->pdata;
2927 unsigned int io_reg = 0xf2 + page;
2928 struct i2c_client *new_client;
2929
2930 if (pdata && pdata->i2c_addresses[page])
2931 new_client = i2c_new_dummy_device(client->adapter,
2932 pdata->i2c_addresses[page]);
2933 else
2934 new_client = i2c_new_ancillary_device(client,
2935 adv76xx_default_addresses[page].name,
2936 adv76xx_default_addresses[page].default_addr);
2937
2938 if (!IS_ERR(new_client))
2939 io_write(sd, io_reg, new_client->addr << 1);
2940
2941 return new_client;
2942}
2943
2944static const struct adv76xx_reg_seq adv7604_recommended_settings_afe[] = {
2945
2946
2947 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 },
2948 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x04 },
2949 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x00 },
2950 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x74 },
2951 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b },
2952 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0x74 },
2953 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x63 },
2954 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 },
2955 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 },
2956 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x88 },
2957 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2e },
2958 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x00 },
2959
2960
2961
2962 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0x7b },
2963 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x1f },
2964 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x3e), 0x04 },
2965 { ADV76XX_REG(ADV76XX_PAGE_CP, 0xc3), 0x39 },
2966 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x40), 0x5c },
2967
2968 { ADV76XX_REG_SEQ_TERM, 0 },
2969};
2970
2971static const struct adv76xx_reg_seq adv7604_recommended_settings_hdmi[] = {
2972
2973
2974 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x0d), 0x84 },
2975 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3d), 0x10 },
2976 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x3e), 0x39 },
2977 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4e), 0x3b },
2978 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xb6 },
2979 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x03 },
2980 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x18 },
2981 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x34 },
2982 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x93), 0x8b },
2983 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x94), 0x2d },
2984 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x96), 0x01 },
2985
2986
2987
2988 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x12), 0xfb },
2989 { ADV76XX_REG(ADV76XX_PAGE_AFE, 0x0c), 0x0d },
2990
2991 { ADV76XX_REG_SEQ_TERM, 0 },
2992};
2993
2994static const struct adv76xx_reg_seq adv7611_recommended_settings_hdmi[] = {
2995
2996 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
2997 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
2998 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
2999 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3000 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3001 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3002 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3003 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3004 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3005 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8d), 0x04 },
3006 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x8e), 0x1e },
3007
3008 { ADV76XX_REG_SEQ_TERM, 0 },
3009};
3010
3011static const struct adv76xx_reg_seq adv7612_recommended_settings_hdmi[] = {
3012 { ADV76XX_REG(ADV76XX_PAGE_CP, 0x6c), 0x00 },
3013 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x9b), 0x03 },
3014 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x6f), 0x08 },
3015 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x85), 0x1f },
3016 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x87), 0x70 },
3017 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x57), 0xda },
3018 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x58), 0x01 },
3019 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x03), 0x98 },
3020 { ADV76XX_REG(ADV76XX_PAGE_HDMI, 0x4c), 0x44 },
3021 { ADV76XX_REG_SEQ_TERM, 0 },
3022};
3023
3024static const struct adv76xx_chip_info adv76xx_chip_info[] = {
3025 [ADV7604] = {
3026 .type = ADV7604,
3027 .has_afe = true,
3028 .max_port = ADV7604_PAD_VGA_COMP,
3029 .num_dv_ports = 4,
3030 .edid_enable_reg = 0x77,
3031 .edid_status_reg = 0x7d,
3032 .edid_segment_reg = 0x77,
3033 .edid_segment_mask = 0x10,
3034 .edid_spa_loc_reg = 0x76,
3035 .edid_spa_loc_msb_mask = 0x40,
3036 .edid_spa_port_b_reg = 0x70,
3037 .lcf_reg = 0xb3,
3038 .tdms_lock_mask = 0xe0,
3039 .cable_det_mask = 0x1e,
3040 .fmt_change_digital_mask = 0xc1,
3041 .cp_csc = 0xfc,
3042 .cec_irq_status = 0x4d,
3043 .cec_rx_enable = 0x26,
3044 .cec_rx_enable_mask = 0x01,
3045 .cec_irq_swap = true,
3046 .formats = adv7604_formats,
3047 .nformats = ARRAY_SIZE(adv7604_formats),
3048 .set_termination = adv7604_set_termination,
3049 .setup_irqs = adv7604_setup_irqs,
3050 .read_hdmi_pixelclock = adv7604_read_hdmi_pixelclock,
3051 .read_cable_det = adv7604_read_cable_det,
3052 .recommended_settings = {
3053 [0] = adv7604_recommended_settings_afe,
3054 [1] = adv7604_recommended_settings_hdmi,
3055 },
3056 .num_recommended_settings = {
3057 [0] = ARRAY_SIZE(adv7604_recommended_settings_afe),
3058 [1] = ARRAY_SIZE(adv7604_recommended_settings_hdmi),
3059 },
3060 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV7604_PAGE_AVLINK) |
3061 BIT(ADV76XX_PAGE_CEC) | BIT(ADV76XX_PAGE_INFOFRAME) |
3062 BIT(ADV7604_PAGE_ESDP) | BIT(ADV7604_PAGE_DPP) |
3063 BIT(ADV76XX_PAGE_AFE) | BIT(ADV76XX_PAGE_REP) |
3064 BIT(ADV76XX_PAGE_EDID) | BIT(ADV76XX_PAGE_HDMI) |
3065 BIT(ADV76XX_PAGE_TEST) | BIT(ADV76XX_PAGE_CP) |
3066 BIT(ADV7604_PAGE_VDP),
3067 .linewidth_mask = 0xfff,
3068 .field0_height_mask = 0xfff,
3069 .field1_height_mask = 0xfff,
3070 .hfrontporch_mask = 0x3ff,
3071 .hsync_mask = 0x3ff,
3072 .hbackporch_mask = 0x3ff,
3073 .field0_vfrontporch_mask = 0x1fff,
3074 .field0_vsync_mask = 0x1fff,
3075 .field0_vbackporch_mask = 0x1fff,
3076 .field1_vfrontporch_mask = 0x1fff,
3077 .field1_vsync_mask = 0x1fff,
3078 .field1_vbackporch_mask = 0x1fff,
3079 },
3080 [ADV7611] = {
3081 .type = ADV7611,
3082 .has_afe = false,
3083 .max_port = ADV76XX_PAD_HDMI_PORT_A,
3084 .num_dv_ports = 1,
3085 .edid_enable_reg = 0x74,
3086 .edid_status_reg = 0x76,
3087 .edid_segment_reg = 0x7a,
3088 .edid_segment_mask = 0x01,
3089 .lcf_reg = 0xa3,
3090 .tdms_lock_mask = 0x43,
3091 .cable_det_mask = 0x01,
3092 .fmt_change_digital_mask = 0x03,
3093 .cp_csc = 0xf4,
3094 .cec_irq_status = 0x93,
3095 .cec_rx_enable = 0x2c,
3096 .cec_rx_enable_mask = 0x02,
3097 .formats = adv7611_formats,
3098 .nformats = ARRAY_SIZE(adv7611_formats),
3099 .set_termination = adv7611_set_termination,
3100 .setup_irqs = adv7611_setup_irqs,
3101 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3102 .read_cable_det = adv7611_read_cable_det,
3103 .recommended_settings = {
3104 [1] = adv7611_recommended_settings_hdmi,
3105 },
3106 .num_recommended_settings = {
3107 [1] = ARRAY_SIZE(adv7611_recommended_settings_hdmi),
3108 },
3109 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3110 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3111 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3112 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3113 .linewidth_mask = 0x1fff,
3114 .field0_height_mask = 0x1fff,
3115 .field1_height_mask = 0x1fff,
3116 .hfrontporch_mask = 0x1fff,
3117 .hsync_mask = 0x1fff,
3118 .hbackporch_mask = 0x1fff,
3119 .field0_vfrontporch_mask = 0x3fff,
3120 .field0_vsync_mask = 0x3fff,
3121 .field0_vbackporch_mask = 0x3fff,
3122 .field1_vfrontporch_mask = 0x3fff,
3123 .field1_vsync_mask = 0x3fff,
3124 .field1_vbackporch_mask = 0x3fff,
3125 },
3126 [ADV7612] = {
3127 .type = ADV7612,
3128 .has_afe = false,
3129 .max_port = ADV76XX_PAD_HDMI_PORT_A,
3130 .num_dv_ports = 1,
3131 .edid_enable_reg = 0x74,
3132 .edid_status_reg = 0x76,
3133 .edid_segment_reg = 0x7a,
3134 .edid_segment_mask = 0x01,
3135 .edid_spa_loc_reg = 0x70,
3136 .edid_spa_loc_msb_mask = 0x01,
3137 .edid_spa_port_b_reg = 0x52,
3138 .lcf_reg = 0xa3,
3139 .tdms_lock_mask = 0x43,
3140 .cable_det_mask = 0x01,
3141 .fmt_change_digital_mask = 0x03,
3142 .cp_csc = 0xf4,
3143 .cec_irq_status = 0x93,
3144 .cec_rx_enable = 0x2c,
3145 .cec_rx_enable_mask = 0x02,
3146 .formats = adv7612_formats,
3147 .nformats = ARRAY_SIZE(adv7612_formats),
3148 .set_termination = adv7611_set_termination,
3149 .setup_irqs = adv7612_setup_irqs,
3150 .read_hdmi_pixelclock = adv7611_read_hdmi_pixelclock,
3151 .read_cable_det = adv7612_read_cable_det,
3152 .recommended_settings = {
3153 [1] = adv7612_recommended_settings_hdmi,
3154 },
3155 .num_recommended_settings = {
3156 [1] = ARRAY_SIZE(adv7612_recommended_settings_hdmi),
3157 },
3158 .page_mask = BIT(ADV76XX_PAGE_IO) | BIT(ADV76XX_PAGE_CEC) |
3159 BIT(ADV76XX_PAGE_INFOFRAME) | BIT(ADV76XX_PAGE_AFE) |
3160 BIT(ADV76XX_PAGE_REP) | BIT(ADV76XX_PAGE_EDID) |
3161 BIT(ADV76XX_PAGE_HDMI) | BIT(ADV76XX_PAGE_CP),
3162 .linewidth_mask = 0x1fff,
3163 .field0_height_mask = 0x1fff,
3164 .field1_height_mask = 0x1fff,
3165 .hfrontporch_mask = 0x1fff,
3166 .hsync_mask = 0x1fff,
3167 .hbackporch_mask = 0x1fff,
3168 .field0_vfrontporch_mask = 0x3fff,
3169 .field0_vsync_mask = 0x3fff,
3170 .field0_vbackporch_mask = 0x3fff,
3171 .field1_vfrontporch_mask = 0x3fff,
3172 .field1_vsync_mask = 0x3fff,
3173 .field1_vbackporch_mask = 0x3fff,
3174 },
3175};
3176
3177static const struct i2c_device_id adv76xx_i2c_id[] = {
3178 { "adv7604", (kernel_ulong_t)&adv76xx_chip_info[ADV7604] },
3179 { "adv7611", (kernel_ulong_t)&adv76xx_chip_info[ADV7611] },
3180 { "adv7612", (kernel_ulong_t)&adv76xx_chip_info[ADV7612] },
3181 { }
3182};
3183MODULE_DEVICE_TABLE(i2c, adv76xx_i2c_id);
3184
3185static const struct of_device_id adv76xx_of_id[] __maybe_unused = {
3186 { .compatible = "adi,adv7611", .data = &adv76xx_chip_info[ADV7611] },
3187 { .compatible = "adi,adv7612", .data = &adv76xx_chip_info[ADV7612] },
3188 { }
3189};
3190MODULE_DEVICE_TABLE(of, adv76xx_of_id);
3191
3192static int adv76xx_parse_dt(struct adv76xx_state *state)
3193{
3194 struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
3195 struct device_node *endpoint;
3196 struct device_node *np;
3197 unsigned int flags;
3198 int ret;
3199 u32 v;
3200
3201 np = state->i2c_clients[ADV76XX_PAGE_IO]->dev.of_node;
3202
3203
3204 endpoint = of_graph_get_next_endpoint(np, NULL);
3205 if (!endpoint)
3206 return -EINVAL;
3207
3208 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint), &bus_cfg);
3209 of_node_put(endpoint);
3210 if (ret)
3211 return ret;
3212
3213 if (!of_property_read_u32(np, "default-input", &v))
3214 state->pdata.default_input = v;
3215 else
3216 state->pdata.default_input = -1;
3217
3218 flags = bus_cfg.bus.parallel.flags;
3219
3220 if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
3221 state->pdata.inv_hs_pol = 1;
3222
3223 if (flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
3224 state->pdata.inv_vs_pol = 1;
3225
3226 if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
3227 state->pdata.inv_llc_pol = 1;
3228
3229 if (bus_cfg.bus_type == V4L2_MBUS_BT656)
3230 state->pdata.insert_av_codes = 1;
3231
3232
3233 state->pdata.int1_config = ADV76XX_INT1_CONFIG_ACTIVE_HIGH;
3234
3235
3236 state->pdata.disable_pwrdnb = 0;
3237 state->pdata.disable_cable_det_rst = 0;
3238 state->pdata.blank_data = 1;
3239 state->pdata.op_format_mode_sel = ADV7604_OP_FORMAT_MODE0;
3240 state->pdata.bus_order = ADV7604_BUS_ORDER_RGB;
3241 state->pdata.dr_str_data = ADV76XX_DR_STR_MEDIUM_HIGH;
3242 state->pdata.dr_str_clk = ADV76XX_DR_STR_MEDIUM_HIGH;
3243 state->pdata.dr_str_sync = ADV76XX_DR_STR_MEDIUM_HIGH;
3244
3245 return 0;
3246}
3247
3248static const struct regmap_config adv76xx_regmap_cnf[] = {
3249 {
3250 .name = "io",
3251 .reg_bits = 8,
3252 .val_bits = 8,
3253
3254 .max_register = 0xff,
3255 .cache_type = REGCACHE_NONE,
3256 },
3257 {
3258 .name = "avlink",
3259 .reg_bits = 8,
3260 .val_bits = 8,
3261
3262 .max_register = 0xff,
3263 .cache_type = REGCACHE_NONE,
3264 },
3265 {
3266 .name = "cec",
3267 .reg_bits = 8,
3268 .val_bits = 8,
3269
3270 .max_register = 0xff,
3271 .cache_type = REGCACHE_NONE,
3272 },
3273 {
3274 .name = "infoframe",
3275 .reg_bits = 8,
3276 .val_bits = 8,
3277
3278 .max_register = 0xff,
3279 .cache_type = REGCACHE_NONE,
3280 },
3281 {
3282 .name = "esdp",
3283 .reg_bits = 8,
3284 .val_bits = 8,
3285
3286 .max_register = 0xff,
3287 .cache_type = REGCACHE_NONE,
3288 },
3289 {
3290 .name = "epp",
3291 .reg_bits = 8,
3292 .val_bits = 8,
3293
3294 .max_register = 0xff,
3295 .cache_type = REGCACHE_NONE,
3296 },
3297 {
3298 .name = "afe",
3299 .reg_bits = 8,
3300 .val_bits = 8,
3301
3302 .max_register = 0xff,
3303 .cache_type = REGCACHE_NONE,
3304 },
3305 {
3306 .name = "rep",
3307 .reg_bits = 8,
3308 .val_bits = 8,
3309
3310 .max_register = 0xff,
3311 .cache_type = REGCACHE_NONE,
3312 },
3313 {
3314 .name = "edid",
3315 .reg_bits = 8,
3316 .val_bits = 8,
3317
3318 .max_register = 0xff,
3319 .cache_type = REGCACHE_NONE,
3320 },
3321
3322 {
3323 .name = "hdmi",
3324 .reg_bits = 8,
3325 .val_bits = 8,
3326
3327 .max_register = 0xff,
3328 .cache_type = REGCACHE_NONE,
3329 },
3330 {
3331 .name = "test",
3332 .reg_bits = 8,
3333 .val_bits = 8,
3334
3335 .max_register = 0xff,
3336 .cache_type = REGCACHE_NONE,
3337 },
3338 {
3339 .name = "cp",
3340 .reg_bits = 8,
3341 .val_bits = 8,
3342
3343 .max_register = 0xff,
3344 .cache_type = REGCACHE_NONE,
3345 },
3346 {
3347 .name = "vdp",
3348 .reg_bits = 8,
3349 .val_bits = 8,
3350
3351 .max_register = 0xff,
3352 .cache_type = REGCACHE_NONE,
3353 },
3354};
3355
3356static int configure_regmap(struct adv76xx_state *state, int region)
3357{
3358 int err;
3359
3360 if (!state->i2c_clients[region])
3361 return -ENODEV;
3362
3363 state->regmap[region] =
3364 devm_regmap_init_i2c(state->i2c_clients[region],
3365 &adv76xx_regmap_cnf[region]);
3366
3367 if (IS_ERR(state->regmap[region])) {
3368 err = PTR_ERR(state->regmap[region]);
3369 v4l_err(state->i2c_clients[region],
3370 "Error initializing regmap %d with error %d\n",
3371 region, err);
3372 return -EINVAL;
3373 }
3374
3375 return 0;
3376}
3377
3378static int configure_regmaps(struct adv76xx_state *state)
3379{
3380 int i, err;
3381
3382 for (i = ADV7604_PAGE_AVLINK ; i < ADV76XX_PAGE_MAX; i++) {
3383 err = configure_regmap(state, i);
3384 if (err && (err != -ENODEV))
3385 return err;
3386 }
3387 return 0;
3388}
3389
3390static void adv76xx_reset(struct adv76xx_state *state)
3391{
3392 if (state->reset_gpio) {
3393
3394 gpiod_set_value_cansleep(state->reset_gpio, 0);
3395 usleep_range(5000, 10000);
3396 gpiod_set_value_cansleep(state->reset_gpio, 1);
3397
3398
3399 usleep_range(5000, 10000);
3400 }
3401}
3402
3403static int adv76xx_probe(struct i2c_client *client,
3404 const struct i2c_device_id *id)
3405{
3406 static const struct v4l2_dv_timings cea640x480 =
3407 V4L2_DV_BT_CEA_640X480P59_94;
3408 struct adv76xx_state *state;
3409 struct v4l2_ctrl_handler *hdl;
3410 struct v4l2_ctrl *ctrl;
3411 struct v4l2_subdev *sd;
3412 unsigned int i;
3413 unsigned int val, val2;
3414 int err;
3415
3416
3417 if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
3418 return -EIO;
3419 v4l_dbg(1, debug, client, "detecting adv76xx client on address 0x%x\n",
3420 client->addr << 1);
3421
3422 state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
3423 if (!state)
3424 return -ENOMEM;
3425
3426 state->i2c_clients[ADV76XX_PAGE_IO] = client;
3427
3428
3429 state->restart_stdi_once = true;
3430 state->selected_input = ~0;
3431
3432 if (IS_ENABLED(CONFIG_OF) && client->dev.of_node) {
3433 const struct of_device_id *oid;
3434
3435 oid = of_match_node(adv76xx_of_id, client->dev.of_node);
3436 state->info = oid->data;
3437
3438 err = adv76xx_parse_dt(state);
3439 if (err < 0) {
3440 v4l_err(client, "DT parsing error\n");
3441 return err;
3442 }
3443 } else if (client->dev.platform_data) {
3444 struct adv76xx_platform_data *pdata = client->dev.platform_data;
3445
3446 state->info = (const struct adv76xx_chip_info *)id->driver_data;
3447 state->pdata = *pdata;
3448 } else {
3449 v4l_err(client, "No platform data!\n");
3450 return -ENODEV;
3451 }
3452
3453
3454 for (i = 0; i < state->info->num_dv_ports; ++i) {
3455 state->hpd_gpio[i] =
3456 devm_gpiod_get_index_optional(&client->dev, "hpd", i,
3457 GPIOD_OUT_LOW);
3458 if (IS_ERR(state->hpd_gpio[i]))
3459 return PTR_ERR(state->hpd_gpio[i]);
3460
3461 if (state->hpd_gpio[i])
3462 v4l_info(client, "Handling HPD %u GPIO\n", i);
3463 }
3464 state->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
3465 GPIOD_OUT_HIGH);
3466 if (IS_ERR(state->reset_gpio))
3467 return PTR_ERR(state->reset_gpio);
3468
3469 adv76xx_reset(state);
3470
3471 state->timings = cea640x480;
3472 state->format = adv76xx_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);
3473
3474 sd = &state->sd;
3475 v4l2_i2c_subdev_init(sd, client, &adv76xx_ops);
3476 snprintf(sd->name, sizeof(sd->name), "%s %d-%04x",
3477 id->name, i2c_adapter_id(client->adapter),
3478 client->addr);
3479 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
3480 sd->internal_ops = &adv76xx_int_ops;
3481
3482
3483 err = configure_regmap(state, ADV76XX_PAGE_IO);
3484
3485 if (err) {
3486 v4l2_err(sd, "Error configuring IO regmap region\n");
3487 return -ENODEV;
3488 }
3489
3490
3491
3492
3493
3494
3495 switch (state->info->type) {
3496 case ADV7604:
3497 err = regmap_read(state->regmap[ADV76XX_PAGE_IO], 0xfb, &val);
3498 if (err) {
3499 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3500 return -ENODEV;
3501 }
3502 if (val != 0x68) {
3503 v4l2_err(sd, "not an adv7604 on address 0x%x\n",
3504 client->addr << 1);
3505 return -ENODEV;
3506 }
3507 break;
3508 case ADV7611:
3509 case ADV7612:
3510 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3511 0xea,
3512 &val);
3513 if (err) {
3514 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3515 return -ENODEV;
3516 }
3517 val2 = val << 8;
3518 err = regmap_read(state->regmap[ADV76XX_PAGE_IO],
3519 0xeb,
3520 &val);
3521 if (err) {
3522 v4l2_err(sd, "Error %d reading IO Regmap\n", err);
3523 return -ENODEV;
3524 }
3525 val |= val2;
3526 if ((state->info->type == ADV7611 && val != 0x2051) ||
3527 (state->info->type == ADV7612 && val != 0x2041)) {
3528 v4l2_err(sd, "not an adv761x on address 0x%x\n",
3529 client->addr << 1);
3530 return -ENODEV;
3531 }
3532 break;
3533 }
3534
3535
3536 hdl = &state->hdl;
3537 v4l2_ctrl_handler_init(hdl, adv76xx_has_afe(state) ? 9 : 8);
3538
3539 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3540 V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);
3541 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3542 V4L2_CID_CONTRAST, 0, 255, 1, 128);
3543 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3544 V4L2_CID_SATURATION, 0, 255, 1, 128);
3545 v4l2_ctrl_new_std(hdl, &adv76xx_ctrl_ops,
3546 V4L2_CID_HUE, 0, 128, 1, 0);
3547 ctrl = v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3548 V4L2_CID_DV_RX_IT_CONTENT_TYPE, V4L2_DV_IT_CONTENT_TYPE_NO_ITC,
3549 0, V4L2_DV_IT_CONTENT_TYPE_NO_ITC);
3550 if (ctrl)
3551 ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
3552
3553 state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,
3554 V4L2_CID_DV_RX_POWER_PRESENT, 0,
3555 (1 << state->info->num_dv_ports) - 1, 0, 0);
3556 state->rgb_quantization_range_ctrl =
3557 v4l2_ctrl_new_std_menu(hdl, &adv76xx_ctrl_ops,
3558 V4L2_CID_DV_RX_RGB_RANGE, V4L2_DV_RGB_RANGE_FULL,
3559 0, V4L2_DV_RGB_RANGE_AUTO);
3560
3561
3562 if (adv76xx_has_afe(state))
3563 state->analog_sampling_phase_ctrl =
3564 v4l2_ctrl_new_custom(hdl, &adv7604_ctrl_analog_sampling_phase, NULL);
3565 state->free_run_color_manual_ctrl =
3566 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color_manual, NULL);
3567 state->free_run_color_ctrl =
3568 v4l2_ctrl_new_custom(hdl, &adv76xx_ctrl_free_run_color, NULL);
3569
3570 sd->ctrl_handler = hdl;
3571 if (hdl->error) {
3572 err = hdl->error;
3573 goto err_hdl;
3574 }
3575 if (adv76xx_s_detect_tx_5v_ctrl(sd)) {
3576 err = -ENODEV;
3577 goto err_hdl;
3578 }
3579
3580 for (i = 1; i < ADV76XX_PAGE_MAX; ++i) {
3581 struct i2c_client *dummy_client;
3582
3583 if (!(BIT(i) & state->info->page_mask))
3584 continue;
3585
3586 dummy_client = adv76xx_dummy_client(sd, i);
3587 if (IS_ERR(dummy_client)) {
3588 err = PTR_ERR(dummy_client);
3589 v4l2_err(sd, "failed to create i2c client %u\n", i);
3590 goto err_i2c;
3591 }
3592
3593 state->i2c_clients[i] = dummy_client;
3594 }
3595
3596 INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
3597 adv76xx_delayed_work_enable_hotplug);
3598
3599 state->source_pad = state->info->num_dv_ports
3600 + (state->info->has_afe ? 2 : 0);
3601 for (i = 0; i < state->source_pad; ++i)
3602 state->pads[i].flags = MEDIA_PAD_FL_SINK;
3603 state->pads[state->source_pad].flags = MEDIA_PAD_FL_SOURCE;
3604 sd->entity.function = MEDIA_ENT_F_DV_DECODER;
3605
3606 err = media_entity_pads_init(&sd->entity, state->source_pad + 1,
3607 state->pads);
3608 if (err)
3609 goto err_work_queues;
3610
3611
3612 err = configure_regmaps(state);
3613 if (err)
3614 goto err_entity;
3615
3616 err = adv76xx_core_init(sd);
3617 if (err)
3618 goto err_entity;
3619
3620 if (client->irq) {
3621 err = devm_request_threaded_irq(&client->dev,
3622 client->irq,
3623 NULL, adv76xx_irq_handler,
3624 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
3625 client->name, state);
3626 if (err)
3627 goto err_entity;
3628 }
3629
3630#if IS_ENABLED(CONFIG_VIDEO_ADV7604_CEC)
3631 state->cec_adap = cec_allocate_adapter(&adv76xx_cec_adap_ops,
3632 state, dev_name(&client->dev),
3633 CEC_CAP_DEFAULTS, ADV76XX_MAX_ADDRS);
3634 err = PTR_ERR_OR_ZERO(state->cec_adap);
3635 if (err)
3636 goto err_entity;
3637#endif
3638
3639 v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
3640 client->addr << 1, client->adapter->name);
3641
3642 err = v4l2_async_register_subdev(sd);
3643 if (err)
3644 goto err_entity;
3645
3646 return 0;
3647
3648err_entity:
3649 media_entity_cleanup(&sd->entity);
3650err_work_queues:
3651 cancel_delayed_work(&state->delayed_work_enable_hotplug);
3652err_i2c:
3653 adv76xx_unregister_clients(state);
3654err_hdl:
3655 v4l2_ctrl_handler_free(hdl);
3656 return err;
3657}
3658
3659
3660
3661static int adv76xx_remove(struct i2c_client *client)
3662{
3663 struct v4l2_subdev *sd = i2c_get_clientdata(client);
3664 struct adv76xx_state *state = to_state(sd);
3665
3666
3667 io_write(sd, 0x40, 0);
3668 io_write(sd, 0x41, 0);
3669 io_write(sd, 0x46, 0);
3670 io_write(sd, 0x6e, 0);
3671 io_write(sd, 0x73, 0);
3672
3673 cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
3674 v4l2_async_unregister_subdev(sd);
3675 media_entity_cleanup(&sd->entity);
3676 adv76xx_unregister_clients(to_state(sd));
3677 v4l2_ctrl_handler_free(sd->ctrl_handler);
3678 return 0;
3679}
3680
3681
3682
3683static struct i2c_driver adv76xx_driver = {
3684 .driver = {
3685 .name = "adv7604",
3686 .of_match_table = of_match_ptr(adv76xx_of_id),
3687 },
3688 .probe = adv76xx_probe,
3689 .remove = adv76xx_remove,
3690 .id_table = adv76xx_i2c_id,
3691};
3692
3693module_i2c_driver(adv76xx_driver);
3694