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20#include <linux/bitops.h>
21#include <linux/clk.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/gpio/consumer.h>
25#include <linux/i2c.h>
26#include <linux/init.h>
27#include <linux/module.h>
28#include <linux/of.h>
29#include <linux/of_graph.h>
30#include <linux/regulator/consumer.h>
31#include <linux/slab.h>
32#include <linux/types.h>
33#include <media/v4l2-ctrls.h>
34#include <media/v4l2-fwnode.h>
35#include <media/v4l2-subdev.h>
36
37#define OV5645_SYSTEM_CTRL0 0x3008
38#define OV5645_SYSTEM_CTRL0_START 0x02
39#define OV5645_SYSTEM_CTRL0_STOP 0x42
40#define OV5645_CHIP_ID_HIGH 0x300a
41#define OV5645_CHIP_ID_HIGH_BYTE 0x56
42#define OV5645_CHIP_ID_LOW 0x300b
43#define OV5645_CHIP_ID_LOW_BYTE 0x45
44#define OV5645_IO_MIPI_CTRL00 0x300e
45#define OV5645_PAD_OUTPUT00 0x3019
46#define OV5645_AWB_MANUAL_CONTROL 0x3406
47#define OV5645_AWB_MANUAL_ENABLE BIT(0)
48#define OV5645_AEC_PK_MANUAL 0x3503
49#define OV5645_AEC_MANUAL_ENABLE BIT(0)
50#define OV5645_AGC_MANUAL_ENABLE BIT(1)
51#define OV5645_TIMING_TC_REG20 0x3820
52#define OV5645_SENSOR_VFLIP BIT(1)
53#define OV5645_ISP_VFLIP BIT(2)
54#define OV5645_TIMING_TC_REG21 0x3821
55#define OV5645_SENSOR_MIRROR BIT(1)
56#define OV5645_MIPI_CTRL00 0x4800
57#define OV5645_PRE_ISP_TEST_SETTING_1 0x503d
58#define OV5645_TEST_PATTERN_MASK 0x3
59#define OV5645_SET_TEST_PATTERN(x) ((x) & OV5645_TEST_PATTERN_MASK)
60#define OV5645_TEST_PATTERN_ENABLE BIT(7)
61#define OV5645_SDE_SAT_U 0x5583
62#define OV5645_SDE_SAT_V 0x5584
63
64
65static const char * const ov5645_supply_name[] = {
66 "vdddo",
67 "vdda",
68 "vddd",
69};
70
71#define OV5645_NUM_SUPPLIES ARRAY_SIZE(ov5645_supply_name)
72
73struct reg_value {
74 u16 reg;
75 u8 val;
76};
77
78struct ov5645_mode_info {
79 u32 width;
80 u32 height;
81 const struct reg_value *data;
82 u32 data_size;
83 u32 pixel_clock;
84 u32 link_freq;
85};
86
87struct ov5645 {
88 struct i2c_client *i2c_client;
89 struct device *dev;
90 struct v4l2_subdev sd;
91 struct media_pad pad;
92 struct v4l2_fwnode_endpoint ep;
93 struct v4l2_mbus_framefmt fmt;
94 struct v4l2_rect crop;
95 struct clk *xclk;
96
97 struct regulator_bulk_data supplies[OV5645_NUM_SUPPLIES];
98
99 const struct ov5645_mode_info *current_mode;
100
101 struct v4l2_ctrl_handler ctrls;
102 struct v4l2_ctrl *pixel_clock;
103 struct v4l2_ctrl *link_freq;
104
105
106 u8 aec_pk_manual;
107 u8 timing_tc_reg20;
108 u8 timing_tc_reg21;
109
110 struct mutex power_lock;
111 int power_count;
112
113 struct gpio_desc *enable_gpio;
114 struct gpio_desc *rst_gpio;
115};
116
117static inline struct ov5645 *to_ov5645(struct v4l2_subdev *sd)
118{
119 return container_of(sd, struct ov5645, sd);
120}
121
122static const struct reg_value ov5645_global_init_setting[] = {
123 { 0x3103, 0x11 },
124 { 0x3008, 0x82 },
125 { 0x3008, 0x42 },
126 { 0x3103, 0x03 },
127 { 0x3503, 0x07 },
128 { 0x3002, 0x1c },
129 { 0x3006, 0xc3 },
130 { 0x3017, 0x00 },
131 { 0x3018, 0x00 },
132 { 0x302e, 0x0b },
133 { 0x3037, 0x13 },
134 { 0x3108, 0x01 },
135 { 0x3611, 0x06 },
136 { 0x3500, 0x00 },
137 { 0x3501, 0x01 },
138 { 0x3502, 0x00 },
139 { 0x350a, 0x00 },
140 { 0x350b, 0x3f },
141 { 0x3620, 0x33 },
142 { 0x3621, 0xe0 },
143 { 0x3622, 0x01 },
144 { 0x3630, 0x2e },
145 { 0x3631, 0x00 },
146 { 0x3632, 0x32 },
147 { 0x3633, 0x52 },
148 { 0x3634, 0x70 },
149 { 0x3635, 0x13 },
150 { 0x3636, 0x03 },
151 { 0x3703, 0x5a },
152 { 0x3704, 0xa0 },
153 { 0x3705, 0x1a },
154 { 0x3709, 0x12 },
155 { 0x370b, 0x61 },
156 { 0x370f, 0x10 },
157 { 0x3715, 0x78 },
158 { 0x3717, 0x01 },
159 { 0x371b, 0x20 },
160 { 0x3731, 0x12 },
161 { 0x3901, 0x0a },
162 { 0x3905, 0x02 },
163 { 0x3906, 0x10 },
164 { 0x3719, 0x86 },
165 { 0x3810, 0x00 },
166 { 0x3811, 0x10 },
167 { 0x3812, 0x00 },
168 { 0x3821, 0x01 },
169 { 0x3824, 0x01 },
170 { 0x3826, 0x03 },
171 { 0x3828, 0x08 },
172 { 0x3a19, 0xf8 },
173 { 0x3c01, 0x34 },
174 { 0x3c04, 0x28 },
175 { 0x3c05, 0x98 },
176 { 0x3c07, 0x07 },
177 { 0x3c09, 0xc2 },
178 { 0x3c0a, 0x9c },
179 { 0x3c0b, 0x40 },
180 { 0x3c01, 0x34 },
181 { 0x4001, 0x02 },
182 { 0x4514, 0x00 },
183 { 0x4520, 0xb0 },
184 { 0x460b, 0x37 },
185 { 0x460c, 0x20 },
186 { 0x4818, 0x01 },
187 { 0x481d, 0xf0 },
188 { 0x481f, 0x50 },
189 { 0x4823, 0x70 },
190 { 0x4831, 0x14 },
191 { 0x5000, 0xa7 },
192 { 0x5001, 0x83 },
193 { 0x501d, 0x00 },
194 { 0x501f, 0x00 },
195 { 0x503d, 0x00 },
196 { 0x505c, 0x30 },
197 { 0x5181, 0x59 },
198 { 0x5183, 0x00 },
199 { 0x5191, 0xf0 },
200 { 0x5192, 0x03 },
201 { 0x5684, 0x10 },
202 { 0x5685, 0xa0 },
203 { 0x5686, 0x0c },
204 { 0x5687, 0x78 },
205 { 0x5a00, 0x08 },
206 { 0x5a21, 0x00 },
207 { 0x5a24, 0x00 },
208 { 0x3008, 0x02 },
209 { 0x3503, 0x00 },
210 { 0x5180, 0xff },
211 { 0x5181, 0xf2 },
212 { 0x5182, 0x00 },
213 { 0x5183, 0x14 },
214 { 0x5184, 0x25 },
215 { 0x5185, 0x24 },
216 { 0x5186, 0x09 },
217 { 0x5187, 0x09 },
218 { 0x5188, 0x0a },
219 { 0x5189, 0x75 },
220 { 0x518a, 0x52 },
221 { 0x518b, 0xea },
222 { 0x518c, 0xa8 },
223 { 0x518d, 0x42 },
224 { 0x518e, 0x38 },
225 { 0x518f, 0x56 },
226 { 0x5190, 0x42 },
227 { 0x5191, 0xf8 },
228 { 0x5192, 0x04 },
229 { 0x5193, 0x70 },
230 { 0x5194, 0xf0 },
231 { 0x5195, 0xf0 },
232 { 0x5196, 0x03 },
233 { 0x5197, 0x01 },
234 { 0x5198, 0x04 },
235 { 0x5199, 0x12 },
236 { 0x519a, 0x04 },
237 { 0x519b, 0x00 },
238 { 0x519c, 0x06 },
239 { 0x519d, 0x82 },
240 { 0x519e, 0x38 },
241 { 0x5381, 0x1e },
242 { 0x5382, 0x5b },
243 { 0x5383, 0x08 },
244 { 0x5384, 0x0a },
245 { 0x5385, 0x7e },
246 { 0x5386, 0x88 },
247 { 0x5387, 0x7c },
248 { 0x5388, 0x6c },
249 { 0x5389, 0x10 },
250 { 0x538a, 0x01 },
251 { 0x538b, 0x98 },
252 { 0x5300, 0x08 },
253 { 0x5301, 0x30 },
254 { 0x5302, 0x10 },
255 { 0x5303, 0x00 },
256 { 0x5304, 0x08 },
257 { 0x5305, 0x30 },
258 { 0x5306, 0x08 },
259 { 0x5307, 0x16 },
260 { 0x5309, 0x08 },
261 { 0x530a, 0x30 },
262 { 0x530b, 0x04 },
263 { 0x530c, 0x06 },
264 { 0x5480, 0x01 },
265 { 0x5481, 0x08 },
266 { 0x5482, 0x14 },
267 { 0x5483, 0x28 },
268 { 0x5484, 0x51 },
269 { 0x5485, 0x65 },
270 { 0x5486, 0x71 },
271 { 0x5487, 0x7d },
272 { 0x5488, 0x87 },
273 { 0x5489, 0x91 },
274 { 0x548a, 0x9a },
275 { 0x548b, 0xaa },
276 { 0x548c, 0xb8 },
277 { 0x548d, 0xcd },
278 { 0x548e, 0xdd },
279 { 0x548f, 0xea },
280 { 0x5490, 0x1d },
281 { 0x5580, 0x02 },
282 { 0x5583, 0x40 },
283 { 0x5584, 0x10 },
284 { 0x5589, 0x10 },
285 { 0x558a, 0x00 },
286 { 0x558b, 0xf8 },
287 { 0x5800, 0x3f },
288 { 0x5801, 0x16 },
289 { 0x5802, 0x0e },
290 { 0x5803, 0x0d },
291 { 0x5804, 0x17 },
292 { 0x5805, 0x3f },
293 { 0x5806, 0x0b },
294 { 0x5807, 0x06 },
295 { 0x5808, 0x04 },
296 { 0x5809, 0x04 },
297 { 0x580a, 0x06 },
298 { 0x580b, 0x0b },
299 { 0x580c, 0x09 },
300 { 0x580d, 0x03 },
301 { 0x580e, 0x00 },
302 { 0x580f, 0x00 },
303 { 0x5810, 0x03 },
304 { 0x5811, 0x08 },
305 { 0x5812, 0x0a },
306 { 0x5813, 0x03 },
307 { 0x5814, 0x00 },
308 { 0x5815, 0x00 },
309 { 0x5816, 0x04 },
310 { 0x5817, 0x09 },
311 { 0x5818, 0x0f },
312 { 0x5819, 0x08 },
313 { 0x581a, 0x06 },
314 { 0x581b, 0x06 },
315 { 0x581c, 0x08 },
316 { 0x581d, 0x0c },
317 { 0x581e, 0x3f },
318 { 0x581f, 0x1e },
319 { 0x5820, 0x12 },
320 { 0x5821, 0x13 },
321 { 0x5822, 0x21 },
322 { 0x5823, 0x3f },
323 { 0x5824, 0x68 },
324 { 0x5825, 0x28 },
325 { 0x5826, 0x2c },
326 { 0x5827, 0x28 },
327 { 0x5828, 0x08 },
328 { 0x5829, 0x48 },
329 { 0x582a, 0x64 },
330 { 0x582b, 0x62 },
331 { 0x582c, 0x64 },
332 { 0x582d, 0x28 },
333 { 0x582e, 0x46 },
334 { 0x582f, 0x62 },
335 { 0x5830, 0x60 },
336 { 0x5831, 0x62 },
337 { 0x5832, 0x26 },
338 { 0x5833, 0x48 },
339 { 0x5834, 0x66 },
340 { 0x5835, 0x44 },
341 { 0x5836, 0x64 },
342 { 0x5837, 0x28 },
343 { 0x5838, 0x66 },
344 { 0x5839, 0x48 },
345 { 0x583a, 0x2c },
346 { 0x583b, 0x28 },
347 { 0x583c, 0x26 },
348 { 0x583d, 0xae },
349 { 0x5025, 0x00 },
350 { 0x3a0f, 0x30 },
351 { 0x3a10, 0x28 },
352 { 0x3a1b, 0x30 },
353 { 0x3a1e, 0x26 },
354 { 0x3a11, 0x60 },
355 { 0x3a1f, 0x14 },
356 { 0x0601, 0x02 },
357 { 0x3008, 0x42 },
358 { 0x3008, 0x02 },
359 { OV5645_IO_MIPI_CTRL00, 0x40 },
360 { OV5645_MIPI_CTRL00, 0x24 },
361 { OV5645_PAD_OUTPUT00, 0x70 }
362};
363
364static const struct reg_value ov5645_setting_sxga[] = {
365 { 0x3612, 0xa9 },
366 { 0x3614, 0x50 },
367 { 0x3618, 0x00 },
368 { 0x3034, 0x18 },
369 { 0x3035, 0x21 },
370 { 0x3036, 0x70 },
371 { 0x3600, 0x09 },
372 { 0x3601, 0x43 },
373 { 0x3708, 0x66 },
374 { 0x370c, 0xc3 },
375 { 0x3800, 0x00 },
376 { 0x3801, 0x00 },
377 { 0x3802, 0x00 },
378 { 0x3803, 0x06 },
379 { 0x3804, 0x0a },
380 { 0x3805, 0x3f },
381 { 0x3806, 0x07 },
382 { 0x3807, 0x9d },
383 { 0x3808, 0x05 },
384 { 0x3809, 0x00 },
385 { 0x380a, 0x03 },
386 { 0x380b, 0xc0 },
387 { 0x380c, 0x07 },
388 { 0x380d, 0x68 },
389 { 0x380e, 0x03 },
390 { 0x380f, 0xd8 },
391 { 0x3813, 0x06 },
392 { 0x3814, 0x31 },
393 { 0x3815, 0x31 },
394 { 0x3820, 0x47 },
395 { 0x3a02, 0x03 },
396 { 0x3a03, 0xd8 },
397 { 0x3a08, 0x01 },
398 { 0x3a09, 0xf8 },
399 { 0x3a0a, 0x01 },
400 { 0x3a0b, 0xa4 },
401 { 0x3a0e, 0x02 },
402 { 0x3a0d, 0x02 },
403 { 0x3a14, 0x03 },
404 { 0x3a15, 0xd8 },
405 { 0x3a18, 0x00 },
406 { 0x4004, 0x02 },
407 { 0x4005, 0x18 },
408 { 0x4300, 0x32 },
409 { 0x4202, 0x00 }
410};
411
412static const struct reg_value ov5645_setting_1080p[] = {
413 { 0x3612, 0xab },
414 { 0x3614, 0x50 },
415 { 0x3618, 0x04 },
416 { 0x3034, 0x18 },
417 { 0x3035, 0x11 },
418 { 0x3036, 0x54 },
419 { 0x3600, 0x08 },
420 { 0x3601, 0x33 },
421 { 0x3708, 0x63 },
422 { 0x370c, 0xc0 },
423 { 0x3800, 0x01 },
424 { 0x3801, 0x50 },
425 { 0x3802, 0x01 },
426 { 0x3803, 0xb2 },
427 { 0x3804, 0x08 },
428 { 0x3805, 0xef },
429 { 0x3806, 0x05 },
430 { 0x3807, 0xf1 },
431 { 0x3808, 0x07 },
432 { 0x3809, 0x80 },
433 { 0x380a, 0x04 },
434 { 0x380b, 0x38 },
435 { 0x380c, 0x09 },
436 { 0x380d, 0xc4 },
437 { 0x380e, 0x04 },
438 { 0x380f, 0x60 },
439 { 0x3813, 0x04 },
440 { 0x3814, 0x11 },
441 { 0x3815, 0x11 },
442 { 0x3820, 0x47 },
443 { 0x4514, 0x88 },
444 { 0x3a02, 0x04 },
445 { 0x3a03, 0x60 },
446 { 0x3a08, 0x01 },
447 { 0x3a09, 0x50 },
448 { 0x3a0a, 0x01 },
449 { 0x3a0b, 0x18 },
450 { 0x3a0e, 0x03 },
451 { 0x3a0d, 0x04 },
452 { 0x3a14, 0x04 },
453 { 0x3a15, 0x60 },
454 { 0x3a18, 0x00 },
455 { 0x4004, 0x06 },
456 { 0x4005, 0x18 },
457 { 0x4300, 0x32 },
458 { 0x4202, 0x00 },
459 { 0x4837, 0x0b }
460};
461
462static const struct reg_value ov5645_setting_full[] = {
463 { 0x3612, 0xab },
464 { 0x3614, 0x50 },
465 { 0x3618, 0x04 },
466 { 0x3034, 0x18 },
467 { 0x3035, 0x11 },
468 { 0x3036, 0x54 },
469 { 0x3600, 0x08 },
470 { 0x3601, 0x33 },
471 { 0x3708, 0x63 },
472 { 0x370c, 0xc0 },
473 { 0x3800, 0x00 },
474 { 0x3801, 0x00 },
475 { 0x3802, 0x00 },
476 { 0x3803, 0x00 },
477 { 0x3804, 0x0a },
478 { 0x3805, 0x3f },
479 { 0x3806, 0x07 },
480 { 0x3807, 0x9f },
481 { 0x3808, 0x0a },
482 { 0x3809, 0x20 },
483 { 0x380a, 0x07 },
484 { 0x380b, 0x98 },
485 { 0x380c, 0x0b },
486 { 0x380d, 0x1c },
487 { 0x380e, 0x07 },
488 { 0x380f, 0xb0 },
489 { 0x3813, 0x06 },
490 { 0x3814, 0x11 },
491 { 0x3815, 0x11 },
492 { 0x3820, 0x47 },
493 { 0x4514, 0x88 },
494 { 0x3a02, 0x07 },
495 { 0x3a03, 0xb0 },
496 { 0x3a08, 0x01 },
497 { 0x3a09, 0x27 },
498 { 0x3a0a, 0x00 },
499 { 0x3a0b, 0xf6 },
500 { 0x3a0e, 0x06 },
501 { 0x3a0d, 0x08 },
502 { 0x3a14, 0x07 },
503 { 0x3a15, 0xb0 },
504 { 0x3a18, 0x01 },
505 { 0x4004, 0x06 },
506 { 0x4005, 0x18 },
507 { 0x4300, 0x32 },
508 { 0x4837, 0x0b },
509 { 0x4202, 0x00 }
510};
511
512static const s64 link_freq[] = {
513 224000000,
514 336000000
515};
516
517static const struct ov5645_mode_info ov5645_mode_info_data[] = {
518 {
519 .width = 1280,
520 .height = 960,
521 .data = ov5645_setting_sxga,
522 .data_size = ARRAY_SIZE(ov5645_setting_sxga),
523 .pixel_clock = 112000000,
524 .link_freq = 0
525 },
526 {
527 .width = 1920,
528 .height = 1080,
529 .data = ov5645_setting_1080p,
530 .data_size = ARRAY_SIZE(ov5645_setting_1080p),
531 .pixel_clock = 168000000,
532 .link_freq = 1
533 },
534 {
535 .width = 2592,
536 .height = 1944,
537 .data = ov5645_setting_full,
538 .data_size = ARRAY_SIZE(ov5645_setting_full),
539 .pixel_clock = 168000000,
540 .link_freq = 1
541 },
542};
543
544static int ov5645_write_reg(struct ov5645 *ov5645, u16 reg, u8 val)
545{
546 u8 regbuf[3];
547 int ret;
548
549 regbuf[0] = reg >> 8;
550 regbuf[1] = reg & 0xff;
551 regbuf[2] = val;
552
553 ret = i2c_master_send(ov5645->i2c_client, regbuf, 3);
554 if (ret < 0) {
555 dev_err(ov5645->dev, "%s: write reg error %d: reg=%x, val=%x\n",
556 __func__, ret, reg, val);
557 return ret;
558 }
559
560 return 0;
561}
562
563static int ov5645_read_reg(struct ov5645 *ov5645, u16 reg, u8 *val)
564{
565 u8 regbuf[2];
566 int ret;
567
568 regbuf[0] = reg >> 8;
569 regbuf[1] = reg & 0xff;
570
571 ret = i2c_master_send(ov5645->i2c_client, regbuf, 2);
572 if (ret < 0) {
573 dev_err(ov5645->dev, "%s: write reg error %d: reg=%x\n",
574 __func__, ret, reg);
575 return ret;
576 }
577
578 ret = i2c_master_recv(ov5645->i2c_client, val, 1);
579 if (ret < 0) {
580 dev_err(ov5645->dev, "%s: read reg error %d: reg=%x\n",
581 __func__, ret, reg);
582 return ret;
583 }
584
585 return 0;
586}
587
588static int ov5645_set_aec_mode(struct ov5645 *ov5645, u32 mode)
589{
590 u8 val = ov5645->aec_pk_manual;
591 int ret;
592
593 if (mode == V4L2_EXPOSURE_AUTO)
594 val &= ~OV5645_AEC_MANUAL_ENABLE;
595 else
596 val |= OV5645_AEC_MANUAL_ENABLE;
597
598 ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
599 if (!ret)
600 ov5645->aec_pk_manual = val;
601
602 return ret;
603}
604
605static int ov5645_set_agc_mode(struct ov5645 *ov5645, u32 enable)
606{
607 u8 val = ov5645->aec_pk_manual;
608 int ret;
609
610 if (enable)
611 val &= ~OV5645_AGC_MANUAL_ENABLE;
612 else
613 val |= OV5645_AGC_MANUAL_ENABLE;
614
615 ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
616 if (!ret)
617 ov5645->aec_pk_manual = val;
618
619 return ret;
620}
621
622static int ov5645_set_register_array(struct ov5645 *ov5645,
623 const struct reg_value *settings,
624 unsigned int num_settings)
625{
626 unsigned int i;
627 int ret;
628
629 for (i = 0; i < num_settings; ++i, ++settings) {
630 ret = ov5645_write_reg(ov5645, settings->reg, settings->val);
631 if (ret < 0)
632 return ret;
633 }
634
635 return 0;
636}
637
638static int ov5645_set_power_on(struct ov5645 *ov5645)
639{
640 int ret;
641
642 ret = regulator_bulk_enable(OV5645_NUM_SUPPLIES, ov5645->supplies);
643 if (ret < 0)
644 return ret;
645
646 ret = clk_prepare_enable(ov5645->xclk);
647 if (ret < 0) {
648 dev_err(ov5645->dev, "clk prepare enable failed\n");
649 regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
650 return ret;
651 }
652
653 usleep_range(5000, 15000);
654 gpiod_set_value_cansleep(ov5645->enable_gpio, 1);
655
656 usleep_range(1000, 2000);
657 gpiod_set_value_cansleep(ov5645->rst_gpio, 0);
658
659 msleep(20);
660
661 return 0;
662}
663
664static void ov5645_set_power_off(struct ov5645 *ov5645)
665{
666 gpiod_set_value_cansleep(ov5645->rst_gpio, 1);
667 gpiod_set_value_cansleep(ov5645->enable_gpio, 0);
668 clk_disable_unprepare(ov5645->xclk);
669 regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
670}
671
672static int ov5645_s_power(struct v4l2_subdev *sd, int on)
673{
674 struct ov5645 *ov5645 = to_ov5645(sd);
675 int ret = 0;
676
677 mutex_lock(&ov5645->power_lock);
678
679
680
681
682 if (ov5645->power_count == !on) {
683 if (on) {
684 ret = ov5645_set_power_on(ov5645);
685 if (ret < 0)
686 goto exit;
687
688 ret = ov5645_set_register_array(ov5645,
689 ov5645_global_init_setting,
690 ARRAY_SIZE(ov5645_global_init_setting));
691 if (ret < 0) {
692 dev_err(ov5645->dev,
693 "could not set init registers\n");
694 ov5645_set_power_off(ov5645);
695 goto exit;
696 }
697
698 usleep_range(500, 1000);
699 } else {
700 ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x58);
701 ov5645_set_power_off(ov5645);
702 }
703 }
704
705
706 ov5645->power_count += on ? 1 : -1;
707 WARN_ON(ov5645->power_count < 0);
708
709exit:
710 mutex_unlock(&ov5645->power_lock);
711
712 return ret;
713}
714
715static int ov5645_set_saturation(struct ov5645 *ov5645, s32 value)
716{
717 u32 reg_value = (value * 0x10) + 0x40;
718 int ret;
719
720 ret = ov5645_write_reg(ov5645, OV5645_SDE_SAT_U, reg_value);
721 if (ret < 0)
722 return ret;
723
724 return ov5645_write_reg(ov5645, OV5645_SDE_SAT_V, reg_value);
725}
726
727static int ov5645_set_hflip(struct ov5645 *ov5645, s32 value)
728{
729 u8 val = ov5645->timing_tc_reg21;
730 int ret;
731
732 if (value == 0)
733 val &= ~(OV5645_SENSOR_MIRROR);
734 else
735 val |= (OV5645_SENSOR_MIRROR);
736
737 ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG21, val);
738 if (!ret)
739 ov5645->timing_tc_reg21 = val;
740
741 return ret;
742}
743
744static int ov5645_set_vflip(struct ov5645 *ov5645, s32 value)
745{
746 u8 val = ov5645->timing_tc_reg20;
747 int ret;
748
749 if (value == 0)
750 val |= (OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
751 else
752 val &= ~(OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
753
754 ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG20, val);
755 if (!ret)
756 ov5645->timing_tc_reg20 = val;
757
758 return ret;
759}
760
761static int ov5645_set_test_pattern(struct ov5645 *ov5645, s32 value)
762{
763 u8 val = 0;
764
765 if (value) {
766 val = OV5645_SET_TEST_PATTERN(value - 1);
767 val |= OV5645_TEST_PATTERN_ENABLE;
768 }
769
770 return ov5645_write_reg(ov5645, OV5645_PRE_ISP_TEST_SETTING_1, val);
771}
772
773static const char * const ov5645_test_pattern_menu[] = {
774 "Disabled",
775 "Vertical Color Bars",
776 "Pseudo-Random Data",
777 "Color Square",
778 "Black Image",
779};
780
781static int ov5645_set_awb(struct ov5645 *ov5645, s32 enable_auto)
782{
783 u8 val = 0;
784
785 if (!enable_auto)
786 val = OV5645_AWB_MANUAL_ENABLE;
787
788 return ov5645_write_reg(ov5645, OV5645_AWB_MANUAL_CONTROL, val);
789}
790
791static int ov5645_s_ctrl(struct v4l2_ctrl *ctrl)
792{
793 struct ov5645 *ov5645 = container_of(ctrl->handler,
794 struct ov5645, ctrls);
795 int ret;
796
797 mutex_lock(&ov5645->power_lock);
798 if (!ov5645->power_count) {
799 mutex_unlock(&ov5645->power_lock);
800 return 0;
801 }
802
803 switch (ctrl->id) {
804 case V4L2_CID_SATURATION:
805 ret = ov5645_set_saturation(ov5645, ctrl->val);
806 break;
807 case V4L2_CID_AUTO_WHITE_BALANCE:
808 ret = ov5645_set_awb(ov5645, ctrl->val);
809 break;
810 case V4L2_CID_AUTOGAIN:
811 ret = ov5645_set_agc_mode(ov5645, ctrl->val);
812 break;
813 case V4L2_CID_EXPOSURE_AUTO:
814 ret = ov5645_set_aec_mode(ov5645, ctrl->val);
815 break;
816 case V4L2_CID_TEST_PATTERN:
817 ret = ov5645_set_test_pattern(ov5645, ctrl->val);
818 break;
819 case V4L2_CID_HFLIP:
820 ret = ov5645_set_hflip(ov5645, ctrl->val);
821 break;
822 case V4L2_CID_VFLIP:
823 ret = ov5645_set_vflip(ov5645, ctrl->val);
824 break;
825 default:
826 ret = -EINVAL;
827 break;
828 }
829
830 mutex_unlock(&ov5645->power_lock);
831
832 return ret;
833}
834
835static const struct v4l2_ctrl_ops ov5645_ctrl_ops = {
836 .s_ctrl = ov5645_s_ctrl,
837};
838
839static int ov5645_enum_mbus_code(struct v4l2_subdev *sd,
840 struct v4l2_subdev_state *sd_state,
841 struct v4l2_subdev_mbus_code_enum *code)
842{
843 if (code->index > 0)
844 return -EINVAL;
845
846 code->code = MEDIA_BUS_FMT_UYVY8_2X8;
847
848 return 0;
849}
850
851static int ov5645_enum_frame_size(struct v4l2_subdev *subdev,
852 struct v4l2_subdev_state *sd_state,
853 struct v4l2_subdev_frame_size_enum *fse)
854{
855 if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
856 return -EINVAL;
857
858 if (fse->index >= ARRAY_SIZE(ov5645_mode_info_data))
859 return -EINVAL;
860
861 fse->min_width = ov5645_mode_info_data[fse->index].width;
862 fse->max_width = ov5645_mode_info_data[fse->index].width;
863 fse->min_height = ov5645_mode_info_data[fse->index].height;
864 fse->max_height = ov5645_mode_info_data[fse->index].height;
865
866 return 0;
867}
868
869static struct v4l2_mbus_framefmt *
870__ov5645_get_pad_format(struct ov5645 *ov5645,
871 struct v4l2_subdev_state *sd_state,
872 unsigned int pad,
873 enum v4l2_subdev_format_whence which)
874{
875 switch (which) {
876 case V4L2_SUBDEV_FORMAT_TRY:
877 return v4l2_subdev_get_try_format(&ov5645->sd, sd_state, pad);
878 case V4L2_SUBDEV_FORMAT_ACTIVE:
879 return &ov5645->fmt;
880 default:
881 return NULL;
882 }
883}
884
885static int ov5645_get_format(struct v4l2_subdev *sd,
886 struct v4l2_subdev_state *sd_state,
887 struct v4l2_subdev_format *format)
888{
889 struct ov5645 *ov5645 = to_ov5645(sd);
890
891 format->format = *__ov5645_get_pad_format(ov5645, sd_state,
892 format->pad,
893 format->which);
894 return 0;
895}
896
897static struct v4l2_rect *
898__ov5645_get_pad_crop(struct ov5645 *ov5645,
899 struct v4l2_subdev_state *sd_state,
900 unsigned int pad, enum v4l2_subdev_format_whence which)
901{
902 switch (which) {
903 case V4L2_SUBDEV_FORMAT_TRY:
904 return v4l2_subdev_get_try_crop(&ov5645->sd, sd_state, pad);
905 case V4L2_SUBDEV_FORMAT_ACTIVE:
906 return &ov5645->crop;
907 default:
908 return NULL;
909 }
910}
911
912static int ov5645_set_format(struct v4l2_subdev *sd,
913 struct v4l2_subdev_state *sd_state,
914 struct v4l2_subdev_format *format)
915{
916 struct ov5645 *ov5645 = to_ov5645(sd);
917 struct v4l2_mbus_framefmt *__format;
918 struct v4l2_rect *__crop;
919 const struct ov5645_mode_info *new_mode;
920 int ret;
921
922 __crop = __ov5645_get_pad_crop(ov5645, sd_state, format->pad,
923 format->which);
924
925 new_mode = v4l2_find_nearest_size(ov5645_mode_info_data,
926 ARRAY_SIZE(ov5645_mode_info_data),
927 width, height,
928 format->format.width, format->format.height);
929
930 __crop->width = new_mode->width;
931 __crop->height = new_mode->height;
932
933 if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
934 ret = v4l2_ctrl_s_ctrl_int64(ov5645->pixel_clock,
935 new_mode->pixel_clock);
936 if (ret < 0)
937 return ret;
938
939 ret = v4l2_ctrl_s_ctrl(ov5645->link_freq,
940 new_mode->link_freq);
941 if (ret < 0)
942 return ret;
943
944 ov5645->current_mode = new_mode;
945 }
946
947 __format = __ov5645_get_pad_format(ov5645, sd_state, format->pad,
948 format->which);
949 __format->width = __crop->width;
950 __format->height = __crop->height;
951 __format->code = MEDIA_BUS_FMT_UYVY8_2X8;
952 __format->field = V4L2_FIELD_NONE;
953 __format->colorspace = V4L2_COLORSPACE_SRGB;
954
955 format->format = *__format;
956
957 return 0;
958}
959
960static int ov5645_entity_init_cfg(struct v4l2_subdev *subdev,
961 struct v4l2_subdev_state *sd_state)
962{
963 struct v4l2_subdev_format fmt = { 0 };
964
965 fmt.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
966 fmt.format.width = 1920;
967 fmt.format.height = 1080;
968
969 ov5645_set_format(subdev, sd_state, &fmt);
970
971 return 0;
972}
973
974static int ov5645_get_selection(struct v4l2_subdev *sd,
975 struct v4l2_subdev_state *sd_state,
976 struct v4l2_subdev_selection *sel)
977{
978 struct ov5645 *ov5645 = to_ov5645(sd);
979
980 if (sel->target != V4L2_SEL_TGT_CROP)
981 return -EINVAL;
982
983 sel->r = *__ov5645_get_pad_crop(ov5645, sd_state, sel->pad,
984 sel->which);
985 return 0;
986}
987
988static int ov5645_s_stream(struct v4l2_subdev *subdev, int enable)
989{
990 struct ov5645 *ov5645 = to_ov5645(subdev);
991 int ret;
992
993 if (enable) {
994 ret = ov5645_set_register_array(ov5645,
995 ov5645->current_mode->data,
996 ov5645->current_mode->data_size);
997 if (ret < 0) {
998 dev_err(ov5645->dev, "could not set mode %dx%d\n",
999 ov5645->current_mode->width,
1000 ov5645->current_mode->height);
1001 return ret;
1002 }
1003 ret = v4l2_ctrl_handler_setup(&ov5645->ctrls);
1004 if (ret < 0) {
1005 dev_err(ov5645->dev, "could not sync v4l2 controls\n");
1006 return ret;
1007 }
1008
1009 ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x45);
1010 if (ret < 0)
1011 return ret;
1012
1013 ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1014 OV5645_SYSTEM_CTRL0_START);
1015 if (ret < 0)
1016 return ret;
1017 } else {
1018 ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x40);
1019 if (ret < 0)
1020 return ret;
1021
1022 ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
1023 OV5645_SYSTEM_CTRL0_STOP);
1024 if (ret < 0)
1025 return ret;
1026 }
1027
1028 return 0;
1029}
1030
1031static const struct v4l2_subdev_core_ops ov5645_core_ops = {
1032 .s_power = ov5645_s_power,
1033};
1034
1035static const struct v4l2_subdev_video_ops ov5645_video_ops = {
1036 .s_stream = ov5645_s_stream,
1037};
1038
1039static const struct v4l2_subdev_pad_ops ov5645_subdev_pad_ops = {
1040 .init_cfg = ov5645_entity_init_cfg,
1041 .enum_mbus_code = ov5645_enum_mbus_code,
1042 .enum_frame_size = ov5645_enum_frame_size,
1043 .get_fmt = ov5645_get_format,
1044 .set_fmt = ov5645_set_format,
1045 .get_selection = ov5645_get_selection,
1046};
1047
1048static const struct v4l2_subdev_ops ov5645_subdev_ops = {
1049 .core = &ov5645_core_ops,
1050 .video = &ov5645_video_ops,
1051 .pad = &ov5645_subdev_pad_ops,
1052};
1053
1054static int ov5645_probe(struct i2c_client *client)
1055{
1056 struct device *dev = &client->dev;
1057 struct device_node *endpoint;
1058 struct ov5645 *ov5645;
1059 u8 chip_id_high, chip_id_low;
1060 unsigned int i;
1061 u32 xclk_freq;
1062 int ret;
1063
1064 ov5645 = devm_kzalloc(dev, sizeof(struct ov5645), GFP_KERNEL);
1065 if (!ov5645)
1066 return -ENOMEM;
1067
1068 ov5645->i2c_client = client;
1069 ov5645->dev = dev;
1070
1071 endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
1072 if (!endpoint) {
1073 dev_err(dev, "endpoint node not found\n");
1074 return -EINVAL;
1075 }
1076
1077 ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
1078 &ov5645->ep);
1079
1080 of_node_put(endpoint);
1081
1082 if (ret < 0) {
1083 dev_err(dev, "parsing endpoint node failed\n");
1084 return ret;
1085 }
1086
1087 if (ov5645->ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
1088 dev_err(dev, "invalid bus type, must be CSI2\n");
1089 return -EINVAL;
1090 }
1091
1092
1093 ov5645->xclk = devm_clk_get(dev, "xclk");
1094 if (IS_ERR(ov5645->xclk)) {
1095 dev_err(dev, "could not get xclk");
1096 return PTR_ERR(ov5645->xclk);
1097 }
1098
1099 ret = of_property_read_u32(dev->of_node, "clock-frequency", &xclk_freq);
1100 if (ret) {
1101 dev_err(dev, "could not get xclk frequency\n");
1102 return ret;
1103 }
1104
1105
1106 if (xclk_freq < 23760000 || xclk_freq > 24240000) {
1107 dev_err(dev, "external clock frequency %u is not supported\n",
1108 xclk_freq);
1109 return -EINVAL;
1110 }
1111
1112 ret = clk_set_rate(ov5645->xclk, xclk_freq);
1113 if (ret) {
1114 dev_err(dev, "could not set xclk frequency\n");
1115 return ret;
1116 }
1117
1118 for (i = 0; i < OV5645_NUM_SUPPLIES; i++)
1119 ov5645->supplies[i].supply = ov5645_supply_name[i];
1120
1121 ret = devm_regulator_bulk_get(dev, OV5645_NUM_SUPPLIES,
1122 ov5645->supplies);
1123 if (ret < 0)
1124 return ret;
1125
1126 ov5645->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
1127 if (IS_ERR(ov5645->enable_gpio)) {
1128 dev_err(dev, "cannot get enable gpio\n");
1129 return PTR_ERR(ov5645->enable_gpio);
1130 }
1131
1132 ov5645->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
1133 if (IS_ERR(ov5645->rst_gpio)) {
1134 dev_err(dev, "cannot get reset gpio\n");
1135 return PTR_ERR(ov5645->rst_gpio);
1136 }
1137
1138 mutex_init(&ov5645->power_lock);
1139
1140 v4l2_ctrl_handler_init(&ov5645->ctrls, 9);
1141 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1142 V4L2_CID_SATURATION, -4, 4, 1, 0);
1143 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1144 V4L2_CID_HFLIP, 0, 1, 1, 0);
1145 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1146 V4L2_CID_VFLIP, 0, 1, 1, 0);
1147 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1148 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1149 v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
1150 V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
1151 v4l2_ctrl_new_std_menu(&ov5645->ctrls, &ov5645_ctrl_ops,
1152 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL,
1153 0, V4L2_EXPOSURE_AUTO);
1154 v4l2_ctrl_new_std_menu_items(&ov5645->ctrls, &ov5645_ctrl_ops,
1155 V4L2_CID_TEST_PATTERN,
1156 ARRAY_SIZE(ov5645_test_pattern_menu) - 1,
1157 0, 0, ov5645_test_pattern_menu);
1158 ov5645->pixel_clock = v4l2_ctrl_new_std(&ov5645->ctrls,
1159 &ov5645_ctrl_ops,
1160 V4L2_CID_PIXEL_RATE,
1161 1, INT_MAX, 1, 1);
1162 ov5645->link_freq = v4l2_ctrl_new_int_menu(&ov5645->ctrls,
1163 &ov5645_ctrl_ops,
1164 V4L2_CID_LINK_FREQ,
1165 ARRAY_SIZE(link_freq) - 1,
1166 0, link_freq);
1167 if (ov5645->link_freq)
1168 ov5645->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1169
1170 ov5645->sd.ctrl_handler = &ov5645->ctrls;
1171
1172 if (ov5645->ctrls.error) {
1173 dev_err(dev, "%s: control initialization error %d\n",
1174 __func__, ov5645->ctrls.error);
1175 ret = ov5645->ctrls.error;
1176 goto free_ctrl;
1177 }
1178
1179 v4l2_i2c_subdev_init(&ov5645->sd, client, &ov5645_subdev_ops);
1180 ov5645->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1181 ov5645->pad.flags = MEDIA_PAD_FL_SOURCE;
1182 ov5645->sd.dev = &client->dev;
1183 ov5645->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1184
1185 ret = media_entity_pads_init(&ov5645->sd.entity, 1, &ov5645->pad);
1186 if (ret < 0) {
1187 dev_err(dev, "could not register media entity\n");
1188 goto free_ctrl;
1189 }
1190
1191 ret = ov5645_s_power(&ov5645->sd, true);
1192 if (ret < 0) {
1193 dev_err(dev, "could not power up OV5645\n");
1194 goto free_entity;
1195 }
1196
1197 ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_HIGH, &chip_id_high);
1198 if (ret < 0 || chip_id_high != OV5645_CHIP_ID_HIGH_BYTE) {
1199 dev_err(dev, "could not read ID high\n");
1200 ret = -ENODEV;
1201 goto power_down;
1202 }
1203 ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_LOW, &chip_id_low);
1204 if (ret < 0 || chip_id_low != OV5645_CHIP_ID_LOW_BYTE) {
1205 dev_err(dev, "could not read ID low\n");
1206 ret = -ENODEV;
1207 goto power_down;
1208 }
1209
1210 dev_info(dev, "OV5645 detected at address 0x%02x\n", client->addr);
1211
1212 ret = ov5645_read_reg(ov5645, OV5645_AEC_PK_MANUAL,
1213 &ov5645->aec_pk_manual);
1214 if (ret < 0) {
1215 dev_err(dev, "could not read AEC/AGC mode\n");
1216 ret = -ENODEV;
1217 goto power_down;
1218 }
1219
1220 ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG20,
1221 &ov5645->timing_tc_reg20);
1222 if (ret < 0) {
1223 dev_err(dev, "could not read vflip value\n");
1224 ret = -ENODEV;
1225 goto power_down;
1226 }
1227
1228 ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG21,
1229 &ov5645->timing_tc_reg21);
1230 if (ret < 0) {
1231 dev_err(dev, "could not read hflip value\n");
1232 ret = -ENODEV;
1233 goto power_down;
1234 }
1235
1236 ov5645_s_power(&ov5645->sd, false);
1237
1238 ret = v4l2_async_register_subdev(&ov5645->sd);
1239 if (ret < 0) {
1240 dev_err(dev, "could not register v4l2 device\n");
1241 goto free_entity;
1242 }
1243
1244 ov5645_entity_init_cfg(&ov5645->sd, NULL);
1245
1246 return 0;
1247
1248power_down:
1249 ov5645_s_power(&ov5645->sd, false);
1250free_entity:
1251 media_entity_cleanup(&ov5645->sd.entity);
1252free_ctrl:
1253 v4l2_ctrl_handler_free(&ov5645->ctrls);
1254 mutex_destroy(&ov5645->power_lock);
1255
1256 return ret;
1257}
1258
1259static int ov5645_remove(struct i2c_client *client)
1260{
1261 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1262 struct ov5645 *ov5645 = to_ov5645(sd);
1263
1264 v4l2_async_unregister_subdev(&ov5645->sd);
1265 media_entity_cleanup(&ov5645->sd.entity);
1266 v4l2_ctrl_handler_free(&ov5645->ctrls);
1267 mutex_destroy(&ov5645->power_lock);
1268
1269 return 0;
1270}
1271
1272static const struct i2c_device_id ov5645_id[] = {
1273 { "ov5645", 0 },
1274 {}
1275};
1276MODULE_DEVICE_TABLE(i2c, ov5645_id);
1277
1278static const struct of_device_id ov5645_of_match[] = {
1279 { .compatible = "ovti,ov5645" },
1280 { }
1281};
1282MODULE_DEVICE_TABLE(of, ov5645_of_match);
1283
1284static struct i2c_driver ov5645_i2c_driver = {
1285 .driver = {
1286 .of_match_table = of_match_ptr(ov5645_of_match),
1287 .name = "ov5645",
1288 },
1289 .probe_new = ov5645_probe,
1290 .remove = ov5645_remove,
1291 .id_table = ov5645_id,
1292};
1293
1294module_i2c_driver(ov5645_i2c_driver);
1295
1296MODULE_DESCRIPTION("Omnivision OV5645 Camera Driver");
1297MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
1298MODULE_LICENSE("GPL v2");
1299
