1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/gpio/consumer.h>
20#include <linux/i2c.h>
21#include <linux/init.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/regmap.h>
25#include <linux/slab.h>
26#include <linux/v4l2-mediabus.h>
27#include <linux/videodev2.h>
28
29#include <media/i2c/ov772x.h>
30
31#include <media/v4l2-ctrls.h>
32#include <media/v4l2-device.h>
33#include <media/v4l2-event.h>
34#include <media/v4l2-fwnode.h>
35#include <media/v4l2-image-sizes.h>
36#include <media/v4l2-subdev.h>
37
38
39
40
41#define GAIN 0x00
42#define BLUE 0x01
43#define RED 0x02
44#define GREEN 0x03
45#define COM1 0x04
46#define BAVG 0x05
47#define GAVG 0x06
48#define RAVG 0x07
49#define AECH 0x08
50#define COM2 0x09
51#define PID 0x0A
52#define VER 0x0B
53#define COM3 0x0C
54#define COM4 0x0D
55#define COM5 0x0E
56#define COM6 0x0F
57#define AEC 0x10
58#define CLKRC 0x11
59#define COM7 0x12
60#define COM8 0x13
61#define COM9 0x14
62#define COM10 0x15
63#define REG16 0x16
64#define HSTART 0x17
65#define HSIZE 0x18
66#define VSTART 0x19
67#define VSIZE 0x1A
68#define PSHFT 0x1B
69#define MIDH 0x1C
70#define MIDL 0x1D
71#define LAEC 0x1F
72#define COM11 0x20
73#define BDBASE 0x22
74#define DBSTEP 0x23
75#define AEW 0x24
76#define AEB 0x25
77#define VPT 0x26
78#define REG28 0x28
79#define HOUTSIZE 0x29
80#define EXHCH 0x2A
81#define EXHCL 0x2B
82#define VOUTSIZE 0x2C
83#define ADVFL 0x2D
84#define ADVFH 0x2E
85#define YAVE 0x2F
86#define LUMHTH 0x30
87#define LUMLTH 0x31
88#define HREF 0x32
89#define DM_LNL 0x33
90#define DM_LNH 0x34
91#define ADOFF_B 0x35
92#define ADOFF_R 0x36
93#define ADOFF_GB 0x37
94#define ADOFF_GR 0x38
95#define OFF_B 0x39
96#define OFF_R 0x3A
97#define OFF_GB 0x3B
98#define OFF_GR 0x3C
99#define COM12 0x3D
100#define COM13 0x3E
101#define COM14 0x3F
102#define COM15 0x40
103#define COM16 0x41
104#define TGT_B 0x42
105#define TGT_R 0x43
106#define TGT_GB 0x44
107#define TGT_GR 0x45
108
109#define LCC0 0x46
110#define LCC1 0x47
111#define LCC2 0x48
112#define LCC3 0x49
113#define LCC4 0x4A
114#define LCC5 0x4B
115#define LCC6 0x4C
116
117#define LC_CTR 0x46
118#define LC_XC 0x47
119#define LC_YC 0x48
120#define LC_COEF 0x49
121#define LC_RADI 0x4A
122#define LC_COEFB 0x4B
123#define LC_COEFR 0x4C
124
125#define FIXGAIN 0x4D
126#define AREF0 0x4E
127#define AREF1 0x4F
128#define AREF2 0x50
129#define AREF3 0x51
130#define AREF4 0x52
131#define AREF5 0x53
132#define AREF6 0x54
133#define AREF7 0x55
134#define UFIX 0x60
135#define VFIX 0x61
136#define AWBB_BLK 0x62
137#define AWB_CTRL0 0x63
138#define DSP_CTRL1 0x64
139#define DSP_CTRL2 0x65
140#define DSP_CTRL3 0x66
141#define DSP_CTRL4 0x67
142#define AWB_BIAS 0x68
143#define AWB_CTRL1 0x69
144#define AWB_CTRL2 0x6A
145#define AWB_CTRL3 0x6B
146#define AWB_CTRL4 0x6C
147#define AWB_CTRL5 0x6D
148#define AWB_CTRL6 0x6E
149#define AWB_CTRL7 0x6F
150#define AWB_CTRL8 0x70
151#define AWB_CTRL9 0x71
152#define AWB_CTRL10 0x72
153#define AWB_CTRL11 0x73
154#define AWB_CTRL12 0x74
155#define AWB_CTRL13 0x75
156#define AWB_CTRL14 0x76
157#define AWB_CTRL15 0x77
158#define AWB_CTRL16 0x78
159#define AWB_CTRL17 0x79
160#define AWB_CTRL18 0x7A
161#define AWB_CTRL19 0x7B
162#define AWB_CTRL20 0x7C
163#define AWB_CTRL21 0x7D
164#define GAM1 0x7E
165#define GAM2 0x7F
166#define GAM3 0x80
167#define GAM4 0x81
168#define GAM5 0x82
169#define GAM6 0x83
170#define GAM7 0x84
171#define GAM8 0x85
172#define GAM9 0x86
173#define GAM10 0x87
174#define GAM11 0x88
175#define GAM12 0x89
176#define GAM13 0x8A
177#define GAM14 0x8B
178#define GAM15 0x8C
179#define SLOP 0x8D
180#define DNSTH 0x8E
181#define EDGE_STRNGT 0x8F
182#define EDGE_TRSHLD 0x90
183#define DNSOFF 0x91
184#define EDGE_UPPER 0x92
185#define EDGE_LOWER 0x93
186#define MTX1 0x94
187#define MTX2 0x95
188#define MTX3 0x96
189#define MTX4 0x97
190#define MTX5 0x98
191#define MTX6 0x99
192#define MTX_CTRL 0x9A
193#define BRIGHT 0x9B
194#define CNTRST 0x9C
195#define CNTRST_CTRL 0x9D
196#define UVAD_J0 0x9E
197#define UVAD_J1 0x9F
198#define SCAL0 0xA0
199#define SCAL1 0xA1
200#define SCAL2 0xA2
201#define FIFODLYM 0xA3
202#define FIFODLYA 0xA4
203#define SDE 0xA6
204#define USAT 0xA7
205#define VSAT 0xA8
206
207#define HUE0 0xA9
208#define HUE1 0xAA
209
210#define HUECOS 0xA9
211#define HUESIN 0xAA
212
213#define SIGN 0xAB
214#define DSPAUTO 0xAC
215
216
217
218
219
220
221#define SOFT_SLEEP_MODE 0x10
222
223#define OCAP_1x 0x00
224#define OCAP_2x 0x01
225#define OCAP_3x 0x02
226#define OCAP_4x 0x03
227
228
229#define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
230#define IMG_MASK (VFLIP_IMG | HFLIP_IMG | SCOLOR_TEST)
231
232#define VFLIP_IMG 0x80
233#define HFLIP_IMG 0x40
234#define SWAP_RGB 0x20
235#define SWAP_YUV 0x10
236#define SWAP_ML 0x08
237
238#define NOTRI_CLOCK 0x04
239
240
241#define NOTRI_DATA 0x02
242
243#define SCOLOR_TEST 0x01
244
245
246
247#define PLL_BYPASS 0x00
248#define PLL_4x 0x40
249#define PLL_6x 0x80
250#define PLL_8x 0xc0
251
252#define AEC_FULL 0x00
253#define AEC_1p2 0x10
254#define AEC_1p4 0x20
255#define AEC_2p3 0x30
256#define COM4_RESERVED 0x01
257
258
259#define AFR_ON_OFF 0x80
260#define AFR_SPPED 0x40
261
262#define AFR_NO_RATE 0x00
263#define AFR_1p2 0x10
264#define AFR_1p4 0x20
265#define AFR_1p8 0x30
266
267#define AF_2x 0x00
268#define AF_4x 0x04
269#define AF_8x 0x08
270#define AF_16x 0x0c
271
272#define AEC_NO_LIMIT 0x01
273
274
275
276#define CLKRC_RESERVED 0x80
277#define CLKRC_DIV(n) ((n) - 1)
278
279
280
281#define SCCB_RESET 0x80
282
283
284#define SLCT_MASK 0x40
285#define SLCT_VGA 0x00
286#define SLCT_QVGA 0x40
287#define ITU656_ON_OFF 0x20
288#define SENSOR_RAW 0x10
289
290#define FMT_MASK 0x0c
291#define FMT_GBR422 0x00
292#define FMT_RGB565 0x04
293#define FMT_RGB555 0x08
294#define FMT_RGB444 0x0c
295
296#define OFMT_MASK 0x03
297#define OFMT_YUV 0x00
298#define OFMT_P_BRAW 0x01
299#define OFMT_RGB 0x02
300#define OFMT_BRAW 0x03
301
302
303#define FAST_ALGO 0x80
304
305#define UNLMT_STEP 0x40
306
307#define BNDF_ON_OFF 0x20
308#define AEC_BND 0x10
309#define AEC_ON_OFF 0x08
310#define AGC_ON 0x04
311#define AWB_ON 0x02
312#define AEC_ON 0x01
313
314
315#define BASE_AECAGC 0x80
316
317#define GAIN_2x 0x00
318#define GAIN_4x 0x10
319#define GAIN_8x 0x20
320#define GAIN_16x 0x30
321#define GAIN_32x 0x40
322#define GAIN_64x 0x50
323#define GAIN_128x 0x60
324#define DROP_VSYNC 0x04
325#define DROP_HREF 0x02
326
327
328#define SGLF_ON_OFF 0x02
329#define SGLF_TRIG 0x01
330
331
332#define HREF_VSTART_SHIFT 6
333#define HREF_HSTART_SHIFT 4
334#define HREF_VSIZE_SHIFT 2
335#define HREF_HSIZE_SHIFT 0
336
337
338#define EXHCH_VSIZE_SHIFT 2
339#define EXHCH_HSIZE_SHIFT 0
340
341
342#define FIFO_ON 0x80
343#define UV_ON_OFF 0x40
344#define YUV444_2_422 0x20
345#define CLR_MTRX_ON_OFF 0x10
346#define INTPLT_ON_OFF 0x08
347#define GMM_ON_OFF 0x04
348#define AUTO_BLK_ON_OFF 0x02
349#define AUTO_WHT_ON_OFF 0x01
350
351
352#define UV_MASK 0x80
353#define UV_ON 0x80
354#define UV_OFF 0x00
355#define CBAR_MASK 0x20
356#define CBAR_ON 0x20
357#define CBAR_OFF 0x00
358
359
360#define DSP_OFMT_YUV 0x00
361#define DSP_OFMT_RGB 0x00
362#define DSP_OFMT_RAW8 0x02
363#define DSP_OFMT_RAW10 0x03
364
365
366#define AWB_ACTRL 0x80
367#define DENOISE_ACTRL 0x40
368#define EDGE_ACTRL 0x20
369#define UV_ACTRL 0x10
370#define SCAL0_ACTRL 0x08
371#define SCAL1_2_ACTRL 0x04
372
373#define OV772X_MAX_WIDTH VGA_WIDTH
374#define OV772X_MAX_HEIGHT VGA_HEIGHT
375
376
377
378
379#define OV7720 0x7720
380#define OV7725 0x7721
381#define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
382
383
384
385
386static struct {
387 unsigned int mult;
388 u8 com4;
389} ov772x_pll[] = {
390 { 1, PLL_BYPASS, },
391 { 4, PLL_4x, },
392 { 6, PLL_6x, },
393 { 8, PLL_8x, },
394};
395
396
397
398
399
400struct ov772x_color_format {
401 u32 code;
402 enum v4l2_colorspace colorspace;
403 u8 dsp3;
404 u8 dsp4;
405 u8 com3;
406 u8 com7;
407};
408
409struct ov772x_win_size {
410 char *name;
411 unsigned char com7_bit;
412 unsigned int sizeimage;
413 struct v4l2_rect rect;
414};
415
416struct ov772x_priv {
417 struct v4l2_subdev subdev;
418 struct v4l2_ctrl_handler hdl;
419 struct clk *clk;
420 struct regmap *regmap;
421 struct ov772x_camera_info *info;
422 struct gpio_desc *pwdn_gpio;
423 struct gpio_desc *rstb_gpio;
424 const struct ov772x_color_format *cfmt;
425 const struct ov772x_win_size *win;
426 struct v4l2_ctrl *vflip_ctrl;
427 struct v4l2_ctrl *hflip_ctrl;
428 unsigned int test_pattern;
429
430 struct v4l2_ctrl *band_filter_ctrl;
431 unsigned int fps;
432
433 struct mutex lock;
434 int power_count;
435 int streaming;
436#ifdef CONFIG_MEDIA_CONTROLLER
437 struct media_pad pad;
438#endif
439 enum v4l2_mbus_type bus_type;
440};
441
442
443
444
445static const struct ov772x_color_format ov772x_cfmts[] = {
446 {
447 .code = MEDIA_BUS_FMT_YUYV8_2X8,
448 .colorspace = V4L2_COLORSPACE_SRGB,
449 .dsp3 = 0x0,
450 .dsp4 = DSP_OFMT_YUV,
451 .com3 = SWAP_YUV,
452 .com7 = OFMT_YUV,
453 },
454 {
455 .code = MEDIA_BUS_FMT_YVYU8_2X8,
456 .colorspace = V4L2_COLORSPACE_SRGB,
457 .dsp3 = UV_ON,
458 .dsp4 = DSP_OFMT_YUV,
459 .com3 = SWAP_YUV,
460 .com7 = OFMT_YUV,
461 },
462 {
463 .code = MEDIA_BUS_FMT_UYVY8_2X8,
464 .colorspace = V4L2_COLORSPACE_SRGB,
465 .dsp3 = 0x0,
466 .dsp4 = DSP_OFMT_YUV,
467 .com3 = 0x0,
468 .com7 = OFMT_YUV,
469 },
470 {
471 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
472 .colorspace = V4L2_COLORSPACE_SRGB,
473 .dsp3 = 0x0,
474 .dsp4 = DSP_OFMT_YUV,
475 .com3 = SWAP_RGB,
476 .com7 = FMT_RGB555 | OFMT_RGB,
477 },
478 {
479 .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
480 .colorspace = V4L2_COLORSPACE_SRGB,
481 .dsp3 = 0x0,
482 .dsp4 = DSP_OFMT_YUV,
483 .com3 = 0x0,
484 .com7 = FMT_RGB555 | OFMT_RGB,
485 },
486 {
487 .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
488 .colorspace = V4L2_COLORSPACE_SRGB,
489 .dsp3 = 0x0,
490 .dsp4 = DSP_OFMT_YUV,
491 .com3 = SWAP_RGB,
492 .com7 = FMT_RGB565 | OFMT_RGB,
493 },
494 {
495 .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
496 .colorspace = V4L2_COLORSPACE_SRGB,
497 .dsp3 = 0x0,
498 .dsp4 = DSP_OFMT_YUV,
499 .com3 = 0x0,
500 .com7 = FMT_RGB565 | OFMT_RGB,
501 },
502 {
503
504
505
506
507 .code = MEDIA_BUS_FMT_SBGGR10_1X10,
508 .colorspace = V4L2_COLORSPACE_SRGB,
509 .dsp3 = 0x0,
510 .dsp4 = DSP_OFMT_RAW10,
511 .com3 = 0x0,
512 .com7 = SENSOR_RAW | OFMT_BRAW,
513 },
514};
515
516
517
518
519
520static const struct ov772x_win_size ov772x_win_sizes[] = {
521 {
522 .name = "VGA",
523 .com7_bit = SLCT_VGA,
524 .sizeimage = 510 * 748,
525 .rect = {
526 .left = 140,
527 .top = 14,
528 .width = VGA_WIDTH,
529 .height = VGA_HEIGHT,
530 },
531 }, {
532 .name = "QVGA",
533 .com7_bit = SLCT_QVGA,
534 .sizeimage = 278 * 576,
535 .rect = {
536 .left = 252,
537 .top = 6,
538 .width = QVGA_WIDTH,
539 .height = QVGA_HEIGHT,
540 },
541 },
542};
543
544static const char * const ov772x_test_pattern_menu[] = {
545 "Disabled",
546 "Vertical Color Bar Type 1",
547};
548
549
550
551
552static const unsigned int ov772x_frame_intervals[] = { 5, 10, 15, 20, 30, 60 };
553
554
555
556
557
558static struct ov772x_priv *to_ov772x(struct v4l2_subdev *sd)
559{
560 return container_of(sd, struct ov772x_priv, subdev);
561}
562
563static int ov772x_reset(struct ov772x_priv *priv)
564{
565 int ret;
566
567 ret = regmap_write(priv->regmap, COM7, SCCB_RESET);
568 if (ret < 0)
569 return ret;
570
571 usleep_range(1000, 5000);
572
573 return regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE,
574 SOFT_SLEEP_MODE);
575}
576
577
578
579
580
581static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
582{
583 struct i2c_client *client = v4l2_get_subdevdata(sd);
584 struct ov772x_priv *priv = to_ov772x(sd);
585 int ret = 0;
586
587 mutex_lock(&priv->lock);
588
589 if (priv->streaming == enable)
590 goto done;
591
592 if (priv->bus_type == V4L2_MBUS_BT656) {
593 ret = regmap_update_bits(priv->regmap, COM7, ITU656_ON_OFF,
594 enable ?
595 ITU656_ON_OFF : ~ITU656_ON_OFF);
596 if (ret)
597 goto done;
598 }
599
600 ret = regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE,
601 enable ? 0 : SOFT_SLEEP_MODE);
602 if (ret)
603 goto done;
604
605 if (enable) {
606 dev_dbg(&client->dev, "format %d, win %s\n",
607 priv->cfmt->code, priv->win->name);
608 }
609 priv->streaming = enable;
610
611done:
612 mutex_unlock(&priv->lock);
613
614 return ret;
615}
616
617static unsigned int ov772x_select_fps(struct ov772x_priv *priv,
618 struct v4l2_fract *tpf)
619{
620 unsigned int fps = tpf->numerator ?
621 tpf->denominator / tpf->numerator :
622 tpf->denominator;
623 unsigned int best_diff;
624 unsigned int diff;
625 unsigned int idx;
626 unsigned int i;
627
628
629 best_diff = ~0L;
630 for (i = 0, idx = 0; i < ARRAY_SIZE(ov772x_frame_intervals); i++) {
631 diff = abs(fps - ov772x_frame_intervals[i]);
632 if (diff < best_diff) {
633 idx = i;
634 best_diff = diff;
635 }
636 }
637
638 return ov772x_frame_intervals[idx];
639}
640
641static int ov772x_set_frame_rate(struct ov772x_priv *priv,
642 unsigned int fps,
643 const struct ov772x_color_format *cfmt,
644 const struct ov772x_win_size *win)
645{
646 unsigned long fin = clk_get_rate(priv->clk);
647 unsigned int best_diff;
648 unsigned int fsize;
649 unsigned int pclk;
650 unsigned int diff;
651 unsigned int i;
652 u8 clkrc = 0;
653 u8 com4 = 0;
654 int ret;
655
656
657 switch (cfmt->com7 & OFMT_MASK) {
658 case OFMT_BRAW:
659 fsize = win->sizeimage;
660 break;
661 case OFMT_RGB:
662 case OFMT_YUV:
663 default:
664 fsize = win->sizeimage * 2;
665 break;
666 }
667
668 pclk = fps * fsize;
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691 best_diff = ~0L;
692 for (i = 0; i < ARRAY_SIZE(ov772x_pll); i++) {
693 unsigned int pll_mult = ov772x_pll[i].mult;
694 unsigned int pll_out = pll_mult * fin;
695 unsigned int t_pclk;
696 unsigned int div;
697
698 if (pll_out < pclk)
699 continue;
700
701 div = DIV_ROUND_CLOSEST(pll_out, pclk);
702 t_pclk = DIV_ROUND_CLOSEST(fin * pll_mult, div);
703 diff = abs(pclk - t_pclk);
704 if (diff < best_diff) {
705 best_diff = diff;
706 clkrc = CLKRC_DIV(div);
707 com4 = ov772x_pll[i].com4;
708 }
709 }
710
711 ret = regmap_write(priv->regmap, COM4, com4 | COM4_RESERVED);
712 if (ret < 0)
713 return ret;
714
715 ret = regmap_write(priv->regmap, CLKRC, clkrc | CLKRC_RESERVED);
716 if (ret < 0)
717 return ret;
718
719 return 0;
720}
721
722static int ov772x_g_frame_interval(struct v4l2_subdev *sd,
723 struct v4l2_subdev_frame_interval *ival)
724{
725 struct ov772x_priv *priv = to_ov772x(sd);
726 struct v4l2_fract *tpf = &ival->interval;
727
728 tpf->numerator = 1;
729 tpf->denominator = priv->fps;
730
731 return 0;
732}
733
734static int ov772x_s_frame_interval(struct v4l2_subdev *sd,
735 struct v4l2_subdev_frame_interval *ival)
736{
737 struct ov772x_priv *priv = to_ov772x(sd);
738 struct v4l2_fract *tpf = &ival->interval;
739 unsigned int fps;
740 int ret = 0;
741
742 mutex_lock(&priv->lock);
743
744 if (priv->streaming) {
745 ret = -EBUSY;
746 goto error;
747 }
748
749 fps = ov772x_select_fps(priv, tpf);
750
751
752
753
754
755
756 if (priv->power_count > 0) {
757 ret = ov772x_set_frame_rate(priv, fps, priv->cfmt, priv->win);
758 if (ret)
759 goto error;
760 }
761
762 tpf->numerator = 1;
763 tpf->denominator = fps;
764 priv->fps = fps;
765
766error:
767 mutex_unlock(&priv->lock);
768
769 return ret;
770}
771
772static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
773{
774 struct ov772x_priv *priv = container_of(ctrl->handler,
775 struct ov772x_priv, hdl);
776 struct regmap *regmap = priv->regmap;
777 int ret = 0;
778 u8 val;
779
780
781
782
783
784
785
786
787 if (priv->power_count == 0)
788 return 0;
789
790 switch (ctrl->id) {
791 case V4L2_CID_VFLIP:
792 val = ctrl->val ? VFLIP_IMG : 0x00;
793 if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
794 val ^= VFLIP_IMG;
795 return regmap_update_bits(regmap, COM3, VFLIP_IMG, val);
796 case V4L2_CID_HFLIP:
797 val = ctrl->val ? HFLIP_IMG : 0x00;
798 if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
799 val ^= HFLIP_IMG;
800 return regmap_update_bits(regmap, COM3, HFLIP_IMG, val);
801 case V4L2_CID_BAND_STOP_FILTER:
802 if (!ctrl->val) {
803
804 ret = regmap_update_bits(regmap, BDBASE, 0xff, 0xff);
805 if (!ret)
806 ret = regmap_update_bits(regmap, COM8,
807 BNDF_ON_OFF, 0);
808 } else {
809
810 val = 256 - ctrl->val;
811 ret = regmap_update_bits(regmap, COM8,
812 BNDF_ON_OFF, BNDF_ON_OFF);
813 if (!ret)
814 ret = regmap_update_bits(regmap, BDBASE,
815 0xff, val);
816 }
817
818 return ret;
819 case V4L2_CID_TEST_PATTERN:
820 priv->test_pattern = ctrl->val;
821 return 0;
822 }
823
824 return -EINVAL;
825}
826
827#ifdef CONFIG_VIDEO_ADV_DEBUG
828static int ov772x_g_register(struct v4l2_subdev *sd,
829 struct v4l2_dbg_register *reg)
830{
831 struct ov772x_priv *priv = to_ov772x(sd);
832 int ret;
833 unsigned int val;
834
835 reg->size = 1;
836 if (reg->reg > 0xff)
837 return -EINVAL;
838
839 ret = regmap_read(priv->regmap, reg->reg, &val);
840 if (ret < 0)
841 return ret;
842
843 reg->val = (__u64)val;
844
845 return 0;
846}
847
848static int ov772x_s_register(struct v4l2_subdev *sd,
849 const struct v4l2_dbg_register *reg)
850{
851 struct ov772x_priv *priv = to_ov772x(sd);
852
853 if (reg->reg > 0xff ||
854 reg->val > 0xff)
855 return -EINVAL;
856
857 return regmap_write(priv->regmap, reg->reg, reg->val);
858}
859#endif
860
861static int ov772x_power_on(struct ov772x_priv *priv)
862{
863 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
864 int ret;
865
866 if (priv->clk) {
867 ret = clk_prepare_enable(priv->clk);
868 if (ret)
869 return ret;
870 }
871
872 if (priv->pwdn_gpio) {
873 gpiod_set_value(priv->pwdn_gpio, 1);
874 usleep_range(500, 1000);
875 }
876
877
878
879
880
881
882
883 priv->rstb_gpio = gpiod_get_optional(&client->dev, "reset",
884 GPIOD_OUT_LOW);
885 if (IS_ERR(priv->rstb_gpio)) {
886 dev_info(&client->dev, "Unable to get GPIO \"reset\"");
887 clk_disable_unprepare(priv->clk);
888 return PTR_ERR(priv->rstb_gpio);
889 }
890
891 if (priv->rstb_gpio) {
892 gpiod_set_value(priv->rstb_gpio, 1);
893 usleep_range(500, 1000);
894 gpiod_set_value(priv->rstb_gpio, 0);
895 usleep_range(500, 1000);
896
897 gpiod_put(priv->rstb_gpio);
898 }
899
900 return 0;
901}
902
903static int ov772x_power_off(struct ov772x_priv *priv)
904{
905 clk_disable_unprepare(priv->clk);
906
907 if (priv->pwdn_gpio) {
908 gpiod_set_value(priv->pwdn_gpio, 0);
909 usleep_range(500, 1000);
910 }
911
912 return 0;
913}
914
915static int ov772x_set_params(struct ov772x_priv *priv,
916 const struct ov772x_color_format *cfmt,
917 const struct ov772x_win_size *win);
918
919static int ov772x_s_power(struct v4l2_subdev *sd, int on)
920{
921 struct ov772x_priv *priv = to_ov772x(sd);
922 int ret = 0;
923
924 mutex_lock(&priv->lock);
925
926
927
928
929 if (priv->power_count == !on) {
930 if (on) {
931 ret = ov772x_power_on(priv);
932
933
934
935
936 if (!ret)
937 ret = ov772x_set_params(priv, priv->cfmt,
938 priv->win);
939 } else {
940 ret = ov772x_power_off(priv);
941 }
942 }
943
944 if (!ret) {
945
946 priv->power_count += on ? 1 : -1;
947 WARN(priv->power_count < 0, "Unbalanced power count\n");
948 WARN(priv->power_count > 1, "Duplicated s_power call\n");
949 }
950
951 mutex_unlock(&priv->lock);
952
953 return ret;
954}
955
956static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
957{
958 const struct ov772x_win_size *win = &ov772x_win_sizes[0];
959 u32 best_diff = UINT_MAX;
960 unsigned int i;
961
962 for (i = 0; i < ARRAY_SIZE(ov772x_win_sizes); ++i) {
963 u32 diff = abs(width - ov772x_win_sizes[i].rect.width)
964 + abs(height - ov772x_win_sizes[i].rect.height);
965 if (diff < best_diff) {
966 best_diff = diff;
967 win = &ov772x_win_sizes[i];
968 }
969 }
970
971 return win;
972}
973
974static void ov772x_select_params(const struct v4l2_mbus_framefmt *mf,
975 const struct ov772x_color_format **cfmt,
976 const struct ov772x_win_size **win)
977{
978 unsigned int i;
979
980
981 *cfmt = &ov772x_cfmts[0];
982
983 for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
984 if (mf->code == ov772x_cfmts[i].code) {
985 *cfmt = &ov772x_cfmts[i];
986 break;
987 }
988 }
989
990
991 *win = ov772x_select_win(mf->width, mf->height);
992}
993
994static int ov772x_edgectrl(struct ov772x_priv *priv)
995{
996 struct regmap *regmap = priv->regmap;
997 int ret;
998
999 if (!priv->info)
1000 return 0;
1001
1002 if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
1003
1004
1005
1006
1007
1008
1009
1010 ret = regmap_update_bits(regmap, DSPAUTO, EDGE_ACTRL, 0x00);
1011 if (ret < 0)
1012 return ret;
1013
1014 ret = regmap_update_bits(regmap, EDGE_TRSHLD,
1015 OV772X_EDGE_THRESHOLD_MASK,
1016 priv->info->edgectrl.threshold);
1017 if (ret < 0)
1018 return ret;
1019
1020 ret = regmap_update_bits(regmap, EDGE_STRNGT,
1021 OV772X_EDGE_STRENGTH_MASK,
1022 priv->info->edgectrl.strength);
1023 if (ret < 0)
1024 return ret;
1025
1026 } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
1027
1028
1029
1030
1031
1032 ret = regmap_update_bits(regmap, EDGE_UPPER,
1033 OV772X_EDGE_UPPER_MASK,
1034 priv->info->edgectrl.upper);
1035 if (ret < 0)
1036 return ret;
1037
1038 ret = regmap_update_bits(regmap, EDGE_LOWER,
1039 OV772X_EDGE_LOWER_MASK,
1040 priv->info->edgectrl.lower);
1041 if (ret < 0)
1042 return ret;
1043 }
1044
1045 return 0;
1046}
1047
1048static int ov772x_set_params(struct ov772x_priv *priv,
1049 const struct ov772x_color_format *cfmt,
1050 const struct ov772x_win_size *win)
1051{
1052 int ret;
1053 u8 val;
1054
1055
1056 ov772x_reset(priv);
1057
1058
1059 ret = ov772x_edgectrl(priv);
1060 if (ret < 0)
1061 return ret;
1062
1063
1064 ret = regmap_write(priv->regmap, HSTART, win->rect.left >> 2);
1065 if (ret < 0)
1066 goto ov772x_set_fmt_error;
1067 ret = regmap_write(priv->regmap, HSIZE, win->rect.width >> 2);
1068 if (ret < 0)
1069 goto ov772x_set_fmt_error;
1070 ret = regmap_write(priv->regmap, VSTART, win->rect.top >> 1);
1071 if (ret < 0)
1072 goto ov772x_set_fmt_error;
1073 ret = regmap_write(priv->regmap, VSIZE, win->rect.height >> 1);
1074 if (ret < 0)
1075 goto ov772x_set_fmt_error;
1076 ret = regmap_write(priv->regmap, HOUTSIZE, win->rect.width >> 2);
1077 if (ret < 0)
1078 goto ov772x_set_fmt_error;
1079 ret = regmap_write(priv->regmap, VOUTSIZE, win->rect.height >> 1);
1080 if (ret < 0)
1081 goto ov772x_set_fmt_error;
1082 ret = regmap_write(priv->regmap, HREF,
1083 ((win->rect.top & 1) << HREF_VSTART_SHIFT) |
1084 ((win->rect.left & 3) << HREF_HSTART_SHIFT) |
1085 ((win->rect.height & 1) << HREF_VSIZE_SHIFT) |
1086 ((win->rect.width & 3) << HREF_HSIZE_SHIFT));
1087 if (ret < 0)
1088 goto ov772x_set_fmt_error;
1089 ret = regmap_write(priv->regmap, EXHCH,
1090 ((win->rect.height & 1) << EXHCH_VSIZE_SHIFT) |
1091 ((win->rect.width & 3) << EXHCH_HSIZE_SHIFT));
1092 if (ret < 0)
1093 goto ov772x_set_fmt_error;
1094
1095
1096 val = cfmt->dsp3;
1097 if (val) {
1098 ret = regmap_update_bits(priv->regmap, DSP_CTRL3, UV_MASK, val);
1099 if (ret < 0)
1100 goto ov772x_set_fmt_error;
1101 }
1102
1103
1104 if (cfmt->dsp4) {
1105 ret = regmap_write(priv->regmap, DSP_CTRL4, cfmt->dsp4);
1106 if (ret < 0)
1107 goto ov772x_set_fmt_error;
1108 }
1109
1110
1111 val = cfmt->com3;
1112 if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
1113 val |= VFLIP_IMG;
1114 if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
1115 val |= HFLIP_IMG;
1116 if (priv->vflip_ctrl->val)
1117 val ^= VFLIP_IMG;
1118 if (priv->hflip_ctrl->val)
1119 val ^= HFLIP_IMG;
1120 if (priv->test_pattern)
1121 val |= SCOLOR_TEST;
1122
1123 ret = regmap_update_bits(priv->regmap, COM3, SWAP_MASK | IMG_MASK, val);
1124 if (ret < 0)
1125 goto ov772x_set_fmt_error;
1126
1127
1128 ret = regmap_write(priv->regmap, COM7, win->com7_bit | cfmt->com7);
1129 if (ret < 0)
1130 goto ov772x_set_fmt_error;
1131
1132
1133 ret = ov772x_set_frame_rate(priv, priv->fps, cfmt, win);
1134 if (ret < 0)
1135 goto ov772x_set_fmt_error;
1136
1137
1138 if (priv->band_filter_ctrl->val) {
1139 unsigned short band_filter = priv->band_filter_ctrl->val;
1140
1141 ret = regmap_update_bits(priv->regmap, COM8,
1142 BNDF_ON_OFF, BNDF_ON_OFF);
1143 if (!ret)
1144 ret = regmap_update_bits(priv->regmap, BDBASE,
1145 0xff, 256 - band_filter);
1146 if (ret < 0)
1147 goto ov772x_set_fmt_error;
1148 }
1149
1150 return ret;
1151
1152ov772x_set_fmt_error:
1153
1154 ov772x_reset(priv);
1155
1156 return ret;
1157}
1158
1159static int ov772x_get_selection(struct v4l2_subdev *sd,
1160 struct v4l2_subdev_state *sd_state,
1161 struct v4l2_subdev_selection *sel)
1162{
1163 struct ov772x_priv *priv = to_ov772x(sd);
1164
1165 if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
1166 return -EINVAL;
1167
1168 sel->r.left = 0;
1169 sel->r.top = 0;
1170 switch (sel->target) {
1171 case V4L2_SEL_TGT_CROP_BOUNDS:
1172 case V4L2_SEL_TGT_CROP:
1173 sel->r.width = priv->win->rect.width;
1174 sel->r.height = priv->win->rect.height;
1175 return 0;
1176 default:
1177 return -EINVAL;
1178 }
1179}
1180
1181static int ov772x_get_fmt(struct v4l2_subdev *sd,
1182 struct v4l2_subdev_state *sd_state,
1183 struct v4l2_subdev_format *format)
1184{
1185 struct v4l2_mbus_framefmt *mf = &format->format;
1186 struct ov772x_priv *priv = to_ov772x(sd);
1187
1188 if (format->pad)
1189 return -EINVAL;
1190
1191 mf->width = priv->win->rect.width;
1192 mf->height = priv->win->rect.height;
1193 mf->code = priv->cfmt->code;
1194 mf->colorspace = priv->cfmt->colorspace;
1195 mf->field = V4L2_FIELD_NONE;
1196
1197 return 0;
1198}
1199
1200static int ov772x_set_fmt(struct v4l2_subdev *sd,
1201 struct v4l2_subdev_state *sd_state,
1202 struct v4l2_subdev_format *format)
1203{
1204 struct ov772x_priv *priv = to_ov772x(sd);
1205 struct v4l2_mbus_framefmt *mf = &format->format;
1206 const struct ov772x_color_format *cfmt;
1207 const struct ov772x_win_size *win;
1208 int ret = 0;
1209
1210 if (format->pad)
1211 return -EINVAL;
1212
1213 ov772x_select_params(mf, &cfmt, &win);
1214
1215 mf->code = cfmt->code;
1216 mf->width = win->rect.width;
1217 mf->height = win->rect.height;
1218 mf->field = V4L2_FIELD_NONE;
1219 mf->colorspace = cfmt->colorspace;
1220 mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1221 mf->quantization = V4L2_QUANTIZATION_DEFAULT;
1222 mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
1223
1224 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
1225 sd_state->pads->try_fmt = *mf;
1226 return 0;
1227 }
1228
1229 mutex_lock(&priv->lock);
1230
1231 if (priv->streaming) {
1232 ret = -EBUSY;
1233 goto error;
1234 }
1235
1236
1237
1238
1239
1240
1241 if (priv->power_count > 0) {
1242 ret = ov772x_set_params(priv, cfmt, win);
1243 if (ret < 0)
1244 goto error;
1245 }
1246 priv->win = win;
1247 priv->cfmt = cfmt;
1248
1249error:
1250 mutex_unlock(&priv->lock);
1251
1252 return ret;
1253}
1254
1255static int ov772x_video_probe(struct ov772x_priv *priv)
1256{
1257 struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
1258 int pid, ver, midh, midl;
1259 const char *devname;
1260 int ret;
1261
1262 ret = ov772x_power_on(priv);
1263 if (ret < 0)
1264 return ret;
1265
1266
1267 ret = regmap_read(priv->regmap, PID, &pid);
1268 if (ret < 0)
1269 return ret;
1270 ret = regmap_read(priv->regmap, VER, &ver);
1271 if (ret < 0)
1272 return ret;
1273
1274 switch (VERSION(pid, ver)) {
1275 case OV7720:
1276 devname = "ov7720";
1277 break;
1278 case OV7725:
1279 devname = "ov7725";
1280 break;
1281 default:
1282 dev_err(&client->dev,
1283 "Product ID error %x:%x\n", pid, ver);
1284 ret = -ENODEV;
1285 goto done;
1286 }
1287
1288 ret = regmap_read(priv->regmap, MIDH, &midh);
1289 if (ret < 0)
1290 return ret;
1291 ret = regmap_read(priv->regmap, MIDL, &midl);
1292 if (ret < 0)
1293 return ret;
1294
1295 dev_info(&client->dev,
1296 "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
1297 devname, pid, ver, midh, midl);
1298
1299 ret = v4l2_ctrl_handler_setup(&priv->hdl);
1300
1301done:
1302 ov772x_power_off(priv);
1303
1304 return ret;
1305}
1306
1307static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
1308 .s_ctrl = ov772x_s_ctrl,
1309};
1310
1311static const struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
1312 .log_status = v4l2_ctrl_subdev_log_status,
1313 .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
1314 .unsubscribe_event = v4l2_event_subdev_unsubscribe,
1315#ifdef CONFIG_VIDEO_ADV_DEBUG
1316 .g_register = ov772x_g_register,
1317 .s_register = ov772x_s_register,
1318#endif
1319 .s_power = ov772x_s_power,
1320};
1321
1322static int ov772x_enum_frame_interval(struct v4l2_subdev *sd,
1323 struct v4l2_subdev_state *sd_state,
1324 struct v4l2_subdev_frame_interval_enum *fie)
1325{
1326 if (fie->pad || fie->index >= ARRAY_SIZE(ov772x_frame_intervals))
1327 return -EINVAL;
1328
1329 if (fie->width != VGA_WIDTH && fie->width != QVGA_WIDTH)
1330 return -EINVAL;
1331 if (fie->height != VGA_HEIGHT && fie->height != QVGA_HEIGHT)
1332 return -EINVAL;
1333
1334 fie->interval.numerator = 1;
1335 fie->interval.denominator = ov772x_frame_intervals[fie->index];
1336
1337 return 0;
1338}
1339
1340static int ov772x_enum_mbus_code(struct v4l2_subdev *sd,
1341 struct v4l2_subdev_state *sd_state,
1342 struct v4l2_subdev_mbus_code_enum *code)
1343{
1344 if (code->pad || code->index >= ARRAY_SIZE(ov772x_cfmts))
1345 return -EINVAL;
1346
1347 code->code = ov772x_cfmts[code->index].code;
1348
1349 return 0;
1350}
1351
1352static const struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
1353 .s_stream = ov772x_s_stream,
1354 .s_frame_interval = ov772x_s_frame_interval,
1355 .g_frame_interval = ov772x_g_frame_interval,
1356};
1357
1358static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = {
1359 .enum_frame_interval = ov772x_enum_frame_interval,
1360 .enum_mbus_code = ov772x_enum_mbus_code,
1361 .get_selection = ov772x_get_selection,
1362 .get_fmt = ov772x_get_fmt,
1363 .set_fmt = ov772x_set_fmt,
1364};
1365
1366static const struct v4l2_subdev_ops ov772x_subdev_ops = {
1367 .core = &ov772x_subdev_core_ops,
1368 .video = &ov772x_subdev_video_ops,
1369 .pad = &ov772x_subdev_pad_ops,
1370};
1371
1372static int ov772x_parse_dt(struct i2c_client *client,
1373 struct ov772x_priv *priv)
1374{
1375 struct v4l2_fwnode_endpoint bus_cfg = {
1376 .bus_type = V4L2_MBUS_PARALLEL
1377 };
1378 struct fwnode_handle *ep;
1379 int ret;
1380
1381 ep = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev), NULL);
1382 if (!ep) {
1383 dev_err(&client->dev, "Endpoint node not found\n");
1384 return -EINVAL;
1385 }
1386
1387
1388
1389
1390
1391
1392
1393
1394 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1395 if (ret) {
1396 bus_cfg = (struct v4l2_fwnode_endpoint)
1397 { .bus_type = V4L2_MBUS_BT656 };
1398 ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1399 if (ret)
1400 goto error_fwnode_put;
1401 }
1402
1403 priv->bus_type = bus_cfg.bus_type;
1404 v4l2_fwnode_endpoint_free(&bus_cfg);
1405
1406error_fwnode_put:
1407 fwnode_handle_put(ep);
1408
1409 return ret;
1410}
1411
1412
1413
1414
1415
1416static int ov772x_probe(struct i2c_client *client)
1417{
1418 struct ov772x_priv *priv;
1419 int ret;
1420 static const struct regmap_config ov772x_regmap_config = {
1421 .reg_bits = 8,
1422 .val_bits = 8,
1423 .max_register = DSPAUTO,
1424 };
1425
1426 if (!client->dev.of_node && !client->dev.platform_data) {
1427 dev_err(&client->dev,
1428 "Missing ov772x platform data for non-DT device\n");
1429 return -EINVAL;
1430 }
1431
1432 priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
1433 if (!priv)
1434 return -ENOMEM;
1435
1436 priv->regmap = devm_regmap_init_sccb(client, &ov772x_regmap_config);
1437 if (IS_ERR(priv->regmap)) {
1438 dev_err(&client->dev, "Failed to allocate register map\n");
1439 return PTR_ERR(priv->regmap);
1440 }
1441
1442 priv->info = client->dev.platform_data;
1443 mutex_init(&priv->lock);
1444
1445 v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
1446 priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
1447 V4L2_SUBDEV_FL_HAS_EVENTS;
1448 v4l2_ctrl_handler_init(&priv->hdl, 3);
1449
1450 priv->hdl.lock = &priv->lock;
1451 priv->vflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1452 V4L2_CID_VFLIP, 0, 1, 1, 0);
1453 priv->hflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1454 V4L2_CID_HFLIP, 0, 1, 1, 0);
1455 priv->band_filter_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
1456 V4L2_CID_BAND_STOP_FILTER,
1457 0, 256, 1, 0);
1458 v4l2_ctrl_new_std_menu_items(&priv->hdl, &ov772x_ctrl_ops,
1459 V4L2_CID_TEST_PATTERN,
1460 ARRAY_SIZE(ov772x_test_pattern_menu) - 1,
1461 0, 0, ov772x_test_pattern_menu);
1462 priv->subdev.ctrl_handler = &priv->hdl;
1463 if (priv->hdl.error) {
1464 ret = priv->hdl.error;
1465 goto error_mutex_destroy;
1466 }
1467
1468 priv->clk = clk_get(&client->dev, NULL);
1469 if (IS_ERR(priv->clk)) {
1470 dev_err(&client->dev, "Unable to get xclk clock\n");
1471 ret = PTR_ERR(priv->clk);
1472 goto error_ctrl_free;
1473 }
1474
1475 priv->pwdn_gpio = gpiod_get_optional(&client->dev, "powerdown",
1476 GPIOD_OUT_LOW);
1477 if (IS_ERR(priv->pwdn_gpio)) {
1478 dev_info(&client->dev, "Unable to get GPIO \"powerdown\"");
1479 ret = PTR_ERR(priv->pwdn_gpio);
1480 goto error_clk_put;
1481 }
1482
1483 ret = ov772x_parse_dt(client, priv);
1484 if (ret)
1485 goto error_clk_put;
1486
1487 ret = ov772x_video_probe(priv);
1488 if (ret < 0)
1489 goto error_gpio_put;
1490
1491#ifdef CONFIG_MEDIA_CONTROLLER
1492 priv->pad.flags = MEDIA_PAD_FL_SOURCE;
1493 priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1494 ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
1495 if (ret < 0)
1496 goto error_gpio_put;
1497#endif
1498
1499 priv->cfmt = &ov772x_cfmts[0];
1500 priv->win = &ov772x_win_sizes[0];
1501 priv->fps = 15;
1502
1503 ret = v4l2_async_register_subdev(&priv->subdev);
1504 if (ret)
1505 goto error_entity_cleanup;
1506
1507 return 0;
1508
1509error_entity_cleanup:
1510 media_entity_cleanup(&priv->subdev.entity);
1511error_gpio_put:
1512 if (priv->pwdn_gpio)
1513 gpiod_put(priv->pwdn_gpio);
1514error_clk_put:
1515 clk_put(priv->clk);
1516error_ctrl_free:
1517 v4l2_ctrl_handler_free(&priv->hdl);
1518error_mutex_destroy:
1519 mutex_destroy(&priv->lock);
1520
1521 return ret;
1522}
1523
1524static int ov772x_remove(struct i2c_client *client)
1525{
1526 struct ov772x_priv *priv = to_ov772x(i2c_get_clientdata(client));
1527
1528 media_entity_cleanup(&priv->subdev.entity);
1529 clk_put(priv->clk);
1530 if (priv->pwdn_gpio)
1531 gpiod_put(priv->pwdn_gpio);
1532 v4l2_async_unregister_subdev(&priv->subdev);
1533 v4l2_ctrl_handler_free(&priv->hdl);
1534 mutex_destroy(&priv->lock);
1535
1536 return 0;
1537}
1538
1539static const struct i2c_device_id ov772x_id[] = {
1540 { "ov772x", 0 },
1541 { }
1542};
1543MODULE_DEVICE_TABLE(i2c, ov772x_id);
1544
1545static const struct of_device_id ov772x_of_match[] = {
1546 { .compatible = "ovti,ov7725", },
1547 { .compatible = "ovti,ov7720", },
1548 { },
1549};
1550MODULE_DEVICE_TABLE(of, ov772x_of_match);
1551
1552static struct i2c_driver ov772x_i2c_driver = {
1553 .driver = {
1554 .name = "ov772x",
1555 .of_match_table = ov772x_of_match,
1556 },
1557 .probe_new = ov772x_probe,
1558 .remove = ov772x_remove,
1559 .id_table = ov772x_id,
1560};
1561
1562module_i2c_driver(ov772x_i2c_driver);
1563
1564MODULE_DESCRIPTION("V4L2 driver for OV772x image sensor");
1565MODULE_AUTHOR("Kuninori Morimoto");
1566MODULE_LICENSE("GPL v2");
1567