LXR linux/drivers/media/pci/dt3155/dt3155.c

   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/***************************************************************************
   3 *   Copyright (C) 2006-2010 by Marin Mitov                                *
   4 *   mitov@issp.bas.bg                                                     *
   5 *                                                                         *
   6 *                                                                         *
   7 ***************************************************************************/
   8
   9#include <linux/module.h>
  10#include <linux/stringify.h>
  11#include <linux/delay.h>
  12#include <linux/kthread.h>
  13#include <linux/slab.h>
  14#include <media/v4l2-dev.h>
  15#include <media/v4l2-ioctl.h>
  16#include <media/v4l2-common.h>
  17#include <media/videobuf2-dma-contig.h>
  18
  19#include "dt3155.h"
  20
  21#define DT3155_DEVICE_ID 0x1223
  22
  23/**
  24 * read_i2c_reg - reads an internal i2c register
  25 *
  26 * @addr:       dt3155 mmio base address
  27 * @index:      index (internal address) of register to read
  28 * @data:       pointer to byte the read data will be placed in
  29 *
  30 * returns:     zero on success or error code
  31 *
  32 * This function starts reading the specified (by index) register
  33 * and busy waits for the process to finish. The result is placed
  34 * in a byte pointed by data.
  35 */
  36static int read_i2c_reg(void __iomem *addr, u8 index, u8 *data)
  37{
  38        u32 tmp = index;
  39
  40        iowrite32((tmp << 17) | IIC_READ, addr + IIC_CSR2);
  41        udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */
  42        if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
  43                return -EIO; /* error: NEW_CYCLE not cleared */
  44        tmp = ioread32(addr + IIC_CSR1);
  45        if (tmp & DIRECT_ABORT) {
  46                /* reset DIRECT_ABORT bit */
  47                iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
  48                return -EIO; /* error: DIRECT_ABORT set */
  49        }
  50        *data = tmp >> 24;
  51        return 0;
  52}
  53
  54/**
  55 * write_i2c_reg - writes to an internal i2c register
  56 *
  57 * @addr:       dt3155 mmio base address
  58 * @index:      index (internal address) of register to read
  59 * @data:       data to be written
  60 *
  61 * returns:     zero on success or error code
  62 *
  63 * This function starts writing the specified (by index) register
  64 * and busy waits for the process to finish.
  65 */
  66static int write_i2c_reg(void __iomem *addr, u8 index, u8 data)
  67{
  68        u32 tmp = index;
  69
  70        iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
  71        udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
  72        if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
  73                return -EIO; /* error: NEW_CYCLE not cleared */
  74        if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
  75                /* reset DIRECT_ABORT bit */
  76                iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
  77                return -EIO; /* error: DIRECT_ABORT set */
  78        }
  79        return 0;
  80}
  81
  82/**
  83 * write_i2c_reg_nowait - writes to an internal i2c register
  84 *
  85 * @addr:       dt3155 mmio base address
  86 * @index:      index (internal address) of register to read
  87 * @data:       data to be written
  88 *
  89 * This function starts writing the specified (by index) register
  90 * and then returns.
  91 */
  92static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data)
  93{
  94        u32 tmp = index;
  95
  96        iowrite32((tmp << 17) | IIC_WRITE | data, addr + IIC_CSR2);
  97}
  98
  99/**
 100 * wait_i2c_reg - waits the read/write to finish
 101 *
 102 * @addr:       dt3155 mmio base address
 103 *
 104 * returns:     zero on success or error code
 105 *
 106 * This function waits reading/writing to finish.
 107 */
 108static int wait_i2c_reg(void __iomem *addr)
 109{
 110        if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 111                udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */
 112        if (ioread32(addr + IIC_CSR2) & NEW_CYCLE)
 113                return -EIO; /* error: NEW_CYCLE not cleared */
 114        if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) {
 115                /* reset DIRECT_ABORT bit */
 116                iowrite32(DIRECT_ABORT, addr + IIC_CSR1);
 117                return -EIO; /* error: DIRECT_ABORT set */
 118        }
 119        return 0;
 120}
 121
 122static int
 123dt3155_queue_setup(struct vb2_queue *vq,
 124                unsigned int *nbuffers, unsigned int *num_planes,
 125                unsigned int sizes[], struct device *alloc_devs[])
 126
 127{
 128        struct dt3155_priv *pd = vb2_get_drv_priv(vq);
 129        unsigned size = pd->width * pd->height;
 130
 131        if (vq->num_buffers + *nbuffers < 2)
 132                *nbuffers = 2 - vq->num_buffers;
 133        if (*num_planes)
 134                return sizes[0] < size ? -EINVAL : 0;
 135        *num_planes = 1;
 136        sizes[0] = size;
 137        return 0;
 138}
 139
 140static int dt3155_buf_prepare(struct vb2_buffer *vb)
 141{
 142        struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
 143
 144        vb2_set_plane_payload(vb, 0, pd->width * pd->height);
 145        return 0;
 146}
 147
 148static int dt3155_start_streaming(struct vb2_queue *q, unsigned count)
 149{
 150        struct dt3155_priv *pd = vb2_get_drv_priv(q);
 151        struct vb2_buffer *vb = &pd->curr_buf->vb2_buf;
 152        dma_addr_t dma_addr;
 153
 154        pd->sequence = 0;
 155        dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
 156        iowrite32(dma_addr, pd->regs + EVEN_DMA_START);
 157        iowrite32(dma_addr + pd->width, pd->regs + ODD_DMA_START);
 158        iowrite32(pd->width, pd->regs + EVEN_DMA_STRIDE);
 159        iowrite32(pd->width, pd->regs + ODD_DMA_STRIDE);
 160        /* enable interrupts, clear all irq flags */
 161        iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
 162                        FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
 163        iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
 164                  FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD,
 165                                                        pd->regs + CSR1);
 166        wait_i2c_reg(pd->regs);
 167        write_i2c_reg(pd->regs, CONFIG, pd->config);
 168        write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE);
 169        write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE);
 170
 171        /*  start the board  */
 172        write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD);
 173        return 0;
 174}
 175
 176static void dt3155_stop_streaming(struct vb2_queue *q)
 177{
 178        struct dt3155_priv *pd = vb2_get_drv_priv(q);
 179        struct vb2_buffer *vb;
 180
 181        spin_lock_irq(&pd->lock);
 182        /* stop the board */
 183        write_i2c_reg_nowait(pd->regs, CSR2, pd->csr2);
 184        iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
 185                  FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
 186        /* disable interrupts, clear all irq flags */
 187        iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR);
 188        spin_unlock_irq(&pd->lock);
 189
 190        /*
 191         * It is not clear whether the DMA stops at once or whether it
 192         * will finish the current frame or field first. To be on the
 193         * safe side we wait a bit.
 194         */
 195        msleep(45);
 196
 197        spin_lock_irq(&pd->lock);
 198        if (pd->curr_buf) {
 199                vb2_buffer_done(&pd->curr_buf->vb2_buf, VB2_BUF_STATE_ERROR);
 200                pd->curr_buf = NULL;
 201        }
 202
 203        while (!list_empty(&pd->dmaq)) {
 204                vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry);
 205                list_del(&vb->done_entry);
 206                vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
 207        }
 208        spin_unlock_irq(&pd->lock);
 209}
 210
 211static void dt3155_buf_queue(struct vb2_buffer *vb)
 212{
 213        struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
 214        struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue);
 215
 216        /*  pd->vidq.streaming = 1 when dt3155_buf_queue() is invoked  */
 217        spin_lock_irq(&pd->lock);
 218        if (pd->curr_buf)
 219                list_add_tail(&vb->done_entry, &pd->dmaq);
 220        else
 221                pd->curr_buf = vbuf;
 222        spin_unlock_irq(&pd->lock);
 223}
 224
 225static const struct vb2_ops q_ops = {
 226        .queue_setup = dt3155_queue_setup,
 227        .wait_prepare = vb2_ops_wait_prepare,
 228        .wait_finish = vb2_ops_wait_finish,
 229        .buf_prepare = dt3155_buf_prepare,
 230        .start_streaming = dt3155_start_streaming,
 231        .stop_streaming = dt3155_stop_streaming,
 232        .buf_queue = dt3155_buf_queue,
 233};
 234
 235static irqreturn_t dt3155_irq_handler_even(int irq, void *dev_id)
 236{
 237        struct dt3155_priv *ipd = dev_id;
 238        struct vb2_buffer *ivb;
 239        dma_addr_t dma_addr;
 240        u32 tmp;
 241
 242        tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD);
 243        if (!tmp)
 244                return IRQ_NONE;  /* not our irq */
 245        if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) {
 246                iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START,
 247                                                        ipd->regs + INT_CSR);
 248                return IRQ_HANDLED; /* start of field irq */
 249        }
 250        tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD);
 251        if (tmp) {
 252                iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN |
 253                                                FLD_DN_ODD | FLD_DN_EVEN |
 254                                                CAP_CONT_EVEN | CAP_CONT_ODD,
 255                                                        ipd->regs + CSR1);
 256        }
 257
 258        spin_lock(&ipd->lock);
 259        if (ipd->curr_buf && !list_empty(&ipd->dmaq)) {
 260                ipd->curr_buf->vb2_buf.timestamp = ktime_get_ns();
 261                ipd->curr_buf->sequence = ipd->sequence++;
 262                ipd->curr_buf->field = V4L2_FIELD_NONE;
 263                vb2_buffer_done(&ipd->curr_buf->vb2_buf, VB2_BUF_STATE_DONE);
 264
 265                ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry);
 266                list_del(&ivb->done_entry);
 267                ipd->curr_buf = to_vb2_v4l2_buffer(ivb);
 268                dma_addr = vb2_dma_contig_plane_dma_addr(ivb, 0);
 269                iowrite32(dma_addr, ipd->regs + EVEN_DMA_START);
 270                iowrite32(dma_addr + ipd->width, ipd->regs + ODD_DMA_START);
 271                iowrite32(ipd->width, ipd->regs + EVEN_DMA_STRIDE);
 272                iowrite32(ipd->width, ipd->regs + ODD_DMA_STRIDE);
 273        }
 274
 275        /* enable interrupts, clear all irq flags */
 276        iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START |
 277                        FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR);
 278        spin_unlock(&ipd->lock);
 279        return IRQ_HANDLED;
 280}
 281
 282static const struct v4l2_file_operations dt3155_fops = {
 283        .owner = THIS_MODULE,
 284        .open = v4l2_fh_open,
 285        .release = vb2_fop_release,
 286        .unlocked_ioctl = video_ioctl2,
 287        .read = vb2_fop_read,
 288        .mmap = vb2_fop_mmap,
 289        .poll = vb2_fop_poll
 290};
 291
 292static int dt3155_querycap(struct file *filp, void *p,
 293                           struct v4l2_capability *cap)
 294{
 295        struct dt3155_priv *pd = video_drvdata(filp);
 296
 297        strscpy(cap->driver, DT3155_NAME, sizeof(cap->driver));
 298        strscpy(cap->card, DT3155_NAME " frame grabber", sizeof(cap->card));
 299        sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev));
 300        return 0;
 301}
 302
 303static int dt3155_enum_fmt_vid_cap(struct file *filp,
 304                                   void *p, struct v4l2_fmtdesc *f)
 305{
 306        if (f->index)
 307                return -EINVAL;
 308        f->pixelformat = V4L2_PIX_FMT_GREY;
 309        return 0;
 310}
 311
 312static int dt3155_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f)
 313{
 314        struct dt3155_priv *pd = video_drvdata(filp);
 315
 316        f->fmt.pix.width = pd->width;
 317        f->fmt.pix.height = pd->height;
 318        f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY;
 319        f->fmt.pix.field = V4L2_FIELD_NONE;
 320        f->fmt.pix.bytesperline = f->fmt.pix.width;
 321        f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height;
 322        f->fmt.pix.colorspace = V4L2_COLORSPACE_SMPTE170M;
 323        return 0;
 324}
 325
 326static int dt3155_g_std(struct file *filp, void *p, v4l2_std_id *norm)
 327{
 328        struct dt3155_priv *pd = video_drvdata(filp);
 329
 330        *norm = pd->std;
 331        return 0;
 332}
 333
 334static int dt3155_s_std(struct file *filp, void *p, v4l2_std_id norm)
 335{
 336        struct dt3155_priv *pd = video_drvdata(filp);
 337
 338        if (pd->std == norm)
 339                return 0;
 340        if (vb2_is_busy(&pd->vidq))
 341                return -EBUSY;
 342        pd->std = norm;
 343        if (pd->std & V4L2_STD_525_60) {
 344                pd->csr2 = VT_60HZ;
 345                pd->width = 640;
 346                pd->height = 480;
 347        } else {
 348                pd->csr2 = VT_50HZ;
 349                pd->width = 768;
 350                pd->height = 576;
 351        }
 352        return 0;
 353}
 354
 355static int dt3155_enum_input(struct file *filp, void *p,
 356                             struct v4l2_input *input)
 357{
 358        if (input->index > 3)
 359                return -EINVAL;
 360        if (input->index)
 361                snprintf(input->name, sizeof(input->name), "VID%d",
 362                         input->index);
 363        else
 364                strscpy(input->name, "J2/VID0", sizeof(input->name));
 365        input->type = V4L2_INPUT_TYPE_CAMERA;
 366        input->std = V4L2_STD_ALL;
 367        input->status = 0;
 368        return 0;
 369}
 370
 371static int dt3155_g_input(struct file *filp, void *p, unsigned int *i)
 372{
 373        struct dt3155_priv *pd = video_drvdata(filp);
 374
 375        *i = pd->input;
 376        return 0;
 377}
 378
 379static int dt3155_s_input(struct file *filp, void *p, unsigned int i)
 380{
 381        struct dt3155_priv *pd = video_drvdata(filp);
 382
 383        if (i > 3)
 384                return -EINVAL;
 385        pd->input = i;
 386        write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
 387        write_i2c_reg(pd->regs, AD_CMD, (i << 6) | (i << 4) | SYNC_LVL_3);
 388        return 0;
 389}
 390
 391static const struct v4l2_ioctl_ops dt3155_ioctl_ops = {
 392        .vidioc_querycap = dt3155_querycap,
 393        .vidioc_enum_fmt_vid_cap = dt3155_enum_fmt_vid_cap,
 394        .vidioc_try_fmt_vid_cap = dt3155_fmt_vid_cap,
 395        .vidioc_g_fmt_vid_cap = dt3155_fmt_vid_cap,
 396        .vidioc_s_fmt_vid_cap = dt3155_fmt_vid_cap,
 397        .vidioc_reqbufs = vb2_ioctl_reqbufs,
 398        .vidioc_create_bufs = vb2_ioctl_create_bufs,
 399        .vidioc_querybuf = vb2_ioctl_querybuf,
 400        .vidioc_expbuf = vb2_ioctl_expbuf,
 401        .vidioc_qbuf = vb2_ioctl_qbuf,
 402        .vidioc_dqbuf = vb2_ioctl_dqbuf,
 403        .vidioc_streamon = vb2_ioctl_streamon,
 404        .vidioc_streamoff = vb2_ioctl_streamoff,
 405        .vidioc_g_std = dt3155_g_std,
 406        .vidioc_s_std = dt3155_s_std,
 407        .vidioc_enum_input = dt3155_enum_input,
 408        .vidioc_g_input = dt3155_g_input,
 409        .vidioc_s_input = dt3155_s_input,
 410};
 411
 412static int dt3155_init_board(struct dt3155_priv *pd)
 413{
 414        struct pci_dev *pdev = pd->pdev;
 415        int i;
 416        u8 tmp = 0;
 417
 418        pci_set_master(pdev); /* dt3155 needs it */
 419
 420        /*  resetting the adapter  */
 421        iowrite32(ADDR_ERR_ODD | ADDR_ERR_EVEN | FLD_CRPT_ODD | FLD_CRPT_EVEN |
 422                        FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1);
 423        msleep(20);
 424
 425        /*  initializing adapter registers  */
 426        iowrite32(FIFO_EN | SRST, pd->regs + CSR1);
 427        iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT);
 428        iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT);
 429        iowrite32(0x00000020, pd->regs + FIFO_TRIGGER);
 430        iowrite32(0x00000103, pd->regs + XFER_MODE);
 431        iowrite32(0, pd->regs + RETRY_WAIT_CNT);
 432        iowrite32(0, pd->regs + INT_CSR);
 433        iowrite32(1, pd->regs + EVEN_FLD_MASK);
 434        iowrite32(1, pd->regs + ODD_FLD_MASK);
 435        iowrite32(0, pd->regs + MASK_LENGTH);
 436        iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT);
 437        iowrite32(0x01010101, pd->regs + IIC_CLK_DUR);
 438
 439        /* verifying that we have a DT3155 board (not just a SAA7116 chip) */
 440        read_i2c_reg(pd->regs, DT_ID, &tmp);
 441        if (tmp != DT3155_ID)
 442                return -ENODEV;
 443
 444        /* initialize AD LUT */
 445        write_i2c_reg(pd->regs, AD_ADDR, 0);
 446        for (i = 0; i < 256; i++)
 447                write_i2c_reg(pd->regs, AD_LUT, i);
 448
 449        /* initialize ADC references */
 450        /* FIXME: pos_ref & neg_ref depend on VT_50HZ */
 451        write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
 452        write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
 453        write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF);
 454        write_i2c_reg(pd->regs, AD_CMD, 34);
 455        write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF);
 456        write_i2c_reg(pd->regs, AD_CMD, 0);
 457
 458        /* initialize PM LUT */
 459        write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM);
 460        for (i = 0; i < 256; i++) {
 461                write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
 462                write_i2c_reg(pd->regs, PM_LUT_DATA, i);
 463        }
 464        write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL);
 465        for (i = 0; i < 256; i++) {
 466                write_i2c_reg(pd->regs, PM_LUT_ADDR, i);
 467                write_i2c_reg(pd->regs, PM_LUT_DATA, i);
 468        }
 469        write_i2c_reg(pd->regs, CONFIG, pd->config); /*  ACQ_MODE_EVEN  */
 470
 471        /* select channel 1 for input and set sync level */
 472        write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG);
 473        write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3);
 474
 475        /* disable all irqs, clear all irq flags */
 476        iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD,
 477                        pd->regs + INT_CSR);
 478
 479        return 0;
 480}
 481
 482static const struct video_device dt3155_vdev = {
 483        .name = DT3155_NAME,
 484        .fops = &dt3155_fops,
 485        .ioctl_ops = &dt3155_ioctl_ops,
 486        .minor = -1,
 487        .release = video_device_release_empty,
 488        .tvnorms = V4L2_STD_ALL,
 489        .device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING |
 490                       V4L2_CAP_READWRITE,
 491};
 492
 493static int dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 494{
 495        int err;
 496        struct dt3155_priv *pd;
 497
 498        err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
 499        if (err)
 500                return -ENODEV;
 501        pd = devm_kzalloc(&pdev->dev, sizeof(*pd), GFP_KERNEL);
 502        if (!pd)
 503                return -ENOMEM;
 504
 505        err = v4l2_device_register(&pdev->dev, &pd->v4l2_dev);
 506        if (err)
 507                return err;
 508        pd->vdev = dt3155_vdev;
 509        pd->vdev.v4l2_dev = &pd->v4l2_dev;
 510        video_set_drvdata(&pd->vdev, pd);  /* for use in video_fops */
 511        pd->pdev = pdev;
 512        pd->std = V4L2_STD_625_50;
 513        pd->csr2 = VT_50HZ;
 514        pd->width = 768;
 515        pd->height = 576;
 516        INIT_LIST_HEAD(&pd->dmaq);
 517        mutex_init(&pd->mux);
 518        pd->vdev.lock = &pd->mux; /* for locking v4l2_file_operations */
 519        pd->vidq.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
 520        pd->vidq.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
 521        pd->vidq.io_modes = VB2_MMAP | VB2_DMABUF | VB2_READ;
 522        pd->vidq.ops = &q_ops;
 523        pd->vidq.mem_ops = &vb2_dma_contig_memops;
 524        pd->vidq.drv_priv = pd;
 525        pd->vidq.min_buffers_needed = 2;
 526        pd->vidq.gfp_flags = GFP_DMA32;
 527        pd->vidq.lock = &pd->mux; /* for locking v4l2_file_operations */
 528        pd->vidq.dev = &pdev->dev;
 529        pd->vdev.queue = &pd->vidq;
 530        err = vb2_queue_init(&pd->vidq);
 531        if (err < 0)
 532                goto err_v4l2_dev_unreg;
 533        spin_lock_init(&pd->lock);
 534        pd->config = ACQ_MODE_EVEN;
 535        err = pci_enable_device(pdev);
 536        if (err)
 537                goto err_v4l2_dev_unreg;
 538        err = pci_request_region(pdev, 0, pci_name(pdev));
 539        if (err)
 540                goto err_pci_disable;
 541        pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0));
 542        if (!pd->regs) {
 543                err = -ENOMEM;
 544                goto err_free_reg;
 545        }
 546        err = dt3155_init_board(pd);
 547        if (err)
 548                goto err_iounmap;
 549        err = request_irq(pd->pdev->irq, dt3155_irq_handler_even,
 550                                        IRQF_SHARED, DT3155_NAME, pd);
 551        if (err)
 552                goto err_iounmap;
 553        err = video_register_device(&pd->vdev, VFL_TYPE_VIDEO, -1);
 554        if (err)
 555                goto err_free_irq;
 556        dev_info(&pdev->dev, "/dev/video%i is ready\n", pd->vdev.minor);
 557        return 0;  /*   success   */
 558
 559err_free_irq:
 560        free_irq(pd->pdev->irq, pd);
 561err_iounmap:
 562        pci_iounmap(pdev, pd->regs);
 563err_free_reg:
 564        pci_release_region(pdev, 0);
 565err_pci_disable:
 566        pci_disable_device(pdev);
 567err_v4l2_dev_unreg:
 568        v4l2_device_unregister(&pd->v4l2_dev);
 569        return err;
 570}
 571
 572static void dt3155_remove(struct pci_dev *pdev)
 573{
 574        struct v4l2_device *v4l2_dev = pci_get_drvdata(pdev);
 575        struct dt3155_priv *pd = container_of(v4l2_dev, struct dt3155_priv,
 576                                              v4l2_dev);
 577
 578        vb2_video_unregister_device(&pd->vdev);
 579        free_irq(pd->pdev->irq, pd);
 580        v4l2_device_unregister(&pd->v4l2_dev);
 581        pci_iounmap(pdev, pd->regs);
 582        pci_release_region(pdev, 0);
 583        pci_disable_device(pdev);
 584}
 585
 586static const struct pci_device_id pci_ids[] = {
 587        { PCI_DEVICE(PCI_VENDOR_ID_INTEL, DT3155_DEVICE_ID) },
 588        { 0, /* zero marks the end */ },
 589};
 590MODULE_DEVICE_TABLE(pci, pci_ids);
 591
 592static struct pci_driver pci_driver = {
 593        .name = DT3155_NAME,
 594        .id_table = pci_ids,
 595        .probe = dt3155_probe,
 596        .remove = dt3155_remove,
 597};
 598
 599module_pci_driver(pci_driver);
 600
 601MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber");
 602MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>");
 603MODULE_VERSION(DT3155_VERSION);
 604MODULE_LICENSE("GPL");
 605