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10#include <linux/clk.h>
11#include <linux/completion.h>
12#include <linux/interrupt.h>
13#include <linux/io.h>
14#include <linux/iopoll.h>
15#include <linux/kernel.h>
16#include <linux/mutex.h>
17#include <linux/platform_device.h>
18#include <linux/pm_runtime.h>
19#include <media/media-entity.h>
20#include <media/v4l2-device.h>
21#include <media/v4l2-subdev.h>
22
23#include "camss-ispif.h"
24#include "camss.h"
25
26#define MSM_ISPIF_NAME "msm_ispif"
27
28#define ISPIF_RST_CMD_0 0x008
29#define ISPIF_RST_CMD_1 0x00c
30#define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
31#define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
32#define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
33#define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)
34#define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)
35#define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)
36#define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)
37#define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)
38#define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)
39#define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)
40#define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)
41#define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)
42#define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)
43#define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)
44#define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)
45#define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)
46#define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)
47#define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
48#define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
49#define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
50#define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
51#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249
52#define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff
53#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000
54#define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000
55#define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
56#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249
57#define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff
58#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000
59#define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000
60#define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
61#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249
62#define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff
63#define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
64#define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)
65#define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)
66#define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
67#define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)
68#define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)
69#define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
70#define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)
71#define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
72#define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
73#define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
74#define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
75#define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
76#define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
77#define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \
78 (0x254 + 0x200 * (m) + 0x4 * (n))
79#define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \
80 (0x264 + 0x200 * (m) + 0x4 * (n))
81
82#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \
83 (0x270 + 0x200 * (m) + 0x4 * (n))
84#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \
85 (0x27c + 0x200 * (m) + 0x4 * (n))
86#define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \
87 (1 << ((cid % 8) * 4))
88#define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \
89 (0x2c0 + 0x200 * (m) + 0x4 * (n))
90#define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \
91 (0x2d0 + 0x200 * (m) + 0x4 * (n))
92
93#define CSI_PIX_CLK_MUX_SEL 0x000
94#define CSI_RDI_CLK_MUX_SEL 0x008
95
96#define ISPIF_TIMEOUT_SLEEP_US 1000
97#define ISPIF_TIMEOUT_ALL_US 1000000
98#define ISPIF_RESET_TIMEOUT_MS 500
99
100enum ispif_intf_cmd {
101 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
102 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
103 CMD_DISABLE_IMMEDIATELY = 0x2,
104 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
105 CMD_ALL_NO_CHANGE = 0xffffffff,
106};
107
108static const u32 ispif_formats_8x16[] = {
109 MEDIA_BUS_FMT_UYVY8_2X8,
110 MEDIA_BUS_FMT_VYUY8_2X8,
111 MEDIA_BUS_FMT_YUYV8_2X8,
112 MEDIA_BUS_FMT_YVYU8_2X8,
113 MEDIA_BUS_FMT_SBGGR8_1X8,
114 MEDIA_BUS_FMT_SGBRG8_1X8,
115 MEDIA_BUS_FMT_SGRBG8_1X8,
116 MEDIA_BUS_FMT_SRGGB8_1X8,
117 MEDIA_BUS_FMT_SBGGR10_1X10,
118 MEDIA_BUS_FMT_SGBRG10_1X10,
119 MEDIA_BUS_FMT_SGRBG10_1X10,
120 MEDIA_BUS_FMT_SRGGB10_1X10,
121 MEDIA_BUS_FMT_SBGGR12_1X12,
122 MEDIA_BUS_FMT_SGBRG12_1X12,
123 MEDIA_BUS_FMT_SGRBG12_1X12,
124 MEDIA_BUS_FMT_SRGGB12_1X12,
125 MEDIA_BUS_FMT_Y10_1X10,
126};
127
128static const u32 ispif_formats_8x96[] = {
129 MEDIA_BUS_FMT_UYVY8_2X8,
130 MEDIA_BUS_FMT_VYUY8_2X8,
131 MEDIA_BUS_FMT_YUYV8_2X8,
132 MEDIA_BUS_FMT_YVYU8_2X8,
133 MEDIA_BUS_FMT_SBGGR8_1X8,
134 MEDIA_BUS_FMT_SGBRG8_1X8,
135 MEDIA_BUS_FMT_SGRBG8_1X8,
136 MEDIA_BUS_FMT_SRGGB8_1X8,
137 MEDIA_BUS_FMT_SBGGR10_1X10,
138 MEDIA_BUS_FMT_SGBRG10_1X10,
139 MEDIA_BUS_FMT_SGRBG10_1X10,
140 MEDIA_BUS_FMT_SRGGB10_1X10,
141 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
142 MEDIA_BUS_FMT_SBGGR12_1X12,
143 MEDIA_BUS_FMT_SGBRG12_1X12,
144 MEDIA_BUS_FMT_SGRBG12_1X12,
145 MEDIA_BUS_FMT_SRGGB12_1X12,
146 MEDIA_BUS_FMT_SBGGR14_1X14,
147 MEDIA_BUS_FMT_SGBRG14_1X14,
148 MEDIA_BUS_FMT_SGRBG14_1X14,
149 MEDIA_BUS_FMT_SRGGB14_1X14,
150 MEDIA_BUS_FMT_Y10_1X10,
151 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
152};
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159
160
161static irqreturn_t ispif_isr_8x96(int irq, void *dev)
162{
163 struct ispif_device *ispif = dev;
164 struct camss *camss = ispif->camss;
165 u32 value0, value1, value2, value3, value4, value5;
166
167 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
168 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
169 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
170 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
171 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
172 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
173
174 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
175 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
176 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
177 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
178 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
179 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
180
181 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
182
183 if ((value0 >> 27) & 0x1)
184 complete(&ispif->reset_complete[0]);
185
186 if ((value3 >> 27) & 0x1)
187 complete(&ispif->reset_complete[1]);
188
189 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
190 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
191
192 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
193 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
194
195 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
196 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
197
198 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
199 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
200
201 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
202 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
203
204 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
205 dev_err_ratelimited(camss->dev, "VFE1 pix0 overflow\n");
206
207 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
208 dev_err_ratelimited(camss->dev, "VFE1 rdi0 overflow\n");
209
210 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
211 dev_err_ratelimited(camss->dev, "VFE1 pix1 overflow\n");
212
213 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
214 dev_err_ratelimited(camss->dev, "VFE1 rdi1 overflow\n");
215
216 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
217 dev_err_ratelimited(camss->dev, "VFE1 rdi2 overflow\n");
218
219 return IRQ_HANDLED;
220}
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227
228
229static irqreturn_t ispif_isr_8x16(int irq, void *dev)
230{
231 struct ispif_device *ispif = dev;
232 struct camss *camss = ispif->camss;
233 u32 value0, value1, value2;
234
235 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
236 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
237 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
238
239 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
240 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
241 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
242
243 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
244
245 if ((value0 >> 27) & 0x1)
246 complete(&ispif->reset_complete[0]);
247
248 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
249 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
250
251 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
252 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
253
254 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
255 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
256
257 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
258 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
259
260 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
261 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
262
263 return IRQ_HANDLED;
264}
265
266static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)
267{
268 struct camss *camss = ispif->camss;
269
270 unsigned long time;
271 u32 val;
272
273 if (vfe_id > (camss->vfe_num - 1)) {
274 dev_err(camss->dev,
275 "Error: asked reset for invalid VFE%d\n", vfe_id);
276 return -ENOENT;
277 }
278
279 reinit_completion(&ispif->reset_complete[vfe_id]);
280
281 val = ISPIF_RST_CMD_0_STROBED_RST_EN |
282 ISPIF_RST_CMD_0_MISC_LOGIC_RST |
283 ISPIF_RST_CMD_0_SW_REG_RST |
284 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
285 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
286 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
287 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
288 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
289 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
290 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
291 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
292 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
293 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
294 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
295 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
296 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
297 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
298
299 if (vfe_id == 1)
300 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);
301 else
302 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
303
304 time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id],
305 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
306 if (!time) {
307 dev_err(camss->dev,
308 "ISPIF for VFE%d reset timeout\n", vfe_id);
309 return -EIO;
310 }
311
312 return 0;
313}
314
315
316
317
318
319
320
321static int ispif_reset(struct ispif_device *ispif, u8 vfe_id)
322{
323 struct camss *camss = ispif->camss;
324 int ret;
325
326 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE0);
327 if (ret < 0)
328 return ret;
329
330 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE1);
331 if (ret < 0)
332 return ret;
333
334 ret = camss_enable_clocks(ispif->nclocks_for_reset,
335 ispif->clock_for_reset,
336 camss->dev);
337 if (ret < 0)
338 return ret;
339
340 ret = ispif_vfe_reset(ispif, vfe_id);
341 if (ret)
342 dev_dbg(camss->dev, "ISPIF Reset failed\n");
343
344 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
345
346 camss_pm_domain_off(camss, PM_DOMAIN_VFE0);
347 camss_pm_domain_off(camss, PM_DOMAIN_VFE1);
348
349 return ret;
350}
351
352
353
354
355
356
357
358
359static int ispif_set_power(struct v4l2_subdev *sd, int on)
360{
361 struct ispif_line *line = v4l2_get_subdevdata(sd);
362 struct ispif_device *ispif = line->ispif;
363 struct device *dev = ispif->camss->dev;
364 int ret = 0;
365
366 mutex_lock(&ispif->power_lock);
367
368 if (on) {
369 if (ispif->power_count) {
370
371 ispif->power_count++;
372 goto exit;
373 }
374
375 ret = pm_runtime_resume_and_get(dev);
376 if (ret < 0)
377 goto exit;
378
379 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
380 if (ret < 0) {
381 pm_runtime_put_sync(dev);
382 goto exit;
383 }
384
385 ret = ispif_reset(ispif, line->vfe_id);
386 if (ret < 0) {
387 pm_runtime_put_sync(dev);
388 camss_disable_clocks(ispif->nclocks, ispif->clock);
389 goto exit;
390 }
391
392 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
393 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
394
395 ispif->power_count++;
396 } else {
397 if (ispif->power_count == 0) {
398 dev_err(dev, "ispif power off on power_count == 0\n");
399 goto exit;
400 } else if (ispif->power_count == 1) {
401 camss_disable_clocks(ispif->nclocks, ispif->clock);
402 pm_runtime_put_sync(dev);
403 }
404
405 ispif->power_count--;
406 }
407
408exit:
409 mutex_unlock(&ispif->power_lock);
410
411 return ret;
412}
413
414
415
416
417
418
419
420
421
422static void ispif_select_clk_mux(struct ispif_device *ispif,
423 enum ispif_intf intf, u8 csid,
424 u8 vfe, u8 enable)
425{
426 u32 val;
427
428 switch (intf) {
429 case PIX0:
430 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
431 val &= ~(0xf << (vfe * 8));
432 if (enable)
433 val |= (csid << (vfe * 8));
434 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
435 break;
436
437 case RDI0:
438 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
439 val &= ~(0xf << (vfe * 12));
440 if (enable)
441 val |= (csid << (vfe * 12));
442 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
443 break;
444
445 case PIX1:
446 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
447 val &= ~(0xf << (4 + (vfe * 8)));
448 if (enable)
449 val |= (csid << (4 + (vfe * 8)));
450 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
451 break;
452
453 case RDI1:
454 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
455 val &= ~(0xf << (4 + (vfe * 12)));
456 if (enable)
457 val |= (csid << (4 + (vfe * 12)));
458 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
459 break;
460
461 case RDI2:
462 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
463 val &= ~(0xf << (8 + (vfe * 12)));
464 if (enable)
465 val |= (csid << (8 + (vfe * 12)));
466 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
467 break;
468 }
469
470 mb();
471}
472
473
474
475
476
477
478
479
480
481static int ispif_validate_intf_status(struct ispif_device *ispif,
482 enum ispif_intf intf, u8 vfe)
483{
484 int ret = 0;
485 u32 val = 0;
486
487 switch (intf) {
488 case PIX0:
489 val = readl_relaxed(ispif->base +
490 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
491 break;
492 case RDI0:
493 val = readl_relaxed(ispif->base +
494 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
495 break;
496 case PIX1:
497 val = readl_relaxed(ispif->base +
498 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
499 break;
500 case RDI1:
501 val = readl_relaxed(ispif->base +
502 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
503 break;
504 case RDI2:
505 val = readl_relaxed(ispif->base +
506 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
507 break;
508 }
509
510 if ((val & 0xf) != 0xf) {
511 dev_err(ispif->camss->dev, "%s: ispif is busy: 0x%x\n",
512 __func__, val);
513 ret = -EBUSY;
514 }
515
516 return ret;
517}
518
519
520
521
522
523
524
525
526
527static int ispif_wait_for_stop(struct ispif_device *ispif,
528 enum ispif_intf intf, u8 vfe)
529{
530 u32 addr = 0;
531 u32 stop_flag = 0;
532 int ret;
533
534 switch (intf) {
535 case PIX0:
536 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
537 break;
538 case RDI0:
539 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
540 break;
541 case PIX1:
542 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
543 break;
544 case RDI1:
545 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
546 break;
547 case RDI2:
548 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
549 break;
550 }
551
552 ret = readl_poll_timeout(ispif->base + addr,
553 stop_flag,
554 (stop_flag & 0xf) == 0xf,
555 ISPIF_TIMEOUT_SLEEP_US,
556 ISPIF_TIMEOUT_ALL_US);
557 if (ret < 0)
558 dev_err(ispif->camss->dev, "%s: ispif stop timeout\n",
559 __func__);
560
561 return ret;
562}
563
564
565
566
567
568
569
570
571
572static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
573 u8 csid, u8 vfe, u8 enable)
574{
575 u32 val;
576
577 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
578 switch (intf) {
579 case PIX0:
580 val &= ~(BIT(1) | BIT(0));
581 if (enable)
582 val |= csid;
583 break;
584 case RDI0:
585 val &= ~(BIT(5) | BIT(4));
586 if (enable)
587 val |= (csid << 4);
588 break;
589 case PIX1:
590 val &= ~(BIT(9) | BIT(8));
591 if (enable)
592 val |= (csid << 8);
593 break;
594 case RDI1:
595 val &= ~(BIT(13) | BIT(12));
596 if (enable)
597 val |= (csid << 12);
598 break;
599 case RDI2:
600 val &= ~(BIT(21) | BIT(20));
601 if (enable)
602 val |= (csid << 20);
603 break;
604 }
605
606 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
607}
608
609
610
611
612
613
614
615
616
617static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
618 u8 cid, u8 vfe, u8 enable)
619{
620 u32 cid_mask = 1 << cid;
621 u32 addr = 0;
622 u32 val;
623
624 switch (intf) {
625 case PIX0:
626 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
627 break;
628 case RDI0:
629 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
630 break;
631 case PIX1:
632 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
633 break;
634 case RDI1:
635 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
636 break;
637 case RDI2:
638 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
639 break;
640 }
641
642 val = readl_relaxed(ispif->base + addr);
643 if (enable)
644 val |= cid_mask;
645 else
646 val &= ~cid_mask;
647
648 writel(val, ispif->base + addr);
649}
650
651
652
653
654
655
656
657
658static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
659 u8 vfe, u8 enable)
660{
661 u32 val;
662
663 switch (intf) {
664 case PIX0:
665 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
666 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
667 if (enable)
668 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
669 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
670 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
671 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
672 break;
673 case RDI0:
674 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
675 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
676 if (enable)
677 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
678 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
679 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
680 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
681 break;
682 case PIX1:
683 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
684 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
685 if (enable)
686 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
687 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
688 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
689 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
690 break;
691 case RDI1:
692 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
693 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
694 if (enable)
695 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
696 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
697 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
698 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
699 break;
700 case RDI2:
701 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
702 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
703 if (enable)
704 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
705 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
706 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
707 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
708 break;
709 }
710
711 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
712}
713
714
715
716
717
718
719
720
721
722
723static void ispif_config_pack(struct ispif_device *ispif, u32 code,
724 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
725{
726 u32 addr, val;
727
728 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
729 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
730 return;
731
732 switch (intf) {
733 case RDI0:
734 if (cid < 8)
735 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
736 else
737 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
738 break;
739 case RDI1:
740 if (cid < 8)
741 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
742 else
743 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
744 break;
745 case RDI2:
746 if (cid < 8)
747 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
748 else
749 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
750 break;
751 default:
752 return;
753 }
754
755 if (enable)
756 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
757 else
758 val = 0;
759
760 writel_relaxed(val, ispif->base + addr);
761}
762
763
764
765
766
767
768
769
770
771static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
772 enum ispif_intf intf, u8 vfe, u8 vc)
773{
774 u32 *val;
775
776 if (intf == RDI2) {
777 val = &ispif->intf_cmd[vfe].cmd_1;
778 *val &= ~(0x3 << (vc * 2 + 8));
779 *val |= (cmd << (vc * 2 + 8));
780 wmb();
781 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
782 wmb();
783 } else {
784 val = &ispif->intf_cmd[vfe].cmd_0;
785 *val &= ~(0x3 << (vc * 2 + intf * 8));
786 *val |= (cmd << (vc * 2 + intf * 8));
787 wmb();
788 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
789 wmb();
790 }
791}
792
793
794
795
796
797
798
799
800
801
802static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
803{
804 struct ispif_line *line = v4l2_get_subdevdata(sd);
805 struct ispif_device *ispif = line->ispif;
806 struct camss *camss = ispif->camss;
807 enum ispif_intf intf = line->interface;
808 u8 csid = line->csid_id;
809 u8 vfe = line->vfe_id;
810 u8 vc = 0;
811 u8 cid = vc * 4;
812 int ret;
813
814 if (enable) {
815 if (!media_entity_remote_pad(&line->pads[MSM_ISPIF_PAD_SINK]))
816 return -ENOLINK;
817
818
819
820 mutex_lock(&ispif->config_lock);
821 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
822
823 ret = ispif_validate_intf_status(ispif, intf, vfe);
824 if (ret < 0) {
825 mutex_unlock(&ispif->config_lock);
826 return ret;
827 }
828
829 ispif_select_csid(ispif, intf, csid, vfe, 1);
830 ispif_select_cid(ispif, intf, cid, vfe, 1);
831 ispif_config_irq(ispif, intf, vfe, 1);
832 if (camss->version == CAMSS_8x96 ||
833 camss->version == CAMSS_660)
834 ispif_config_pack(ispif,
835 line->fmt[MSM_ISPIF_PAD_SINK].code,
836 intf, cid, vfe, 1);
837 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
838 intf, vfe, vc);
839 } else {
840 mutex_lock(&ispif->config_lock);
841 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
842 intf, vfe, vc);
843 mutex_unlock(&ispif->config_lock);
844
845 ret = ispif_wait_for_stop(ispif, intf, vfe);
846 if (ret < 0)
847 return ret;
848
849 mutex_lock(&ispif->config_lock);
850 if (camss->version == CAMSS_8x96 ||
851 camss->version == CAMSS_660)
852 ispif_config_pack(ispif,
853 line->fmt[MSM_ISPIF_PAD_SINK].code,
854 intf, cid, vfe, 0);
855 ispif_config_irq(ispif, intf, vfe, 0);
856 ispif_select_cid(ispif, intf, cid, vfe, 0);
857 ispif_select_csid(ispif, intf, csid, vfe, 0);
858 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
859 }
860
861 mutex_unlock(&ispif->config_lock);
862
863 return 0;
864}
865
866
867
868
869
870
871
872
873
874
875static struct v4l2_mbus_framefmt *
876__ispif_get_format(struct ispif_line *line,
877 struct v4l2_subdev_state *sd_state,
878 unsigned int pad,
879 enum v4l2_subdev_format_whence which)
880{
881 if (which == V4L2_SUBDEV_FORMAT_TRY)
882 return v4l2_subdev_get_try_format(&line->subdev, sd_state,
883 pad);
884
885 return &line->fmt[pad];
886}
887
888
889
890
891
892
893
894
895
896static void ispif_try_format(struct ispif_line *line,
897 struct v4l2_subdev_state *sd_state,
898 unsigned int pad,
899 struct v4l2_mbus_framefmt *fmt,
900 enum v4l2_subdev_format_whence which)
901{
902 unsigned int i;
903
904 switch (pad) {
905 case MSM_ISPIF_PAD_SINK:
906
907
908 for (i = 0; i < line->nformats; i++)
909 if (fmt->code == line->formats[i])
910 break;
911
912
913 if (i >= line->nformats)
914 fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
915
916 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
917 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
918
919 fmt->field = V4L2_FIELD_NONE;
920 fmt->colorspace = V4L2_COLORSPACE_SRGB;
921
922 break;
923
924 case MSM_ISPIF_PAD_SRC:
925
926
927 *fmt = *__ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SINK,
928 which);
929
930 break;
931 }
932
933 fmt->colorspace = V4L2_COLORSPACE_SRGB;
934}
935
936
937
938
939
940
941
942
943static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
944 struct v4l2_subdev_state *sd_state,
945 struct v4l2_subdev_mbus_code_enum *code)
946{
947 struct ispif_line *line = v4l2_get_subdevdata(sd);
948 struct v4l2_mbus_framefmt *format;
949
950 if (code->pad == MSM_ISPIF_PAD_SINK) {
951 if (code->index >= line->nformats)
952 return -EINVAL;
953
954 code->code = line->formats[code->index];
955 } else {
956 if (code->index > 0)
957 return -EINVAL;
958
959 format = __ispif_get_format(line, sd_state,
960 MSM_ISPIF_PAD_SINK,
961 code->which);
962
963 code->code = format->code;
964 }
965
966 return 0;
967}
968
969
970
971
972
973
974
975
976static int ispif_enum_frame_size(struct v4l2_subdev *sd,
977 struct v4l2_subdev_state *sd_state,
978 struct v4l2_subdev_frame_size_enum *fse)
979{
980 struct ispif_line *line = v4l2_get_subdevdata(sd);
981 struct v4l2_mbus_framefmt format;
982
983 if (fse->index != 0)
984 return -EINVAL;
985
986 format.code = fse->code;
987 format.width = 1;
988 format.height = 1;
989 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
990 fse->min_width = format.width;
991 fse->min_height = format.height;
992
993 if (format.code != fse->code)
994 return -EINVAL;
995
996 format.code = fse->code;
997 format.width = -1;
998 format.height = -1;
999 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
1000 fse->max_width = format.width;
1001 fse->max_height = format.height;
1002
1003 return 0;
1004}
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014static int ispif_get_format(struct v4l2_subdev *sd,
1015 struct v4l2_subdev_state *sd_state,
1016 struct v4l2_subdev_format *fmt)
1017{
1018 struct ispif_line *line = v4l2_get_subdevdata(sd);
1019 struct v4l2_mbus_framefmt *format;
1020
1021 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1022 if (format == NULL)
1023 return -EINVAL;
1024
1025 fmt->format = *format;
1026
1027 return 0;
1028}
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038static int ispif_set_format(struct v4l2_subdev *sd,
1039 struct v4l2_subdev_state *sd_state,
1040 struct v4l2_subdev_format *fmt)
1041{
1042 struct ispif_line *line = v4l2_get_subdevdata(sd);
1043 struct v4l2_mbus_framefmt *format;
1044
1045 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1046 if (format == NULL)
1047 return -EINVAL;
1048
1049 ispif_try_format(line, sd_state, fmt->pad, &fmt->format, fmt->which);
1050 *format = fmt->format;
1051
1052
1053 if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1054 format = __ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SRC,
1055 fmt->which);
1056
1057 *format = fmt->format;
1058 ispif_try_format(line, sd_state, MSM_ISPIF_PAD_SRC, format,
1059 fmt->which);
1060 }
1061
1062 return 0;
1063}
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1075{
1076 struct v4l2_subdev_format format = {
1077 .pad = MSM_ISPIF_PAD_SINK,
1078 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1079 V4L2_SUBDEV_FORMAT_ACTIVE,
1080 .format = {
1081 .code = MEDIA_BUS_FMT_UYVY8_2X8,
1082 .width = 1920,
1083 .height = 1080
1084 }
1085 };
1086
1087 return ispif_set_format(sd, fh ? fh->state : NULL, &format);
1088}
1089
1090
1091
1092
1093
1094
1095
1096
1097int msm_ispif_subdev_init(struct camss *camss,
1098 const struct resources_ispif *res)
1099{
1100 struct device *dev = camss->dev;
1101 struct ispif_device *ispif = camss->ispif;
1102 struct platform_device *pdev = to_platform_device(dev);
1103 struct resource *r;
1104 int i;
1105 int ret;
1106
1107 if (!camss->ispif)
1108 return 0;
1109
1110 ispif->camss = camss;
1111
1112
1113 if (camss->version == CAMSS_8x16)
1114 ispif->line_num = 2;
1115 else if (camss->version == CAMSS_8x96 ||
1116 camss->version == CAMSS_660)
1117 ispif->line_num = 4;
1118 else
1119 return -EINVAL;
1120
1121 ispif->line = devm_kcalloc(dev, ispif->line_num,
1122 sizeof(*ispif->line), GFP_KERNEL);
1123 if (!ispif->line)
1124 return -ENOMEM;
1125
1126 for (i = 0; i < ispif->line_num; i++) {
1127 ispif->line[i].ispif = ispif;
1128 ispif->line[i].id = i;
1129
1130 if (camss->version == CAMSS_8x16) {
1131 ispif->line[i].formats = ispif_formats_8x16;
1132 ispif->line[i].nformats =
1133 ARRAY_SIZE(ispif_formats_8x16);
1134 } else if (camss->version == CAMSS_8x96 ||
1135 camss->version == CAMSS_660) {
1136 ispif->line[i].formats = ispif_formats_8x96;
1137 ispif->line[i].nformats =
1138 ARRAY_SIZE(ispif_formats_8x96);
1139 } else {
1140 return -EINVAL;
1141 }
1142 }
1143
1144
1145
1146 ispif->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]);
1147 if (IS_ERR(ispif->base))
1148 return PTR_ERR(ispif->base);
1149
1150 ispif->base_clk_mux = devm_platform_ioremap_resource_byname(pdev, res->reg[1]);
1151 if (IS_ERR(ispif->base_clk_mux))
1152 return PTR_ERR(ispif->base_clk_mux);
1153
1154
1155
1156 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt);
1157
1158 if (!r) {
1159 dev_err(dev, "missing IRQ\n");
1160 return -EINVAL;
1161 }
1162
1163 ispif->irq = r->start;
1164 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1165 dev_name(dev), MSM_ISPIF_NAME);
1166 if (camss->version == CAMSS_8x16)
1167 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1168 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1169 else if (camss->version == CAMSS_8x96 ||
1170 camss->version == CAMSS_660)
1171 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1172 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1173 else
1174 ret = -EINVAL;
1175
1176 if (ret < 0) {
1177 dev_err(dev, "request_irq failed: %d\n", ret);
1178 return ret;
1179 }
1180
1181
1182
1183 ispif->nclocks = 0;
1184 while (res->clock[ispif->nclocks])
1185 ispif->nclocks++;
1186
1187 ispif->clock = devm_kcalloc(dev,
1188 ispif->nclocks, sizeof(*ispif->clock),
1189 GFP_KERNEL);
1190 if (!ispif->clock)
1191 return -ENOMEM;
1192
1193 for (i = 0; i < ispif->nclocks; i++) {
1194 struct camss_clock *clock = &ispif->clock[i];
1195
1196 clock->clk = devm_clk_get(dev, res->clock[i]);
1197 if (IS_ERR(clock->clk))
1198 return PTR_ERR(clock->clk);
1199
1200 clock->freq = NULL;
1201 clock->nfreqs = 0;
1202 }
1203
1204 ispif->nclocks_for_reset = 0;
1205 while (res->clock_for_reset[ispif->nclocks_for_reset])
1206 ispif->nclocks_for_reset++;
1207
1208 ispif->clock_for_reset = devm_kcalloc(dev,
1209 ispif->nclocks_for_reset,
1210 sizeof(*ispif->clock_for_reset),
1211 GFP_KERNEL);
1212 if (!ispif->clock_for_reset)
1213 return -ENOMEM;
1214
1215 for (i = 0; i < ispif->nclocks_for_reset; i++) {
1216 struct camss_clock *clock = &ispif->clock_for_reset[i];
1217
1218 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1219 if (IS_ERR(clock->clk))
1220 return PTR_ERR(clock->clk);
1221
1222 clock->freq = NULL;
1223 clock->nfreqs = 0;
1224 }
1225
1226 mutex_init(&ispif->power_lock);
1227 ispif->power_count = 0;
1228
1229 mutex_init(&ispif->config_lock);
1230
1231 for (i = 0; i < MSM_ISPIF_VFE_NUM; i++)
1232 init_completion(&ispif->reset_complete[i]);
1233
1234 return 0;
1235}
1236
1237
1238
1239
1240
1241
1242
1243static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1244{
1245 switch (line_id) {
1246 case (VFE_LINE_RDI0):
1247 return RDI0;
1248 case (VFE_LINE_RDI1):
1249 return RDI1;
1250 case (VFE_LINE_RDI2):
1251 return RDI2;
1252 case (VFE_LINE_PIX):
1253 return PIX0;
1254 default:
1255 return RDI0;
1256 }
1257}
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268static int ispif_link_setup(struct media_entity *entity,
1269 const struct media_pad *local,
1270 const struct media_pad *remote, u32 flags)
1271{
1272 if (flags & MEDIA_LNK_FL_ENABLED) {
1273 if (media_entity_remote_pad(local))
1274 return -EBUSY;
1275
1276 if (local->flags & MEDIA_PAD_FL_SINK) {
1277 struct v4l2_subdev *sd;
1278 struct ispif_line *line;
1279
1280 sd = media_entity_to_v4l2_subdev(entity);
1281 line = v4l2_get_subdevdata(sd);
1282
1283 msm_csid_get_csid_id(remote->entity, &line->csid_id);
1284 } else {
1285 struct v4l2_subdev *sd;
1286 struct ispif_line *line;
1287 enum vfe_line_id id;
1288
1289 sd = media_entity_to_v4l2_subdev(entity);
1290 line = v4l2_get_subdevdata(sd);
1291
1292 msm_vfe_get_vfe_id(remote->entity, &line->vfe_id);
1293 msm_vfe_get_vfe_line_id(remote->entity, &id);
1294 line->interface = ispif_get_intf(id);
1295 }
1296 }
1297
1298 return 0;
1299}
1300
1301static const struct v4l2_subdev_core_ops ispif_core_ops = {
1302 .s_power = ispif_set_power,
1303};
1304
1305static const struct v4l2_subdev_video_ops ispif_video_ops = {
1306 .s_stream = ispif_set_stream,
1307};
1308
1309static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1310 .enum_mbus_code = ispif_enum_mbus_code,
1311 .enum_frame_size = ispif_enum_frame_size,
1312 .get_fmt = ispif_get_format,
1313 .set_fmt = ispif_set_format,
1314};
1315
1316static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1317 .core = &ispif_core_ops,
1318 .video = &ispif_video_ops,
1319 .pad = &ispif_pad_ops,
1320};
1321
1322static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1323 .open = ispif_init_formats,
1324};
1325
1326static const struct media_entity_operations ispif_media_ops = {
1327 .link_setup = ispif_link_setup,
1328 .link_validate = v4l2_subdev_link_validate,
1329};
1330
1331
1332
1333
1334
1335
1336
1337
1338int msm_ispif_register_entities(struct ispif_device *ispif,
1339 struct v4l2_device *v4l2_dev)
1340{
1341 struct camss *camss;
1342 int ret;
1343 int i;
1344
1345 if (!ispif)
1346 return 0;
1347
1348 camss = ispif->camss;
1349
1350 for (i = 0; i < ispif->line_num; i++) {
1351 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1352 struct media_pad *pads = ispif->line[i].pads;
1353
1354 v4l2_subdev_init(sd, &ispif_v4l2_ops);
1355 sd->internal_ops = &ispif_v4l2_internal_ops;
1356 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1357 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1358 MSM_ISPIF_NAME, i);
1359 v4l2_set_subdevdata(sd, &ispif->line[i]);
1360
1361 ret = ispif_init_formats(sd, NULL);
1362 if (ret < 0) {
1363 dev_err(camss->dev, "Failed to init format: %d\n", ret);
1364 goto error;
1365 }
1366
1367 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1368 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1369
1370 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1371 sd->entity.ops = &ispif_media_ops;
1372 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1373 pads);
1374 if (ret < 0) {
1375 dev_err(camss->dev, "Failed to init media entity: %d\n",
1376 ret);
1377 goto error;
1378 }
1379
1380 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1381 if (ret < 0) {
1382 dev_err(camss->dev, "Failed to register subdev: %d\n",
1383 ret);
1384 media_entity_cleanup(&sd->entity);
1385 goto error;
1386 }
1387 }
1388
1389 return 0;
1390
1391error:
1392 for (i--; i >= 0; i--) {
1393 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1394
1395 v4l2_device_unregister_subdev(sd);
1396 media_entity_cleanup(&sd->entity);
1397 }
1398
1399 return ret;
1400}
1401
1402
1403
1404
1405
1406void msm_ispif_unregister_entities(struct ispif_device *ispif)
1407{
1408 int i;
1409
1410 if (!ispif)
1411 return;
1412
1413 mutex_destroy(&ispif->power_lock);
1414 mutex_destroy(&ispif->config_lock);
1415
1416 for (i = 0; i < ispif->line_num; i++) {
1417 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1418
1419 v4l2_device_unregister_subdev(sd);
1420 media_entity_cleanup(&sd->entity);
1421 }
1422}
1423
