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10#include <linux/delay.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/iopoll.h>
14
15#include "camss.h"
16#include "camss-vfe.h"
17
18#define VFE_HW_VERSION (0x000)
19
20#define VFE_GLOBAL_RESET_CMD (0x018)
21#define GLOBAL_RESET_CMD_CORE BIT(0)
22#define GLOBAL_RESET_CMD_CAMIF BIT(1)
23#define GLOBAL_RESET_CMD_BUS BIT(2)
24#define GLOBAL_RESET_CMD_BUS_BDG BIT(3)
25#define GLOBAL_RESET_CMD_REGISTER BIT(4)
26#define GLOBAL_RESET_CMD_PM BIT(5)
27#define GLOBAL_RESET_CMD_BUS_MISR BIT(6)
28#define GLOBAL_RESET_CMD_TESTGEN BIT(7)
29#define GLOBAL_RESET_CMD_DSP BIT(8)
30#define GLOBAL_RESET_CMD_IDLE_CGC BIT(9)
31#define GLOBAL_RESET_CMD_RDI0 BIT(10)
32#define GLOBAL_RESET_CMD_RDI1 BIT(11)
33#define GLOBAL_RESET_CMD_RDI2 BIT(12)
34#define GLOBAL_RESET_CMD_RDI3 BIT(13)
35#define GLOBAL_RESET_CMD_VFE_DOMAIN BIT(30)
36#define GLOBAL_RESET_CMD_RESET_BYPASS BIT(31)
37
38#define VFE_CORE_CFG (0x050)
39#define CFG_PIXEL_PATTERN_YCBYCR (0x4)
40#define CFG_PIXEL_PATTERN_YCRYCB (0x5)
41#define CFG_PIXEL_PATTERN_CBYCRY (0x6)
42#define CFG_PIXEL_PATTERN_CRYCBY (0x7)
43#define CFG_COMPOSITE_REG_UPDATE_EN BIT(4)
44
45#define VFE_IRQ_CMD (0x058)
46#define CMD_GLOBAL_CLEAR BIT(0)
47
48#define VFE_IRQ_MASK_0 (0x05c)
49#define MASK_0_CAMIF_SOF BIT(0)
50#define MASK_0_CAMIF_EOF BIT(1)
51#define MASK_0_RDI_REG_UPDATE(n) BIT((n) + 5)
52#define MASK_0_IMAGE_MASTER_n_PING_PONG(n) BIT((n) + 8)
53#define MASK_0_IMAGE_COMPOSITE_DONE_n(n) BIT((n) + 25)
54#define MASK_0_RESET_ACK BIT(31)
55
56#define VFE_IRQ_MASK_1 (0x060)
57#define MASK_1_CAMIF_ERROR BIT(0)
58#define MASK_1_VIOLATION BIT(7)
59#define MASK_1_BUS_BDG_HALT_ACK BIT(8)
60#define MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(n) BIT((n) + 9)
61#define MASK_1_RDI_SOF(n) BIT((n) + 29)
62
63#define VFE_IRQ_CLEAR_0 (0x064)
64#define VFE_IRQ_CLEAR_1 (0x068)
65
66#define VFE_IRQ_STATUS_0 (0x06c)
67#define STATUS_0_CAMIF_SOF BIT(0)
68#define STATUS_0_RDI_REG_UPDATE(n) BIT((n) + 5)
69#define STATUS_0_IMAGE_MASTER_PING_PONG(n) BIT((n) + 8)
70#define STATUS_0_IMAGE_COMPOSITE_DONE(n) BIT((n) + 25)
71#define STATUS_0_RESET_ACK BIT(31)
72
73#define VFE_IRQ_STATUS_1 (0x070)
74#define STATUS_1_VIOLATION BIT(7)
75#define STATUS_1_BUS_BDG_HALT_ACK BIT(8)
76#define STATUS_1_RDI_SOF(n) BIT((n) + 27)
77
78#define VFE_VIOLATION_STATUS (0x07c)
79
80#define VFE_CAMIF_CMD (0x478)
81#define CMD_CLEAR_CAMIF_STATUS BIT(2)
82
83#define VFE_CAMIF_CFG (0x47c)
84#define CFG_VSYNC_SYNC_EDGE (0)
85#define VSYNC_ACTIVE_HIGH (0)
86#define VSYNC_ACTIVE_LOW (1)
87#define CFG_HSYNC_SYNC_EDGE (1)
88#define HSYNC_ACTIVE_HIGH (0)
89#define HSYNC_ACTIVE_LOW (1)
90#define CFG_VFE_SUBSAMPLE_ENABLE BIT(4)
91#define CFG_BUS_SUBSAMPLE_ENABLE BIT(5)
92#define CFG_VFE_OUTPUT_EN BIT(6)
93#define CFG_BUS_OUTPUT_EN BIT(7)
94#define CFG_BINNING_EN BIT(9)
95#define CFG_FRAME_BASED_EN BIT(10)
96#define CFG_RAW_CROP_EN BIT(22)
97
98#define VFE_REG_UPDATE_CMD (0x4ac)
99#define REG_UPDATE_RDI(n) BIT(1 + (n))
100
101#define VFE_BUS_IRQ_MASK(n) (0x2044 + (n) * 4)
102#define VFE_BUS_IRQ_CLEAR(n) (0x2050 + (n) * 4)
103#define VFE_BUS_IRQ_STATUS(n) (0x205c + (n) * 4)
104#define STATUS0_COMP_RESET_DONE BIT(0)
105#define STATUS0_COMP_REG_UPDATE0_DONE BIT(1)
106#define STATUS0_COMP_REG_UPDATE1_DONE BIT(2)
107#define STATUS0_COMP_REG_UPDATE2_DONE BIT(3)
108#define STATUS0_COMP_REG_UPDATE3_DONE BIT(4)
109#define STATUS0_COMP_REG_UPDATE_DONE(n) BIT((n) + 1)
110#define STATUS0_COMP0_BUF_DONE BIT(5)
111#define STATUS0_COMP1_BUF_DONE BIT(6)
112#define STATUS0_COMP2_BUF_DONE BIT(7)
113#define STATUS0_COMP3_BUF_DONE BIT(8)
114#define STATUS0_COMP4_BUF_DONE BIT(9)
115#define STATUS0_COMP5_BUF_DONE BIT(10)
116#define STATUS0_COMP_BUF_DONE(n) BIT((n) + 5)
117#define STATUS0_COMP_ERROR BIT(11)
118#define STATUS0_COMP_OVERWRITE BIT(12)
119#define STATUS0_OVERFLOW BIT(13)
120#define STATUS0_VIOLATION BIT(14)
121
122#define STATUS1_WM_CLIENT_BUF_DONE(n) BIT(n)
123#define STATUS1_EARLY_DONE BIT(24)
124#define STATUS2_DUAL_COMP0_BUF_DONE BIT(0)
125#define STATUS2_DUAL_COMP1_BUF_DONE BIT(1)
126#define STATUS2_DUAL_COMP2_BUF_DONE BIT(2)
127#define STATUS2_DUAL_COMP3_BUF_DONE BIT(3)
128#define STATUS2_DUAL_COMP4_BUF_DONE BIT(4)
129#define STATUS2_DUAL_COMP5_BUF_DONE BIT(5)
130#define STATUS2_DUAL_COMP_BUF_DONE(n) BIT(n)
131#define STATUS2_DUAL_COMP_ERROR BIT(6)
132#define STATUS2_DUAL_COMP_OVERWRITE BIT(7)
133
134#define VFE_BUS_IRQ_CLEAR_GLOBAL (0x2068)
135
136#define VFE_BUS_WM_DEBUG_STATUS_CFG (0x226c)
137#define DEBUG_STATUS_CFG_STATUS0(n) BIT(n)
138#define DEBUG_STATUS_CFG_STATUS1(n) BIT(8 + (n))
139
140#define VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER (0x2080)
141
142#define VFE_BUS_WM_ADDR_SYNC_NO_SYNC (0x2084)
143#define BUS_VER2_MAX_CLIENTS (24)
144#define WM_ADDR_NO_SYNC_DEFAULT_VAL \
145 ((1 << BUS_VER2_MAX_CLIENTS) - 1)
146
147#define VFE_BUS_WM_CGC_OVERRIDE (0x200c)
148#define WM_CGC_OVERRIDE_ALL (0xFFFFF)
149
150#define VFE_BUS_WM_TEST_BUS_CTRL (0x211c)
151
152#define VFE_BUS_WM_STATUS0(n) (0x2200 + (n) * 0x100)
153#define VFE_BUS_WM_STATUS1(n) (0x2204 + (n) * 0x100)
154#define VFE_BUS_WM_CFG(n) (0x2208 + (n) * 0x100)
155#define WM_CFG_EN (0)
156#define WM_CFG_MODE (1)
157#define MODE_QCOM_PLAIN (0)
158#define MODE_MIPI_RAW (1)
159#define WM_CFG_VIRTUALFRAME (2)
160#define VFE_BUS_WM_HEADER_ADDR(n) (0x220c + (n) * 0x100)
161#define VFE_BUS_WM_HEADER_CFG(n) (0x2210 + (n) * 0x100)
162#define VFE_BUS_WM_IMAGE_ADDR(n) (0x2214 + (n) * 0x100)
163#define VFE_BUS_WM_IMAGE_ADDR_OFFSET(n) (0x2218 + (n) * 0x100)
164#define VFE_BUS_WM_BUFFER_WIDTH_CFG(n) (0x221c + (n) * 0x100)
165#define WM_BUFFER_DEFAULT_WIDTH (0xFF01)
166
167#define VFE_BUS_WM_BUFFER_HEIGHT_CFG(n) (0x2220 + (n) * 0x100)
168#define VFE_BUS_WM_PACKER_CFG(n) (0x2224 + (n) * 0x100)
169
170#define VFE_BUS_WM_STRIDE(n) (0x2228 + (n) * 0x100)
171#define WM_STRIDE_DEFAULT_STRIDE (0xFF01)
172
173#define VFE_BUS_WM_IRQ_SUBSAMPLE_PERIOD(n) (0x2248 + (n) * 0x100)
174#define VFE_BUS_WM_IRQ_SUBSAMPLE_PATTERN(n) (0x224c + (n) * 0x100)
175#define VFE_BUS_WM_FRAMEDROP_PERIOD(n) (0x2250 + (n) * 0x100)
176#define VFE_BUS_WM_FRAMEDROP_PATTERN(n) (0x2254 + (n) * 0x100)
177#define VFE_BUS_WM_FRAME_INC(n) (0x2258 + (n) * 0x100)
178#define VFE_BUS_WM_BURST_LIMIT(n) (0x225c + (n) * 0x100)
179
180static void vfe_hw_version_read(struct vfe_device *vfe, struct device *dev)
181{
182 u32 hw_version = readl_relaxed(vfe->base + VFE_HW_VERSION);
183
184 u32 gen = (hw_version >> 28) & 0xF;
185 u32 rev = (hw_version >> 16) & 0xFFF;
186 u32 step = hw_version & 0xFFFF;
187
188 dev_err(dev, "VFE HW Version = %u.%u.%u\n", gen, rev, step);
189}
190
191static inline void vfe_reg_clr(struct vfe_device *vfe, u32 reg, u32 clr_bits)
192{
193 u32 bits = readl_relaxed(vfe->base + reg);
194
195 writel_relaxed(bits & ~clr_bits, vfe->base + reg);
196}
197
198static inline void vfe_reg_set(struct vfe_device *vfe, u32 reg, u32 set_bits)
199{
200 u32 bits = readl_relaxed(vfe->base + reg);
201
202 writel_relaxed(bits | set_bits, vfe->base + reg);
203}
204
205static void vfe_global_reset(struct vfe_device *vfe)
206{
207 u32 reset_bits = GLOBAL_RESET_CMD_CORE |
208 GLOBAL_RESET_CMD_CAMIF |
209 GLOBAL_RESET_CMD_BUS |
210 GLOBAL_RESET_CMD_BUS_BDG |
211 GLOBAL_RESET_CMD_REGISTER |
212 GLOBAL_RESET_CMD_TESTGEN |
213 GLOBAL_RESET_CMD_DSP |
214 GLOBAL_RESET_CMD_IDLE_CGC |
215 GLOBAL_RESET_CMD_RDI0 |
216 GLOBAL_RESET_CMD_RDI1 |
217 GLOBAL_RESET_CMD_RDI2;
218
219 writel_relaxed(BIT(31), vfe->base + VFE_IRQ_MASK_0);
220
221
222 wmb();
223
224 writel_relaxed(reset_bits, vfe->base + VFE_GLOBAL_RESET_CMD);
225}
226
227static void vfe_wm_start(struct vfe_device *vfe, u8 wm, struct vfe_line *line)
228{
229 u32 val;
230
231
232 val = DEBUG_STATUS_CFG_STATUS0(1) |
233 DEBUG_STATUS_CFG_STATUS0(7);
234 writel_relaxed(val, vfe->base + VFE_BUS_WM_DEBUG_STATUS_CFG);
235
236
237 writel_relaxed(0, vfe->base + VFE_BUS_WM_ADDR_SYNC_FRAME_HEADER);
238
239
240 val = WM_CGC_OVERRIDE_ALL;
241 writel_relaxed(val, vfe->base + VFE_BUS_WM_CGC_OVERRIDE);
242
243 writel_relaxed(0x0, vfe->base + VFE_BUS_WM_TEST_BUS_CTRL);
244
245
246 val = WM_ADDR_NO_SYNC_DEFAULT_VAL;
247 writel_relaxed(val, vfe->base + VFE_BUS_WM_ADDR_SYNC_NO_SYNC);
248
249 writel_relaxed(0xf, vfe->base + VFE_BUS_WM_BURST_LIMIT(wm));
250
251 val = WM_BUFFER_DEFAULT_WIDTH;
252 writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_WIDTH_CFG(wm));
253
254 val = 0;
255 writel_relaxed(val, vfe->base + VFE_BUS_WM_BUFFER_HEIGHT_CFG(wm));
256
257 val = 0;
258 writel_relaxed(val, vfe->base + VFE_BUS_WM_PACKER_CFG(wm));
259
260
261 val = WM_STRIDE_DEFAULT_STRIDE;
262 writel_relaxed(val, vfe->base + VFE_BUS_WM_STRIDE(wm));
263
264
265 val = 1 << WM_CFG_EN |
266 MODE_MIPI_RAW << WM_CFG_MODE;
267 writel_relaxed(val, vfe->base + VFE_BUS_WM_CFG(wm));
268}
269
270static void vfe_wm_stop(struct vfe_device *vfe, u8 wm)
271{
272
273 writel_relaxed(0, vfe->base + VFE_BUS_WM_CFG(wm));
274}
275
276static void vfe_wm_update(struct vfe_device *vfe, u8 wm, u32 addr,
277 struct vfe_line *line)
278{
279 struct v4l2_pix_format_mplane *pix =
280 &line->video_out.active_fmt.fmt.pix_mp;
281 u32 stride = pix->plane_fmt[0].bytesperline;
282
283 writel_relaxed(addr, vfe->base + VFE_BUS_WM_IMAGE_ADDR(wm));
284 writel_relaxed(stride * pix->height, vfe->base + VFE_BUS_WM_FRAME_INC(wm));
285}
286
287static void vfe_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
288{
289 vfe->reg_update |= REG_UPDATE_RDI(line_id);
290
291
292 wmb();
293
294 writel_relaxed(vfe->reg_update, vfe->base + VFE_REG_UPDATE_CMD);
295
296
297 wmb();
298}
299
300static inline void vfe_reg_update_clear(struct vfe_device *vfe,
301 enum vfe_line_id line_id)
302{
303 vfe->reg_update &= ~REG_UPDATE_RDI(line_id);
304}
305
306static void vfe_enable_irq_common(struct vfe_device *vfe)
307{
308 vfe_reg_set(vfe, VFE_IRQ_MASK_0, ~0u);
309 vfe_reg_set(vfe, VFE_IRQ_MASK_1, ~0u);
310
311 writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(0));
312 writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(1));
313 writel_relaxed(~0u, vfe->base + VFE_BUS_IRQ_MASK(2));
314}
315
316static void vfe_isr_halt_ack(struct vfe_device *vfe)
317{
318 complete(&vfe->halt_complete);
319}
320
321static void vfe_isr_read(struct vfe_device *vfe, u32 *status0, u32 *status1)
322{
323 *status0 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_0);
324 *status1 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_1);
325
326 writel_relaxed(*status0, vfe->base + VFE_IRQ_CLEAR_0);
327 writel_relaxed(*status1, vfe->base + VFE_IRQ_CLEAR_1);
328
329
330 wmb();
331 writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
332}
333
334static void vfe_violation_read(struct vfe_device *vfe)
335{
336 u32 violation = readl_relaxed(vfe->base + VFE_VIOLATION_STATUS);
337
338 pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);
339}
340
341
342
343
344
345
346
347
348static irqreturn_t vfe_isr(int irq, void *dev)
349{
350 struct vfe_device *vfe = dev;
351 u32 status0, status1, vfe_bus_status[3];
352 int i, wm;
353
354 status0 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_0);
355 status1 = readl_relaxed(vfe->base + VFE_IRQ_STATUS_1);
356
357 writel_relaxed(status0, vfe->base + VFE_IRQ_CLEAR_0);
358 writel_relaxed(status1, vfe->base + VFE_IRQ_CLEAR_1);
359
360 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++) {
361 vfe_bus_status[i] = readl_relaxed(vfe->base + VFE_BUS_IRQ_STATUS(i));
362 writel_relaxed(vfe_bus_status[i], vfe->base + VFE_BUS_IRQ_CLEAR(i));
363 }
364
365
366 wmb();
367
368 writel_relaxed(CMD_GLOBAL_CLEAR, vfe->base + VFE_IRQ_CMD);
369 writel_relaxed(1, vfe->base + VFE_BUS_IRQ_CLEAR_GLOBAL);
370
371 if (status0 & STATUS_0_RESET_ACK)
372 vfe->isr_ops.reset_ack(vfe);
373
374 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++)
375 if (status0 & STATUS_0_RDI_REG_UPDATE(i))
376 vfe->isr_ops.reg_update(vfe, i);
377
378 for (i = VFE_LINE_RDI0; i <= VFE_LINE_RDI2; i++)
379 if (status0 & STATUS_1_RDI_SOF(i))
380 vfe->isr_ops.sof(vfe, i);
381
382 for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)
383 if (vfe_bus_status[0] & STATUS0_COMP_BUF_DONE(i))
384 vfe->isr_ops.comp_done(vfe, i);
385
386 for (wm = 0; wm < MSM_VFE_IMAGE_MASTERS_NUM; wm++)
387 if (status0 & BIT(9))
388 if (vfe_bus_status[1] & STATUS1_WM_CLIENT_BUF_DONE(wm))
389 vfe->isr_ops.wm_done(vfe, wm);
390
391 return IRQ_HANDLED;
392}
393
394
395
396
397
398
399
400static int vfe_halt(struct vfe_device *vfe)
401{
402 unsigned long time;
403
404 reinit_completion(&vfe->halt_complete);
405
406 time = wait_for_completion_timeout(&vfe->halt_complete,
407 msecs_to_jiffies(VFE_HALT_TIMEOUT_MS));
408 if (!time) {
409 dev_err(vfe->camss->dev, "VFE halt timeout\n");
410 return -EIO;
411 }
412
413 return 0;
414}
415
416static int vfe_get_output(struct vfe_line *line)
417{
418 struct vfe_device *vfe = to_vfe(line);
419 struct vfe_output *output;
420 unsigned long flags;
421 int wm_idx;
422
423 spin_lock_irqsave(&vfe->output_lock, flags);
424
425 output = &line->output;
426 if (output->state != VFE_OUTPUT_OFF) {
427 dev_err(vfe->camss->dev, "Output is running\n");
428 goto error;
429 }
430
431 output->wm_num = 1;
432
433 wm_idx = vfe_reserve_wm(vfe, line->id);
434 if (wm_idx < 0) {
435 dev_err(vfe->camss->dev, "Can not reserve wm\n");
436 goto error_get_wm;
437 }
438 output->wm_idx[0] = wm_idx;
439
440 output->drop_update_idx = 0;
441
442 spin_unlock_irqrestore(&vfe->output_lock, flags);
443
444 return 0;
445
446error_get_wm:
447 vfe_release_wm(vfe, output->wm_idx[0]);
448 output->state = VFE_OUTPUT_OFF;
449error:
450 spin_unlock_irqrestore(&vfe->output_lock, flags);
451
452 return -EINVAL;
453}
454
455static int vfe_enable_output(struct vfe_line *line)
456{
457 struct vfe_device *vfe = to_vfe(line);
458 struct vfe_output *output = &line->output;
459 const struct vfe_hw_ops *ops = vfe->ops;
460 struct media_entity *sensor;
461 unsigned long flags;
462 unsigned int frame_skip = 0;
463 unsigned int i;
464
465 sensor = camss_find_sensor(&line->subdev.entity);
466 if (sensor) {
467 struct v4l2_subdev *subdev = media_entity_to_v4l2_subdev(sensor);
468
469 v4l2_subdev_call(subdev, sensor, g_skip_frames, &frame_skip);
470
471 if (frame_skip > VFE_FRAME_DROP_VAL - 1)
472 frame_skip = VFE_FRAME_DROP_VAL - 1;
473 }
474
475 spin_lock_irqsave(&vfe->output_lock, flags);
476
477 ops->reg_update_clear(vfe, line->id);
478
479 if (output->state != VFE_OUTPUT_OFF) {
480 dev_err(vfe->camss->dev, "Output is not in reserved state %d\n",
481 output->state);
482 spin_unlock_irqrestore(&vfe->output_lock, flags);
483 return -EINVAL;
484 }
485
486 WARN_ON(output->gen2.active_num);
487
488 output->state = VFE_OUTPUT_ON;
489
490 output->sequence = 0;
491 output->wait_reg_update = 0;
492 reinit_completion(&output->reg_update);
493
494 vfe_wm_start(vfe, output->wm_idx[0], line);
495
496 for (i = 0; i < 2; i++) {
497 output->buf[i] = vfe_buf_get_pending(output);
498 if (!output->buf[i])
499 break;
500 output->gen2.active_num++;
501 vfe_wm_update(vfe, output->wm_idx[0], output->buf[i]->addr[0], line);
502 }
503
504 ops->reg_update(vfe, line->id);
505
506 spin_unlock_irqrestore(&vfe->output_lock, flags);
507
508 return 0;
509}
510
511static int vfe_disable_output(struct vfe_line *line)
512{
513 struct vfe_device *vfe = to_vfe(line);
514 struct vfe_output *output = &line->output;
515 unsigned long flags;
516 unsigned int i;
517 bool done;
518 int timeout = 0;
519
520 do {
521 spin_lock_irqsave(&vfe->output_lock, flags);
522 done = !output->gen2.active_num;
523 spin_unlock_irqrestore(&vfe->output_lock, flags);
524 usleep_range(10000, 20000);
525
526 if (timeout++ == 100) {
527 dev_err(vfe->camss->dev, "VFE idle timeout - resetting\n");
528 vfe_reset(vfe);
529 output->gen2.active_num = 0;
530 return 0;
531 }
532 } while (!done);
533
534 spin_lock_irqsave(&vfe->output_lock, flags);
535 for (i = 0; i < output->wm_num; i++)
536 vfe_wm_stop(vfe, output->wm_idx[i]);
537 spin_unlock_irqrestore(&vfe->output_lock, flags);
538
539 return 0;
540}
541
542
543
544
545
546
547
548static int vfe_enable(struct vfe_line *line)
549{
550 struct vfe_device *vfe = to_vfe(line);
551 int ret;
552
553 mutex_lock(&vfe->stream_lock);
554
555 if (!vfe->stream_count)
556 vfe_enable_irq_common(vfe);
557
558 vfe->stream_count++;
559
560 mutex_unlock(&vfe->stream_lock);
561
562 ret = vfe_get_output(line);
563 if (ret < 0)
564 goto error_get_output;
565
566 ret = vfe_enable_output(line);
567 if (ret < 0)
568 goto error_enable_output;
569
570 vfe->was_streaming = 1;
571
572 return 0;
573
574error_enable_output:
575 vfe_put_output(line);
576
577error_get_output:
578 mutex_lock(&vfe->stream_lock);
579
580 vfe->stream_count--;
581
582 mutex_unlock(&vfe->stream_lock);
583
584 return ret;
585}
586
587
588
589
590
591
592
593static int vfe_disable(struct vfe_line *line)
594{
595 struct vfe_device *vfe = to_vfe(line);
596
597 vfe_disable_output(line);
598
599 vfe_put_output(line);
600
601 mutex_lock(&vfe->stream_lock);
602
603 vfe->stream_count--;
604
605 mutex_unlock(&vfe->stream_lock);
606
607 return 0;
608}
609
610
611
612
613
614
615static void vfe_isr_sof(struct vfe_device *vfe, enum vfe_line_id line_id)
616{
617
618}
619
620
621
622
623
624
625static void vfe_isr_reg_update(struct vfe_device *vfe, enum vfe_line_id line_id)
626{
627 struct vfe_output *output;
628 unsigned long flags;
629
630 spin_lock_irqsave(&vfe->output_lock, flags);
631 vfe->ops->reg_update_clear(vfe, line_id);
632
633 output = &vfe->line[line_id].output;
634
635 if (output->wait_reg_update) {
636 output->wait_reg_update = 0;
637 complete(&output->reg_update);
638 }
639
640 spin_unlock_irqrestore(&vfe->output_lock, flags);
641}
642
643
644
645
646
647
648static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm)
649{
650 struct vfe_line *line = &vfe->line[vfe->wm_output_map[wm]];
651 struct camss_buffer *ready_buf;
652 struct vfe_output *output;
653 unsigned long flags;
654 u32 index;
655 u64 ts = ktime_get_ns();
656
657 spin_lock_irqsave(&vfe->output_lock, flags);
658
659 if (vfe->wm_output_map[wm] == VFE_LINE_NONE) {
660 dev_err_ratelimited(vfe->camss->dev,
661 "Received wm done for unmapped index\n");
662 goto out_unlock;
663 }
664 output = &vfe->line[vfe->wm_output_map[wm]].output;
665
666 ready_buf = output->buf[0];
667 if (!ready_buf) {
668 dev_err_ratelimited(vfe->camss->dev,
669 "Missing ready buf %d!\n", output->state);
670 goto out_unlock;
671 }
672
673 ready_buf->vb.vb2_buf.timestamp = ts;
674 ready_buf->vb.sequence = output->sequence++;
675
676 index = 0;
677 output->buf[0] = output->buf[1];
678 if (output->buf[0])
679 index = 1;
680
681 output->buf[index] = vfe_buf_get_pending(output);
682
683 if (output->buf[index])
684 vfe_wm_update(vfe, output->wm_idx[0], output->buf[index]->addr[0], line);
685 else
686 output->gen2.active_num--;
687
688 spin_unlock_irqrestore(&vfe->output_lock, flags);
689
690 vb2_buffer_done(&ready_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
691
692 return;
693
694out_unlock:
695 spin_unlock_irqrestore(&vfe->output_lock, flags);
696}
697
698
699
700
701
702static void vfe_pm_domain_off(struct vfe_device *vfe)
703{
704
705}
706
707
708
709
710
711static int vfe_pm_domain_on(struct vfe_device *vfe)
712{
713 return 0;
714}
715
716
717
718
719
720
721
722
723
724
725
726static int vfe_queue_buffer(struct camss_video *vid,
727 struct camss_buffer *buf)
728{
729 struct vfe_line *line = container_of(vid, struct vfe_line, video_out);
730 struct vfe_device *vfe = to_vfe(line);
731 struct vfe_output *output;
732 unsigned long flags;
733
734 output = &line->output;
735
736 spin_lock_irqsave(&vfe->output_lock, flags);
737
738 if (output->state == VFE_OUTPUT_ON && output->gen2.active_num < 2) {
739 output->buf[output->gen2.active_num++] = buf;
740 vfe_wm_update(vfe, output->wm_idx[0], buf->addr[0], line);
741 } else {
742 vfe_buf_add_pending(output, buf);
743 }
744
745 spin_unlock_irqrestore(&vfe->output_lock, flags);
746
747 return 0;
748}
749
750static const struct vfe_isr_ops vfe_isr_ops_170 = {
751 .reset_ack = vfe_isr_reset_ack,
752 .halt_ack = vfe_isr_halt_ack,
753 .reg_update = vfe_isr_reg_update,
754 .sof = vfe_isr_sof,
755 .comp_done = vfe_isr_comp_done,
756 .wm_done = vfe_isr_wm_done,
757};
758
759static const struct camss_video_ops vfe_video_ops_170 = {
760 .queue_buffer = vfe_queue_buffer,
761 .flush_buffers = vfe_flush_buffers,
762};
763
764static void vfe_subdev_init(struct device *dev, struct vfe_device *vfe)
765{
766 vfe->isr_ops = vfe_isr_ops_170;
767 vfe->video_ops = vfe_video_ops_170;
768
769 vfe->line_num = VFE_LINE_NUM_GEN2;
770}
771
772const struct vfe_hw_ops vfe_ops_170 = {
773 .global_reset = vfe_global_reset,
774 .hw_version_read = vfe_hw_version_read,
775 .isr_read = vfe_isr_read,
776 .isr = vfe_isr,
777 .pm_domain_off = vfe_pm_domain_off,
778 .pm_domain_on = vfe_pm_domain_on,
779 .reg_update_clear = vfe_reg_update_clear,
780 .reg_update = vfe_reg_update,
781 .subdev_init = vfe_subdev_init,
782 .vfe_disable = vfe_disable,
783 .vfe_enable = vfe_enable,
784 .vfe_halt = vfe_halt,
785 .violation_read = vfe_violation_read,
786};
787