1
2
3
4
5
6
7
8
9
10
11#include <linux/delay.h>
12#include <linux/pm_runtime.h>
13#include <media/v4l2-common.h>
14#include <media/v4l2-event.h>
15#include <media/v4l2-fh.h>
16#include <media/v4l2-ioctl.h>
17#include <media/v4l2-mc.h>
18#include <media/v4l2-subdev.h>
19#include <media/videobuf2-dma-contig.h>
20
21#include "rkisp1-common.h"
22
23
24
25
26
27
28
29
30
31
32
33
34
35#define RKISP1_SP_DEV_NAME RKISP1_DRIVER_NAME "_selfpath"
36#define RKISP1_MP_DEV_NAME RKISP1_DRIVER_NAME "_mainpath"
37
38#define RKISP1_MIN_BUFFERS_NEEDED 3
39
40enum rkisp1_plane {
41 RKISP1_PLANE_Y = 0,
42 RKISP1_PLANE_CB = 1,
43 RKISP1_PLANE_CR = 2
44};
45
46
47
48
49
50
51
52
53
54struct rkisp1_capture_fmt_cfg {
55 u32 fourcc;
56 u8 uv_swap;
57 u32 write_format;
58 u32 output_format;
59 u32 mbus;
60};
61
62struct rkisp1_capture_ops {
63 void (*config)(struct rkisp1_capture *cap);
64 void (*stop)(struct rkisp1_capture *cap);
65 void (*enable)(struct rkisp1_capture *cap);
66 void (*disable)(struct rkisp1_capture *cap);
67 void (*set_data_path)(struct rkisp1_capture *cap);
68 bool (*is_stopped)(struct rkisp1_capture *cap);
69};
70
71struct rkisp1_capture_config {
72 const struct rkisp1_capture_fmt_cfg *fmts;
73 int fmt_size;
74 struct {
75 u32 y_size_init;
76 u32 cb_size_init;
77 u32 cr_size_init;
78 u32 y_base_ad_init;
79 u32 cb_base_ad_init;
80 u32 cr_base_ad_init;
81 u32 y_offs_cnt_init;
82 u32 cb_offs_cnt_init;
83 u32 cr_offs_cnt_init;
84 } mi;
85};
86
87
88
89
90
91static const struct rkisp1_capture_fmt_cfg rkisp1_mp_fmts[] = {
92
93 {
94 .fourcc = V4L2_PIX_FMT_YUYV,
95 .uv_swap = 0,
96 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUVINT,
97 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
98 }, {
99 .fourcc = V4L2_PIX_FMT_YUV422P,
100 .uv_swap = 0,
101 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
102 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
103 }, {
104 .fourcc = V4L2_PIX_FMT_NV16,
105 .uv_swap = 0,
106 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
107 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
108 }, {
109 .fourcc = V4L2_PIX_FMT_NV61,
110 .uv_swap = 1,
111 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
112 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
113 }, {
114 .fourcc = V4L2_PIX_FMT_YVU422M,
115 .uv_swap = 1,
116 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
117 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
118 },
119
120 {
121 .fourcc = V4L2_PIX_FMT_GREY,
122 .uv_swap = 0,
123 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
124 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
125 },
126
127 {
128 .fourcc = V4L2_PIX_FMT_NV21,
129 .uv_swap = 1,
130 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
131 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
132 }, {
133 .fourcc = V4L2_PIX_FMT_NV12,
134 .uv_swap = 0,
135 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
136 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
137 }, {
138 .fourcc = V4L2_PIX_FMT_NV21M,
139 .uv_swap = 1,
140 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
141 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
142 }, {
143 .fourcc = V4L2_PIX_FMT_NV12M,
144 .uv_swap = 0,
145 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_SPLA,
146 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
147 }, {
148 .fourcc = V4L2_PIX_FMT_YUV420,
149 .uv_swap = 0,
150 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
151 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
152 }, {
153 .fourcc = V4L2_PIX_FMT_YVU420,
154 .uv_swap = 1,
155 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
156 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
157 },
158
159 {
160 .fourcc = V4L2_PIX_FMT_SRGGB8,
161 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
162 .mbus = MEDIA_BUS_FMT_SRGGB8_1X8,
163 }, {
164 .fourcc = V4L2_PIX_FMT_SGRBG8,
165 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
166 .mbus = MEDIA_BUS_FMT_SGRBG8_1X8,
167 }, {
168 .fourcc = V4L2_PIX_FMT_SGBRG8,
169 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
170 .mbus = MEDIA_BUS_FMT_SGBRG8_1X8,
171 }, {
172 .fourcc = V4L2_PIX_FMT_SBGGR8,
173 .write_format = RKISP1_MI_CTRL_MP_WRITE_YUV_PLA_OR_RAW8,
174 .mbus = MEDIA_BUS_FMT_SBGGR8_1X8,
175 }, {
176 .fourcc = V4L2_PIX_FMT_SRGGB10,
177 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
178 .mbus = MEDIA_BUS_FMT_SRGGB10_1X10,
179 }, {
180 .fourcc = V4L2_PIX_FMT_SGRBG10,
181 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
182 .mbus = MEDIA_BUS_FMT_SGRBG10_1X10,
183 }, {
184 .fourcc = V4L2_PIX_FMT_SGBRG10,
185 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
186 .mbus = MEDIA_BUS_FMT_SGBRG10_1X10,
187 }, {
188 .fourcc = V4L2_PIX_FMT_SBGGR10,
189 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
190 .mbus = MEDIA_BUS_FMT_SBGGR10_1X10,
191 }, {
192 .fourcc = V4L2_PIX_FMT_SRGGB12,
193 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
194 .mbus = MEDIA_BUS_FMT_SRGGB12_1X12,
195 }, {
196 .fourcc = V4L2_PIX_FMT_SGRBG12,
197 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
198 .mbus = MEDIA_BUS_FMT_SGRBG12_1X12,
199 }, {
200 .fourcc = V4L2_PIX_FMT_SGBRG12,
201 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
202 .mbus = MEDIA_BUS_FMT_SGBRG12_1X12,
203 }, {
204 .fourcc = V4L2_PIX_FMT_SBGGR12,
205 .write_format = RKISP1_MI_CTRL_MP_WRITE_RAW12,
206 .mbus = MEDIA_BUS_FMT_SBGGR12_1X12,
207 },
208};
209
210
211
212
213
214static const struct rkisp1_capture_fmt_cfg rkisp1_sp_fmts[] = {
215
216 {
217 .fourcc = V4L2_PIX_FMT_YUYV,
218 .uv_swap = 0,
219 .write_format = RKISP1_MI_CTRL_SP_WRITE_INT,
220 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
221 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
222 }, {
223 .fourcc = V4L2_PIX_FMT_YUV422P,
224 .uv_swap = 0,
225 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
226 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
227 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
228 }, {
229 .fourcc = V4L2_PIX_FMT_NV16,
230 .uv_swap = 0,
231 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
232 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
233 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
234 }, {
235 .fourcc = V4L2_PIX_FMT_NV61,
236 .uv_swap = 1,
237 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
238 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
239 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
240 }, {
241 .fourcc = V4L2_PIX_FMT_YVU422M,
242 .uv_swap = 1,
243 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
244 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV422,
245 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
246 },
247
248 {
249 .fourcc = V4L2_PIX_FMT_GREY,
250 .uv_swap = 0,
251 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
252 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV400,
253 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
254 },
255
256 {
257 .fourcc = V4L2_PIX_FMT_XBGR32,
258 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
259 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB888,
260 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
261 }, {
262 .fourcc = V4L2_PIX_FMT_RGB565,
263 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
264 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_RGB565,
265 .mbus = MEDIA_BUS_FMT_YUYV8_2X8,
266 },
267
268 {
269 .fourcc = V4L2_PIX_FMT_NV21,
270 .uv_swap = 1,
271 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
272 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
273 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
274 }, {
275 .fourcc = V4L2_PIX_FMT_NV12,
276 .uv_swap = 0,
277 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
278 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
279 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
280 }, {
281 .fourcc = V4L2_PIX_FMT_NV21M,
282 .uv_swap = 1,
283 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
284 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
285 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
286 }, {
287 .fourcc = V4L2_PIX_FMT_NV12M,
288 .uv_swap = 0,
289 .write_format = RKISP1_MI_CTRL_SP_WRITE_SPLA,
290 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
291 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
292 }, {
293 .fourcc = V4L2_PIX_FMT_YUV420,
294 .uv_swap = 0,
295 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
296 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
297 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
298 }, {
299 .fourcc = V4L2_PIX_FMT_YVU420,
300 .uv_swap = 1,
301 .write_format = RKISP1_MI_CTRL_SP_WRITE_PLA,
302 .output_format = RKISP1_MI_CTRL_SP_OUTPUT_YUV420,
303 .mbus = MEDIA_BUS_FMT_YUYV8_1_5X8,
304 },
305};
306
307static const struct rkisp1_capture_config rkisp1_capture_config_mp = {
308 .fmts = rkisp1_mp_fmts,
309 .fmt_size = ARRAY_SIZE(rkisp1_mp_fmts),
310 .mi = {
311 .y_size_init = RKISP1_CIF_MI_MP_Y_SIZE_INIT,
312 .cb_size_init = RKISP1_CIF_MI_MP_CB_SIZE_INIT,
313 .cr_size_init = RKISP1_CIF_MI_MP_CR_SIZE_INIT,
314 .y_base_ad_init = RKISP1_CIF_MI_MP_Y_BASE_AD_INIT,
315 .cb_base_ad_init = RKISP1_CIF_MI_MP_CB_BASE_AD_INIT,
316 .cr_base_ad_init = RKISP1_CIF_MI_MP_CR_BASE_AD_INIT,
317 .y_offs_cnt_init = RKISP1_CIF_MI_MP_Y_OFFS_CNT_INIT,
318 .cb_offs_cnt_init = RKISP1_CIF_MI_MP_CB_OFFS_CNT_INIT,
319 .cr_offs_cnt_init = RKISP1_CIF_MI_MP_CR_OFFS_CNT_INIT,
320 },
321};
322
323static const struct rkisp1_capture_config rkisp1_capture_config_sp = {
324 .fmts = rkisp1_sp_fmts,
325 .fmt_size = ARRAY_SIZE(rkisp1_sp_fmts),
326 .mi = {
327 .y_size_init = RKISP1_CIF_MI_SP_Y_SIZE_INIT,
328 .cb_size_init = RKISP1_CIF_MI_SP_CB_SIZE_INIT,
329 .cr_size_init = RKISP1_CIF_MI_SP_CR_SIZE_INIT,
330 .y_base_ad_init = RKISP1_CIF_MI_SP_Y_BASE_AD_INIT,
331 .cb_base_ad_init = RKISP1_CIF_MI_SP_CB_BASE_AD_INIT,
332 .cr_base_ad_init = RKISP1_CIF_MI_SP_CR_BASE_AD_INIT,
333 .y_offs_cnt_init = RKISP1_CIF_MI_SP_Y_OFFS_CNT_INIT,
334 .cb_offs_cnt_init = RKISP1_CIF_MI_SP_CB_OFFS_CNT_INIT,
335 .cr_offs_cnt_init = RKISP1_CIF_MI_SP_CR_OFFS_CNT_INIT,
336 },
337};
338
339static inline struct rkisp1_vdev_node *
340rkisp1_vdev_to_node(struct video_device *vdev)
341{
342 return container_of(vdev, struct rkisp1_vdev_node, vdev);
343}
344
345int rkisp1_cap_enum_mbus_codes(struct rkisp1_capture *cap,
346 struct v4l2_subdev_mbus_code_enum *code)
347{
348 const struct rkisp1_capture_fmt_cfg *fmts = cap->config->fmts;
349
350
351
352
353 u32 curr_mbus = 0;
354 int i, n = 0;
355
356 for (i = 0; i < cap->config->fmt_size; i++) {
357 if (fmts[i].mbus == curr_mbus)
358 continue;
359
360 curr_mbus = fmts[i].mbus;
361 if (n++ == code->index) {
362 code->code = curr_mbus;
363 return 0;
364 }
365 }
366 return -EINVAL;
367}
368
369
370
371
372
373static void rkisp1_mi_config_ctrl(struct rkisp1_capture *cap)
374{
375 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
376
377 mi_ctrl &= ~GENMASK(17, 16);
378 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_LUM_64;
379
380 mi_ctrl &= ~GENMASK(19, 18);
381 mi_ctrl |= RKISP1_CIF_MI_CTRL_BURST_LEN_CHROM_64;
382
383 mi_ctrl |= RKISP1_CIF_MI_CTRL_INIT_BASE_EN |
384 RKISP1_CIF_MI_CTRL_INIT_OFFSET_EN;
385
386 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
387}
388
389static u32 rkisp1_pixfmt_comp_size(const struct v4l2_pix_format_mplane *pixm,
390 unsigned int component)
391{
392
393
394
395
396
397 if (!component && pixm->num_planes == 1)
398 return pixm->plane_fmt[0].bytesperline * pixm->height;
399 return pixm->plane_fmt[component].sizeimage;
400}
401
402static void rkisp1_irq_frame_end_enable(struct rkisp1_capture *cap)
403{
404 u32 mi_imsc = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_IMSC);
405
406 mi_imsc |= RKISP1_CIF_MI_FRAME(cap);
407 rkisp1_write(cap->rkisp1, mi_imsc, RKISP1_CIF_MI_IMSC);
408}
409
410static void rkisp1_mp_config(struct rkisp1_capture *cap)
411{
412 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
413 struct rkisp1_device *rkisp1 = cap->rkisp1;
414 u32 reg;
415
416 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
417 cap->config->mi.y_size_init);
418 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
419 cap->config->mi.cb_size_init);
420 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR),
421 cap->config->mi.cr_size_init);
422
423 rkisp1_irq_frame_end_enable(cap);
424
425
426 if (cap->pix.info->comp_planes == 2) {
427 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
428 if (cap->pix.cfg->uv_swap)
429 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
430 else
431 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_MP_CB_CR_SWAP;
432 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
433 }
434
435 rkisp1_mi_config_ctrl(cap);
436
437 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
438 reg &= ~RKISP1_MI_CTRL_MP_FMT_MASK;
439 reg |= cap->pix.cfg->write_format;
440 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL);
441
442 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
443 reg |= RKISP1_CIF_MI_MP_AUTOUPDATE_ENABLE;
444 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_CTRL);
445}
446
447static void rkisp1_sp_config(struct rkisp1_capture *cap)
448{
449 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
450 struct rkisp1_device *rkisp1 = cap->rkisp1;
451 u32 mi_ctrl, reg;
452
453 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
454 cap->config->mi.y_size_init);
455 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
456 cap->config->mi.cb_size_init);
457 rkisp1_write(rkisp1, rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR),
458 cap->config->mi.cr_size_init);
459
460 rkisp1_write(rkisp1, pixm->width, RKISP1_CIF_MI_SP_Y_PIC_WIDTH);
461 rkisp1_write(rkisp1, pixm->height, RKISP1_CIF_MI_SP_Y_PIC_HEIGHT);
462 rkisp1_write(rkisp1, cap->sp_y_stride, RKISP1_CIF_MI_SP_Y_LLENGTH);
463
464 rkisp1_irq_frame_end_enable(cap);
465
466
467 if (cap->pix.info->comp_planes == 2) {
468 reg = rkisp1_read(rkisp1, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
469 if (cap->pix.cfg->uv_swap)
470 reg |= RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
471 else
472 reg &= ~RKISP1_CIF_MI_XTD_FMT_CTRL_SP_CB_CR_SWAP;
473 rkisp1_write(rkisp1, reg, RKISP1_CIF_MI_XTD_FORMAT_CTRL);
474 }
475
476 rkisp1_mi_config_ctrl(cap);
477
478 mi_ctrl = rkisp1_read(rkisp1, RKISP1_CIF_MI_CTRL);
479 mi_ctrl &= ~RKISP1_MI_CTRL_SP_FMT_MASK;
480 mi_ctrl |= cap->pix.cfg->write_format |
481 RKISP1_MI_CTRL_SP_INPUT_YUV422 |
482 cap->pix.cfg->output_format |
483 RKISP1_CIF_MI_SP_AUTOUPDATE_ENABLE;
484 rkisp1_write(rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
485}
486
487static void rkisp1_mp_disable(struct rkisp1_capture *cap)
488{
489 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
490
491 mi_ctrl &= ~(RKISP1_CIF_MI_CTRL_MP_ENABLE |
492 RKISP1_CIF_MI_CTRL_RAW_ENABLE);
493 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
494}
495
496static void rkisp1_sp_disable(struct rkisp1_capture *cap)
497{
498 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
499
500 mi_ctrl &= ~RKISP1_CIF_MI_CTRL_SP_ENABLE;
501 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
502}
503
504static void rkisp1_mp_enable(struct rkisp1_capture *cap)
505{
506 u32 mi_ctrl;
507
508 rkisp1_mp_disable(cap);
509
510 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
511 if (v4l2_is_format_bayer(cap->pix.info))
512 mi_ctrl |= RKISP1_CIF_MI_CTRL_RAW_ENABLE;
513
514 else
515 mi_ctrl |= RKISP1_CIF_MI_CTRL_MP_ENABLE;
516
517 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
518}
519
520static void rkisp1_sp_enable(struct rkisp1_capture *cap)
521{
522 u32 mi_ctrl = rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL);
523
524 mi_ctrl |= RKISP1_CIF_MI_CTRL_SP_ENABLE;
525 rkisp1_write(cap->rkisp1, mi_ctrl, RKISP1_CIF_MI_CTRL);
526}
527
528static void rkisp1_mp_sp_stop(struct rkisp1_capture *cap)
529{
530 if (!cap->is_streaming)
531 return;
532 rkisp1_write(cap->rkisp1,
533 RKISP1_CIF_MI_FRAME(cap), RKISP1_CIF_MI_ICR);
534 cap->ops->disable(cap);
535}
536
537static bool rkisp1_mp_is_stopped(struct rkisp1_capture *cap)
538{
539 u32 en = RKISP1_CIF_MI_CTRL_SHD_MP_IN_ENABLED |
540 RKISP1_CIF_MI_CTRL_SHD_RAW_OUT_ENABLED;
541
542 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) & en);
543}
544
545static bool rkisp1_sp_is_stopped(struct rkisp1_capture *cap)
546{
547 return !(rkisp1_read(cap->rkisp1, RKISP1_CIF_MI_CTRL_SHD) &
548 RKISP1_CIF_MI_CTRL_SHD_SP_IN_ENABLED);
549}
550
551static void rkisp1_mp_set_data_path(struct rkisp1_capture *cap)
552{
553 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
554
555 dpcl = dpcl | RKISP1_CIF_VI_DPCL_CHAN_MODE_MP |
556 RKISP1_CIF_VI_DPCL_MP_MUX_MRSZ_MI;
557 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
558}
559
560static void rkisp1_sp_set_data_path(struct rkisp1_capture *cap)
561{
562 u32 dpcl = rkisp1_read(cap->rkisp1, RKISP1_CIF_VI_DPCL);
563
564 dpcl |= RKISP1_CIF_VI_DPCL_CHAN_MODE_SP;
565 rkisp1_write(cap->rkisp1, dpcl, RKISP1_CIF_VI_DPCL);
566}
567
568static const struct rkisp1_capture_ops rkisp1_capture_ops_mp = {
569 .config = rkisp1_mp_config,
570 .enable = rkisp1_mp_enable,
571 .disable = rkisp1_mp_disable,
572 .stop = rkisp1_mp_sp_stop,
573 .set_data_path = rkisp1_mp_set_data_path,
574 .is_stopped = rkisp1_mp_is_stopped,
575};
576
577static const struct rkisp1_capture_ops rkisp1_capture_ops_sp = {
578 .config = rkisp1_sp_config,
579 .enable = rkisp1_sp_enable,
580 .disable = rkisp1_sp_disable,
581 .stop = rkisp1_mp_sp_stop,
582 .set_data_path = rkisp1_sp_set_data_path,
583 .is_stopped = rkisp1_sp_is_stopped,
584};
585
586
587
588
589
590static int rkisp1_dummy_buf_create(struct rkisp1_capture *cap)
591{
592 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
593 struct rkisp1_dummy_buffer *dummy_buf = &cap->buf.dummy;
594
595 dummy_buf->size = max3(rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y),
596 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB),
597 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CR));
598
599
600 dummy_buf->vaddr = dma_alloc_attrs(cap->rkisp1->dev,
601 dummy_buf->size,
602 &dummy_buf->dma_addr,
603 GFP_KERNEL,
604 DMA_ATTR_NO_KERNEL_MAPPING);
605 if (!dummy_buf->vaddr)
606 return -ENOMEM;
607
608 return 0;
609}
610
611static void rkisp1_dummy_buf_destroy(struct rkisp1_capture *cap)
612{
613 dma_free_attrs(cap->rkisp1->dev,
614 cap->buf.dummy.size, cap->buf.dummy.vaddr,
615 cap->buf.dummy.dma_addr, DMA_ATTR_NO_KERNEL_MAPPING);
616}
617
618static void rkisp1_set_next_buf(struct rkisp1_capture *cap)
619{
620 cap->buf.curr = cap->buf.next;
621 cap->buf.next = NULL;
622
623 if (!list_empty(&cap->buf.queue)) {
624 u32 *buff_addr;
625
626 cap->buf.next = list_first_entry(&cap->buf.queue, struct rkisp1_buffer, queue);
627 list_del(&cap->buf.next->queue);
628
629 buff_addr = cap->buf.next->buff_addr;
630
631 rkisp1_write(cap->rkisp1,
632 buff_addr[RKISP1_PLANE_Y],
633 cap->config->mi.y_base_ad_init);
634 rkisp1_write(cap->rkisp1,
635 buff_addr[RKISP1_PLANE_CB],
636 cap->config->mi.cb_base_ad_init);
637 rkisp1_write(cap->rkisp1,
638 buff_addr[RKISP1_PLANE_CR],
639 cap->config->mi.cr_base_ad_init);
640 } else {
641
642
643
644
645 rkisp1_write(cap->rkisp1,
646 cap->buf.dummy.dma_addr,
647 cap->config->mi.y_base_ad_init);
648 rkisp1_write(cap->rkisp1,
649 cap->buf.dummy.dma_addr,
650 cap->config->mi.cb_base_ad_init);
651 rkisp1_write(cap->rkisp1,
652 cap->buf.dummy.dma_addr,
653 cap->config->mi.cr_base_ad_init);
654 }
655
656
657 rkisp1_write(cap->rkisp1, 0, cap->config->mi.y_offs_cnt_init);
658 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cb_offs_cnt_init);
659 rkisp1_write(cap->rkisp1, 0, cap->config->mi.cr_offs_cnt_init);
660}
661
662
663
664
665
666
667static void rkisp1_handle_buffer(struct rkisp1_capture *cap)
668{
669 struct rkisp1_isp *isp = &cap->rkisp1->isp;
670 struct rkisp1_buffer *curr_buf;
671
672 spin_lock(&cap->buf.lock);
673 curr_buf = cap->buf.curr;
674
675 if (curr_buf) {
676 curr_buf->vb.sequence = isp->frame_sequence;
677 curr_buf->vb.vb2_buf.timestamp = ktime_get_boottime_ns();
678 curr_buf->vb.field = V4L2_FIELD_NONE;
679 vb2_buffer_done(&curr_buf->vb.vb2_buf, VB2_BUF_STATE_DONE);
680 } else {
681 cap->rkisp1->debug.frame_drop[cap->id]++;
682 }
683
684 rkisp1_set_next_buf(cap);
685 spin_unlock(&cap->buf.lock);
686}
687
688void rkisp1_capture_isr(struct rkisp1_device *rkisp1)
689{
690 unsigned int i;
691 u32 status;
692
693 status = rkisp1_read(rkisp1, RKISP1_CIF_MI_MIS);
694 rkisp1_write(rkisp1, status, RKISP1_CIF_MI_ICR);
695
696 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); ++i) {
697 struct rkisp1_capture *cap = &rkisp1->capture_devs[i];
698
699 if (!(status & RKISP1_CIF_MI_FRAME(cap)))
700 continue;
701 if (!cap->is_stopping) {
702 rkisp1_handle_buffer(cap);
703 continue;
704 }
705
706
707
708
709
710
711
712
713 if (!cap->ops->is_stopped(cap)) {
714 cap->ops->stop(cap);
715 continue;
716 }
717 cap->is_stopping = false;
718 cap->is_streaming = false;
719 wake_up(&cap->done);
720 }
721}
722
723
724
725
726
727static int rkisp1_vb2_queue_setup(struct vb2_queue *queue,
728 unsigned int *num_buffers,
729 unsigned int *num_planes,
730 unsigned int sizes[],
731 struct device *alloc_devs[])
732{
733 struct rkisp1_capture *cap = queue->drv_priv;
734 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
735 unsigned int i;
736
737 if (*num_planes) {
738 if (*num_planes != pixm->num_planes)
739 return -EINVAL;
740
741 for (i = 0; i < pixm->num_planes; i++)
742 if (sizes[i] < pixm->plane_fmt[i].sizeimage)
743 return -EINVAL;
744 } else {
745 *num_planes = pixm->num_planes;
746 for (i = 0; i < pixm->num_planes; i++)
747 sizes[i] = pixm->plane_fmt[i].sizeimage;
748 }
749
750 return 0;
751}
752
753static int rkisp1_vb2_buf_init(struct vb2_buffer *vb)
754{
755 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
756 struct rkisp1_buffer *ispbuf =
757 container_of(vbuf, struct rkisp1_buffer, vb);
758 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
759 const struct v4l2_pix_format_mplane *pixm = &cap->pix.fmt;
760 unsigned int i;
761
762 memset(ispbuf->buff_addr, 0, sizeof(ispbuf->buff_addr));
763 for (i = 0; i < pixm->num_planes; i++)
764 ispbuf->buff_addr[i] = vb2_dma_contig_plane_dma_addr(vb, i);
765
766
767 if (pixm->num_planes == 1) {
768 ispbuf->buff_addr[RKISP1_PLANE_CB] =
769 ispbuf->buff_addr[RKISP1_PLANE_Y] +
770 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_Y);
771 ispbuf->buff_addr[RKISP1_PLANE_CR] =
772 ispbuf->buff_addr[RKISP1_PLANE_CB] +
773 rkisp1_pixfmt_comp_size(pixm, RKISP1_PLANE_CB);
774 }
775
776
777
778
779
780 if (cap->pix.info->comp_planes == 3 && cap->pix.cfg->uv_swap)
781 swap(ispbuf->buff_addr[RKISP1_PLANE_CR],
782 ispbuf->buff_addr[RKISP1_PLANE_CB]);
783 return 0;
784}
785
786static void rkisp1_vb2_buf_queue(struct vb2_buffer *vb)
787{
788 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
789 struct rkisp1_buffer *ispbuf =
790 container_of(vbuf, struct rkisp1_buffer, vb);
791 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
792
793 spin_lock_irq(&cap->buf.lock);
794 list_add_tail(&ispbuf->queue, &cap->buf.queue);
795 spin_unlock_irq(&cap->buf.lock);
796}
797
798static int rkisp1_vb2_buf_prepare(struct vb2_buffer *vb)
799{
800 struct rkisp1_capture *cap = vb->vb2_queue->drv_priv;
801 unsigned int i;
802
803 for (i = 0; i < cap->pix.fmt.num_planes; i++) {
804 unsigned long size = cap->pix.fmt.plane_fmt[i].sizeimage;
805
806 if (vb2_plane_size(vb, i) < size) {
807 dev_err(cap->rkisp1->dev,
808 "User buffer too small (%ld < %ld)\n",
809 vb2_plane_size(vb, i), size);
810 return -EINVAL;
811 }
812 vb2_set_plane_payload(vb, i, size);
813 }
814
815 return 0;
816}
817
818static void rkisp1_return_all_buffers(struct rkisp1_capture *cap,
819 enum vb2_buffer_state state)
820{
821 struct rkisp1_buffer *buf;
822
823 spin_lock_irq(&cap->buf.lock);
824 if (cap->buf.curr) {
825 vb2_buffer_done(&cap->buf.curr->vb.vb2_buf, state);
826 cap->buf.curr = NULL;
827 }
828 if (cap->buf.next) {
829 vb2_buffer_done(&cap->buf.next->vb.vb2_buf, state);
830 cap->buf.next = NULL;
831 }
832 while (!list_empty(&cap->buf.queue)) {
833 buf = list_first_entry(&cap->buf.queue,
834 struct rkisp1_buffer, queue);
835 list_del(&buf->queue);
836 vb2_buffer_done(&buf->vb.vb2_buf, state);
837 }
838 spin_unlock_irq(&cap->buf.lock);
839}
840
841
842
843
844
845
846
847static void rkisp1_cap_stream_enable(struct rkisp1_capture *cap)
848{
849 struct rkisp1_device *rkisp1 = cap->rkisp1;
850 struct rkisp1_capture *other = &rkisp1->capture_devs[cap->id ^ 1];
851
852 cap->ops->set_data_path(cap);
853 cap->ops->config(cap);
854
855
856 spin_lock_irq(&cap->buf.lock);
857 rkisp1_set_next_buf(cap);
858 cap->ops->enable(cap);
859
860
861
862
863
864
865
866
867
868 if (!other->is_streaming) {
869
870 rkisp1_write(rkisp1,
871 RKISP1_CIF_MI_INIT_SOFT_UPD, RKISP1_CIF_MI_INIT);
872 rkisp1_set_next_buf(cap);
873 }
874 spin_unlock_irq(&cap->buf.lock);
875 cap->is_streaming = true;
876}
877
878static void rkisp1_cap_stream_disable(struct rkisp1_capture *cap)
879{
880 int ret;
881
882
883 cap->is_stopping = true;
884 ret = wait_event_timeout(cap->done,
885 !cap->is_streaming,
886 msecs_to_jiffies(1000));
887 if (!ret) {
888 cap->rkisp1->debug.stop_timeout[cap->id]++;
889 cap->ops->stop(cap);
890 cap->is_stopping = false;
891 cap->is_streaming = false;
892 }
893}
894
895
896
897
898
899
900
901
902static void rkisp1_pipeline_stream_disable(struct rkisp1_capture *cap)
903 __must_hold(&cap->rkisp1->stream_lock)
904{
905 struct rkisp1_device *rkisp1 = cap->rkisp1;
906
907 rkisp1_cap_stream_disable(cap);
908
909
910
911
912
913 if (rkisp1->pipe.streaming_count < 2) {
914 v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream,
915 false);
916 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false);
917 }
918
919 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream,
920 false);
921}
922
923
924
925
926
927
928
929static int rkisp1_pipeline_stream_enable(struct rkisp1_capture *cap)
930 __must_hold(&cap->rkisp1->stream_lock)
931{
932 struct rkisp1_device *rkisp1 = cap->rkisp1;
933 int ret;
934
935 rkisp1_cap_stream_enable(cap);
936
937 ret = v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video,
938 s_stream, true);
939 if (ret)
940 goto err_disable_cap;
941
942
943
944
945
946 if (rkisp1->pipe.streaming_count > 1)
947 return 0;
948
949 ret = v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, true);
950 if (ret)
951 goto err_disable_rsz;
952
953 ret = v4l2_subdev_call(rkisp1->active_sensor->sd, video, s_stream,
954 true);
955 if (ret)
956 goto err_disable_isp;
957
958 return 0;
959
960err_disable_isp:
961 v4l2_subdev_call(&rkisp1->isp.sd, video, s_stream, false);
962err_disable_rsz:
963 v4l2_subdev_call(&rkisp1->resizer_devs[cap->id].sd, video, s_stream,
964 false);
965err_disable_cap:
966 rkisp1_cap_stream_disable(cap);
967
968 return ret;
969}
970
971static void rkisp1_vb2_stop_streaming(struct vb2_queue *queue)
972{
973 struct rkisp1_capture *cap = queue->drv_priv;
974 struct rkisp1_vdev_node *node = &cap->vnode;
975 struct rkisp1_device *rkisp1 = cap->rkisp1;
976 int ret;
977
978 mutex_lock(&cap->rkisp1->stream_lock);
979
980 rkisp1_pipeline_stream_disable(cap);
981
982 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_ERROR);
983
984 v4l2_pipeline_pm_put(&node->vdev.entity);
985 ret = pm_runtime_put(rkisp1->dev);
986 if (ret < 0)
987 dev_err(rkisp1->dev, "power down failed error:%d\n", ret);
988
989 rkisp1_dummy_buf_destroy(cap);
990
991 media_pipeline_stop(&node->vdev.entity);
992
993 mutex_unlock(&cap->rkisp1->stream_lock);
994}
995
996static int
997rkisp1_vb2_start_streaming(struct vb2_queue *queue, unsigned int count)
998{
999 struct rkisp1_capture *cap = queue->drv_priv;
1000 struct media_entity *entity = &cap->vnode.vdev.entity;
1001 int ret;
1002
1003 mutex_lock(&cap->rkisp1->stream_lock);
1004
1005 ret = media_pipeline_start(entity, &cap->rkisp1->pipe);
1006 if (ret) {
1007 dev_err(cap->rkisp1->dev, "start pipeline failed %d\n", ret);
1008 goto err_ret_buffers;
1009 }
1010
1011 ret = rkisp1_dummy_buf_create(cap);
1012 if (ret)
1013 goto err_pipeline_stop;
1014
1015 ret = pm_runtime_resume_and_get(cap->rkisp1->dev);
1016 if (ret < 0) {
1017 dev_err(cap->rkisp1->dev, "power up failed %d\n", ret);
1018 goto err_destroy_dummy;
1019 }
1020 ret = v4l2_pipeline_pm_get(entity);
1021 if (ret) {
1022 dev_err(cap->rkisp1->dev, "open cif pipeline failed %d\n", ret);
1023 goto err_pipe_pm_put;
1024 }
1025
1026 ret = rkisp1_pipeline_stream_enable(cap);
1027 if (ret)
1028 goto err_v4l2_pm_put;
1029
1030 mutex_unlock(&cap->rkisp1->stream_lock);
1031
1032 return 0;
1033
1034err_v4l2_pm_put:
1035 v4l2_pipeline_pm_put(entity);
1036err_pipe_pm_put:
1037 pm_runtime_put(cap->rkisp1->dev);
1038err_destroy_dummy:
1039 rkisp1_dummy_buf_destroy(cap);
1040err_pipeline_stop:
1041 media_pipeline_stop(entity);
1042err_ret_buffers:
1043 rkisp1_return_all_buffers(cap, VB2_BUF_STATE_QUEUED);
1044 mutex_unlock(&cap->rkisp1->stream_lock);
1045
1046 return ret;
1047}
1048
1049static const struct vb2_ops rkisp1_vb2_ops = {
1050 .queue_setup = rkisp1_vb2_queue_setup,
1051 .buf_init = rkisp1_vb2_buf_init,
1052 .buf_queue = rkisp1_vb2_buf_queue,
1053 .buf_prepare = rkisp1_vb2_buf_prepare,
1054 .wait_prepare = vb2_ops_wait_prepare,
1055 .wait_finish = vb2_ops_wait_finish,
1056 .stop_streaming = rkisp1_vb2_stop_streaming,
1057 .start_streaming = rkisp1_vb2_start_streaming,
1058};
1059
1060
1061
1062
1063
1064static const struct v4l2_format_info *
1065rkisp1_fill_pixfmt(struct v4l2_pix_format_mplane *pixm,
1066 enum rkisp1_stream_id id)
1067{
1068 struct v4l2_plane_pix_format *plane_y = &pixm->plane_fmt[0];
1069 const struct v4l2_format_info *info;
1070 unsigned int i;
1071 u32 stride;
1072
1073 memset(pixm->plane_fmt, 0, sizeof(pixm->plane_fmt));
1074 info = v4l2_format_info(pixm->pixelformat);
1075 pixm->num_planes = info->mem_planes;
1076 stride = info->bpp[0] * pixm->width;
1077
1078 if (id == RKISP1_MAINPATH || plane_y->bytesperline < stride)
1079 plane_y->bytesperline = stride;
1080 plane_y->sizeimage = plane_y->bytesperline * pixm->height;
1081
1082
1083 stride = DIV_ROUND_UP(plane_y->bytesperline, info->bpp[0]);
1084
1085 for (i = 1; i < info->comp_planes; i++) {
1086 struct v4l2_plane_pix_format *plane = &pixm->plane_fmt[i];
1087
1088
1089 plane->bytesperline = DIV_ROUND_UP(stride, info->hdiv) *
1090 info->bpp[i];
1091 plane->sizeimage = plane->bytesperline *
1092 DIV_ROUND_UP(pixm->height, info->vdiv);
1093 }
1094
1095
1096
1097
1098
1099
1100
1101 if (info->mem_planes == 1)
1102 for (i = 1; i < info->comp_planes; i++)
1103 plane_y->sizeimage += pixm->plane_fmt[i].sizeimage;
1104
1105 return info;
1106}
1107
1108static const struct rkisp1_capture_fmt_cfg *
1109rkisp1_find_fmt_cfg(const struct rkisp1_capture *cap, const u32 pixelfmt)
1110{
1111 unsigned int i;
1112
1113 for (i = 0; i < cap->config->fmt_size; i++) {
1114 if (cap->config->fmts[i].fourcc == pixelfmt)
1115 return &cap->config->fmts[i];
1116 }
1117 return NULL;
1118}
1119
1120static void rkisp1_try_fmt(const struct rkisp1_capture *cap,
1121 struct v4l2_pix_format_mplane *pixm,
1122 const struct rkisp1_capture_fmt_cfg **fmt_cfg,
1123 const struct v4l2_format_info **fmt_info)
1124{
1125 const struct rkisp1_capture_config *config = cap->config;
1126 const struct rkisp1_capture_fmt_cfg *fmt;
1127 const struct v4l2_format_info *info;
1128 const unsigned int max_widths[] = { RKISP1_RSZ_MP_SRC_MAX_WIDTH,
1129 RKISP1_RSZ_SP_SRC_MAX_WIDTH };
1130 const unsigned int max_heights[] = { RKISP1_RSZ_MP_SRC_MAX_HEIGHT,
1131 RKISP1_RSZ_SP_SRC_MAX_HEIGHT};
1132
1133 fmt = rkisp1_find_fmt_cfg(cap, pixm->pixelformat);
1134 if (!fmt) {
1135 fmt = config->fmts;
1136 pixm->pixelformat = fmt->fourcc;
1137 }
1138
1139 pixm->width = clamp_t(u32, pixm->width,
1140 RKISP1_RSZ_SRC_MIN_WIDTH, max_widths[cap->id]);
1141 pixm->height = clamp_t(u32, pixm->height,
1142 RKISP1_RSZ_SRC_MIN_HEIGHT, max_heights[cap->id]);
1143
1144 pixm->field = V4L2_FIELD_NONE;
1145 pixm->colorspace = V4L2_COLORSPACE_DEFAULT;
1146 pixm->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
1147 pixm->quantization = V4L2_QUANTIZATION_DEFAULT;
1148
1149 info = rkisp1_fill_pixfmt(pixm, cap->id);
1150
1151 if (fmt_cfg)
1152 *fmt_cfg = fmt;
1153 if (fmt_info)
1154 *fmt_info = info;
1155}
1156
1157static void rkisp1_set_fmt(struct rkisp1_capture *cap,
1158 struct v4l2_pix_format_mplane *pixm)
1159{
1160 rkisp1_try_fmt(cap, pixm, &cap->pix.cfg, &cap->pix.info);
1161 cap->pix.fmt = *pixm;
1162
1163
1164 if (cap->id == RKISP1_SELFPATH)
1165 cap->sp_y_stride = pixm->plane_fmt[0].bytesperline /
1166 cap->pix.info->bpp[0];
1167}
1168
1169static int rkisp1_try_fmt_vid_cap_mplane(struct file *file, void *fh,
1170 struct v4l2_format *f)
1171{
1172 struct rkisp1_capture *cap = video_drvdata(file);
1173
1174 rkisp1_try_fmt(cap, &f->fmt.pix_mp, NULL, NULL);
1175
1176 return 0;
1177}
1178
1179static int rkisp1_enum_fmt_vid_cap_mplane(struct file *file, void *priv,
1180 struct v4l2_fmtdesc *f)
1181{
1182 struct rkisp1_capture *cap = video_drvdata(file);
1183 const struct rkisp1_capture_fmt_cfg *fmt = NULL;
1184 unsigned int i, n = 0;
1185
1186 if (!f->mbus_code) {
1187 if (f->index >= cap->config->fmt_size)
1188 return -EINVAL;
1189
1190 fmt = &cap->config->fmts[f->index];
1191 f->pixelformat = fmt->fourcc;
1192 return 0;
1193 }
1194
1195 for (i = 0; i < cap->config->fmt_size; i++) {
1196 if (cap->config->fmts[i].mbus != f->mbus_code)
1197 continue;
1198
1199 if (n++ == f->index) {
1200 f->pixelformat = cap->config->fmts[i].fourcc;
1201 return 0;
1202 }
1203 }
1204 return -EINVAL;
1205}
1206
1207static int rkisp1_s_fmt_vid_cap_mplane(struct file *file,
1208 void *priv, struct v4l2_format *f)
1209{
1210 struct rkisp1_capture *cap = video_drvdata(file);
1211 struct rkisp1_vdev_node *node =
1212 rkisp1_vdev_to_node(&cap->vnode.vdev);
1213
1214 if (vb2_is_busy(&node->buf_queue))
1215 return -EBUSY;
1216
1217 rkisp1_set_fmt(cap, &f->fmt.pix_mp);
1218
1219 return 0;
1220}
1221
1222static int rkisp1_g_fmt_vid_cap_mplane(struct file *file, void *fh,
1223 struct v4l2_format *f)
1224{
1225 struct rkisp1_capture *cap = video_drvdata(file);
1226
1227 f->fmt.pix_mp = cap->pix.fmt;
1228
1229 return 0;
1230}
1231
1232static int
1233rkisp1_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
1234{
1235 struct rkisp1_capture *cap_dev = video_drvdata(file);
1236 struct rkisp1_device *rkisp1 = cap_dev->rkisp1;
1237
1238 strscpy(cap->driver, rkisp1->dev->driver->name, sizeof(cap->driver));
1239 strscpy(cap->card, rkisp1->dev->driver->name, sizeof(cap->card));
1240 strscpy(cap->bus_info, RKISP1_BUS_INFO, sizeof(cap->bus_info));
1241
1242 return 0;
1243}
1244
1245static const struct v4l2_ioctl_ops rkisp1_v4l2_ioctl_ops = {
1246 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1247 .vidioc_querybuf = vb2_ioctl_querybuf,
1248 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1249 .vidioc_qbuf = vb2_ioctl_qbuf,
1250 .vidioc_expbuf = vb2_ioctl_expbuf,
1251 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1252 .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
1253 .vidioc_streamon = vb2_ioctl_streamon,
1254 .vidioc_streamoff = vb2_ioctl_streamoff,
1255 .vidioc_try_fmt_vid_cap_mplane = rkisp1_try_fmt_vid_cap_mplane,
1256 .vidioc_s_fmt_vid_cap_mplane = rkisp1_s_fmt_vid_cap_mplane,
1257 .vidioc_g_fmt_vid_cap_mplane = rkisp1_g_fmt_vid_cap_mplane,
1258 .vidioc_enum_fmt_vid_cap = rkisp1_enum_fmt_vid_cap_mplane,
1259 .vidioc_querycap = rkisp1_querycap,
1260 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1261 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1262};
1263
1264static int rkisp1_capture_link_validate(struct media_link *link)
1265{
1266 struct video_device *vdev =
1267 media_entity_to_video_device(link->sink->entity);
1268 struct v4l2_subdev *sd =
1269 media_entity_to_v4l2_subdev(link->source->entity);
1270 struct rkisp1_capture *cap = video_get_drvdata(vdev);
1271 const struct rkisp1_capture_fmt_cfg *fmt =
1272 rkisp1_find_fmt_cfg(cap, cap->pix.fmt.pixelformat);
1273 struct v4l2_subdev_format sd_fmt;
1274 int ret;
1275
1276 sd_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
1277 sd_fmt.pad = link->source->index;
1278 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &sd_fmt);
1279 if (ret)
1280 return ret;
1281
1282 if (sd_fmt.format.height != cap->pix.fmt.height ||
1283 sd_fmt.format.width != cap->pix.fmt.width ||
1284 sd_fmt.format.code != fmt->mbus)
1285 return -EPIPE;
1286
1287 return 0;
1288}
1289
1290
1291
1292
1293
1294static const struct media_entity_operations rkisp1_media_ops = {
1295 .link_validate = rkisp1_capture_link_validate,
1296};
1297
1298static const struct v4l2_file_operations rkisp1_fops = {
1299 .open = v4l2_fh_open,
1300 .release = vb2_fop_release,
1301 .unlocked_ioctl = video_ioctl2,
1302 .poll = vb2_fop_poll,
1303 .mmap = vb2_fop_mmap,
1304};
1305
1306static void rkisp1_unregister_capture(struct rkisp1_capture *cap)
1307{
1308 media_entity_cleanup(&cap->vnode.vdev.entity);
1309 vb2_video_unregister_device(&cap->vnode.vdev);
1310}
1311
1312void rkisp1_capture_devs_unregister(struct rkisp1_device *rkisp1)
1313{
1314 struct rkisp1_capture *mp = &rkisp1->capture_devs[RKISP1_MAINPATH];
1315 struct rkisp1_capture *sp = &rkisp1->capture_devs[RKISP1_SELFPATH];
1316
1317 rkisp1_unregister_capture(mp);
1318 rkisp1_unregister_capture(sp);
1319}
1320
1321static int rkisp1_register_capture(struct rkisp1_capture *cap)
1322{
1323 const char * const dev_names[] = {RKISP1_MP_DEV_NAME,
1324 RKISP1_SP_DEV_NAME};
1325 struct v4l2_device *v4l2_dev = &cap->rkisp1->v4l2_dev;
1326 struct video_device *vdev = &cap->vnode.vdev;
1327 struct rkisp1_vdev_node *node;
1328 struct vb2_queue *q;
1329 int ret;
1330
1331 strscpy(vdev->name, dev_names[cap->id], sizeof(vdev->name));
1332 node = rkisp1_vdev_to_node(vdev);
1333 mutex_init(&node->vlock);
1334
1335 vdev->ioctl_ops = &rkisp1_v4l2_ioctl_ops;
1336 vdev->release = video_device_release_empty;
1337 vdev->fops = &rkisp1_fops;
1338 vdev->minor = -1;
1339 vdev->v4l2_dev = v4l2_dev;
1340 vdev->lock = &node->vlock;
1341 vdev->device_caps = V4L2_CAP_VIDEO_CAPTURE_MPLANE |
1342 V4L2_CAP_STREAMING | V4L2_CAP_IO_MC;
1343 vdev->entity.ops = &rkisp1_media_ops;
1344 video_set_drvdata(vdev, cap);
1345 vdev->vfl_dir = VFL_DIR_RX;
1346 node->pad.flags = MEDIA_PAD_FL_SINK;
1347
1348 q = &node->buf_queue;
1349 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1350 q->io_modes = VB2_MMAP | VB2_DMABUF;
1351 q->drv_priv = cap;
1352 q->ops = &rkisp1_vb2_ops;
1353 q->mem_ops = &vb2_dma_contig_memops;
1354 q->buf_struct_size = sizeof(struct rkisp1_buffer);
1355 q->min_buffers_needed = RKISP1_MIN_BUFFERS_NEEDED;
1356 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1357 q->lock = &node->vlock;
1358 q->dev = cap->rkisp1->dev;
1359 ret = vb2_queue_init(q);
1360 if (ret) {
1361 dev_err(cap->rkisp1->dev,
1362 "vb2 queue init failed (err=%d)\n", ret);
1363 return ret;
1364 }
1365
1366 vdev->queue = q;
1367
1368 ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
1369 if (ret) {
1370 dev_err(cap->rkisp1->dev,
1371 "failed to register %s, ret=%d\n", vdev->name, ret);
1372 return ret;
1373 }
1374 v4l2_info(v4l2_dev, "registered %s as /dev/video%d\n", vdev->name,
1375 vdev->num);
1376
1377 ret = media_entity_pads_init(&vdev->entity, 1, &node->pad);
1378 if (ret) {
1379 video_unregister_device(vdev);
1380 return ret;
1381 }
1382
1383 return 0;
1384}
1385
1386static void
1387rkisp1_capture_init(struct rkisp1_device *rkisp1, enum rkisp1_stream_id id)
1388{
1389 struct rkisp1_capture *cap = &rkisp1->capture_devs[id];
1390 struct v4l2_pix_format_mplane pixm;
1391
1392 memset(cap, 0, sizeof(*cap));
1393 cap->id = id;
1394 cap->rkisp1 = rkisp1;
1395
1396 INIT_LIST_HEAD(&cap->buf.queue);
1397 init_waitqueue_head(&cap->done);
1398 spin_lock_init(&cap->buf.lock);
1399 if (cap->id == RKISP1_SELFPATH) {
1400 cap->ops = &rkisp1_capture_ops_sp;
1401 cap->config = &rkisp1_capture_config_sp;
1402 } else {
1403 cap->ops = &rkisp1_capture_ops_mp;
1404 cap->config = &rkisp1_capture_config_mp;
1405 }
1406
1407 cap->is_streaming = false;
1408
1409 memset(&pixm, 0, sizeof(pixm));
1410 pixm.pixelformat = V4L2_PIX_FMT_YUYV;
1411 pixm.width = RKISP1_DEFAULT_WIDTH;
1412 pixm.height = RKISP1_DEFAULT_HEIGHT;
1413 rkisp1_set_fmt(cap, &pixm);
1414}
1415
1416int rkisp1_capture_devs_register(struct rkisp1_device *rkisp1)
1417{
1418 struct rkisp1_capture *cap;
1419 unsigned int i, j;
1420 int ret;
1421
1422 for (i = 0; i < ARRAY_SIZE(rkisp1->capture_devs); i++) {
1423 rkisp1_capture_init(rkisp1, i);
1424 cap = &rkisp1->capture_devs[i];
1425 cap->rkisp1 = rkisp1;
1426 ret = rkisp1_register_capture(cap);
1427 if (ret)
1428 goto err_unreg_capture_devs;
1429 }
1430
1431 return 0;
1432
1433err_unreg_capture_devs:
1434 for (j = 0; j < i; j++) {
1435 cap = &rkisp1->capture_devs[j];
1436 rkisp1_unregister_capture(cap);
1437 }
1438
1439 return ret;
1440}
1441
