1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * c8sectpfe-core.h - C8SECTPFE STi DVB driver 4 * 5 * Copyright (c) STMicroelectronics 2015 6 * 7 * Author:Peter Bennett <peter.bennett@st.com> 8 * Peter Griffin <peter.griffin@linaro.org> 9 * 10 */ 11#ifndef _C8SECTPFE_CORE_H_ 12#define _C8SECTPFE_CORE_H_ 13 14#define C8SECTPFEI_MAXCHANNEL 16 15#define C8SECTPFEI_MAXADAPTER 3 16 17#define C8SECTPFE_MAX_TSIN_CHAN 8 18 19struct channel_info { 20 21 int tsin_id; 22 bool invert_ts_clk; 23 bool serial_not_parallel; 24 bool async_not_sync; 25 int i2c; 26 int dvb_card; 27 28 int rst_gpio; 29 30 struct i2c_adapter *i2c_adapter; 31 struct i2c_adapter *tuner_i2c; 32 struct i2c_adapter *lnb_i2c; 33 struct i2c_client *i2c_client; 34 struct dvb_frontend *frontend; 35 36 struct pinctrl_state *pstate; 37 38 int demux_mapping; 39 int active; 40 41 void *back_buffer_start; 42 void *back_buffer_aligned; 43 dma_addr_t back_buffer_busaddr; 44 45 void *pid_buffer_start; 46 void *pid_buffer_aligned; 47 dma_addr_t pid_buffer_busaddr; 48 49 unsigned long fifo; 50 51 struct completion idle_completion; 52 struct tasklet_struct tsklet; 53 54 struct c8sectpfei *fei; 55 void __iomem *irec; 56 57}; 58 59struct c8sectpfe_hw { 60 int num_ib; 61 int num_mib; 62 int num_swts; 63 int num_tsout; 64 int num_ccsc; 65 int num_ram; 66 int num_tp; 67}; 68 69struct c8sectpfei { 70 71 struct device *dev; 72 struct pinctrl *pinctrl; 73 74 struct dentry *root; 75 struct debugfs_regset32 *regset; 76 struct completion fw_ack; 77 atomic_t fw_loaded; 78 79 int tsin_count; 80 81 struct c8sectpfe_hw hw_stats; 82 83 struct c8sectpfe *c8sectpfe[C8SECTPFEI_MAXADAPTER]; 84 85 int mapping[C8SECTPFEI_MAXCHANNEL]; 86 87 struct mutex lock; 88 89 struct timer_list timer; /* timer interrupts for outputs */ 90 91 void __iomem *io; 92 void __iomem *sram; 93 94 unsigned long sram_size; 95 96 struct channel_info *channel_data[C8SECTPFE_MAX_TSIN_CHAN]; 97 98 struct clk *c8sectpfeclk; 99 int nima_rst_gpio; 100 int nimb_rst_gpio; 101 102 int idle_irq; 103 int error_irq; 104 105 int global_feed_count; 106}; 107 108/* C8SECTPFE SYS Regs list */ 109 110#define SYS_INPUT_ERR_STATUS 0x0 111#define SYS_OTHER_ERR_STATUS 0x8 112#define SYS_INPUT_ERR_MASK 0x10 113#define SYS_OTHER_ERR_MASK 0x18 114#define SYS_DMA_ROUTE 0x20 115#define SYS_INPUT_CLKEN 0x30 116#define IBENABLE_MASK 0x7F 117 118#define SYS_OTHER_CLKEN 0x38 119#define TSDMAENABLE BIT(1) 120#define MEMDMAENABLE BIT(0) 121 122#define SYS_CFG_NUM_IB 0x200 123#define SYS_CFG_NUM_MIB 0x204 124#define SYS_CFG_NUM_SWTS 0x208 125#define SYS_CFG_NUM_TSOUT 0x20C 126#define SYS_CFG_NUM_CCSC 0x210 127#define SYS_CFG_NUM_RAM 0x214 128#define SYS_CFG_NUM_TP 0x218 129 130/* Input Block Regs */ 131 132#define C8SECTPFE_INPUTBLK_OFFSET 0x1000 133#define C8SECTPFE_CHANNEL_OFFSET(x) ((x*0x40) + C8SECTPFE_INPUTBLK_OFFSET) 134 135#define C8SECTPFE_IB_IP_FMT_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x00) 136#define C8SECTPFE_IGNORE_ERR_AT_SOP BIT(7) 137#define C8SECTPFE_IGNORE_ERR_IN_PKT BIT(6) 138#define C8SECTPFE_IGNORE_ERR_IN_BYTE BIT(5) 139#define C8SECTPFE_INVERT_TSCLK BIT(4) 140#define C8SECTPFE_ALIGN_BYTE_SOP BIT(3) 141#define C8SECTPFE_ASYNC_NOT_SYNC BIT(2) 142#define C8SECTPFE_BYTE_ENDIANNESS_MSB BIT(1) 143#define C8SECTPFE_SERIAL_NOT_PARALLEL BIT(0) 144 145#define C8SECTPFE_IB_SYNCLCKDRP_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x04) 146#define C8SECTPFE_SYNC(x) (x & 0xf) 147#define C8SECTPFE_DROP(x) ((x<<4) & 0xf) 148#define C8SECTPFE_TOKEN(x) ((x<<8) & 0xff00) 149#define C8SECTPFE_SLDENDIANNESS BIT(16) 150 151#define C8SECTPFE_IB_TAGBYTES_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x08) 152#define C8SECTPFE_TAG_HEADER(x) (x << 16) 153#define C8SECTPFE_TAG_COUNTER(x) ((x<<1) & 0x7fff) 154#define C8SECTPFE_TAG_ENABLE BIT(0) 155 156#define C8SECTPFE_IB_PID_SET(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x0C) 157#define C8SECTPFE_PID_OFFSET(x) (x & 0x3f) 158#define C8SECTPFE_PID_NUMBITS(x) ((x << 6) & 0xfff) 159#define C8SECTPFE_PID_ENABLE BIT(31) 160 161#define C8SECTPFE_IB_PKT_LEN(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x10) 162 163#define C8SECTPFE_IB_BUFF_STRT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x14) 164#define C8SECTPFE_IB_BUFF_END(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x18) 165#define C8SECTPFE_IB_READ_PNT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x1C) 166#define C8SECTPFE_IB_WRT_PNT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x20) 167 168#define C8SECTPFE_IB_PRI_THRLD(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x24) 169#define C8SECTPFE_PRI_VALUE(x) (x & 0x7fffff) 170#define C8SECTPFE_PRI_LOWPRI(x) ((x & 0xf) << 24) 171#define C8SECTPFE_PRI_HIGHPRI(x) ((x & 0xf) << 28) 172 173#define C8SECTPFE_IB_STAT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x28) 174#define C8SECTPFE_STAT_FIFO_OVERFLOW(x) (x & 0x1) 175#define C8SECTPFE_STAT_BUFFER_OVERFLOW(x) (x & 0x2) 176#define C8SECTPFE_STAT_OUTOFORDERRP(x) (x & 0x4) 177#define C8SECTPFE_STAT_PID_OVERFLOW(x) (x & 0x8) 178#define C8SECTPFE_STAT_PKT_OVERFLOW(x) (x & 0x10) 179#define C8SECTPFE_STAT_ERROR_PACKETS(x) ((x >> 8) & 0xf) 180#define C8SECTPFE_STAT_SHORT_PACKETS(x) ((x >> 12) & 0xf) 181 182#define C8SECTPFE_IB_MASK(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x2C) 183#define C8SECTPFE_MASK_FIFO_OVERFLOW BIT(0) 184#define C8SECTPFE_MASK_BUFFER_OVERFLOW BIT(1) 185#define C8SECTPFE_MASK_OUTOFORDERRP(x) BIT(2) 186#define C8SECTPFE_MASK_PID_OVERFLOW(x) BIT(3) 187#define C8SECTPFE_MASK_PKT_OVERFLOW(x) BIT(4) 188#define C8SECTPFE_MASK_ERROR_PACKETS(x) ((x & 0xf) << 8) 189#define C8SECTPFE_MASK_SHORT_PACKETS(x) ((x & 0xf) >> 12) 190 191#define C8SECTPFE_IB_SYS(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x30) 192#define C8SECTPFE_SYS_RESET BIT(1) 193#define C8SECTPFE_SYS_ENABLE BIT(0) 194 195/* 196 * Pointer record data structure required for each input block 197 * see Table 82 on page 167 of functional specification. 198 */ 199 200#define DMA_PRDS_MEMBASE 0x0 /* Internal sram base address */ 201#define DMA_PRDS_MEMTOP 0x4 /* Internal sram top address */ 202 203/* 204 * TS packet size, including tag bytes added by input block, 205 * rounded up to the next multiple of 8 bytes. The packet size, 206 * including any tagging bytes and rounded up to the nearest 207 * multiple of 8 bytes must be less than 255 bytes. 208 */ 209#define DMA_PRDS_PKTSIZE 0x8 210#define DMA_PRDS_TPENABLE 0xc 211 212#define TP0_OFFSET 0x10 213#define DMA_PRDS_BUSBASE_TP(x) ((0x10*x) + TP0_OFFSET) 214#define DMA_PRDS_BUSTOP_TP(x) ((0x10*x) + TP0_OFFSET + 0x4) 215#define DMA_PRDS_BUSWP_TP(x) ((0x10*x) + TP0_OFFSET + 0x8) 216#define DMA_PRDS_BUSRP_TP(x) ((0x10*x) + TP0_OFFSET + 0xc) 217 218#define DMA_PRDS_SIZE (0x20) 219 220#define DMA_MEMDMA_OFFSET 0x4000 221#define DMA_IMEM_OFFSET 0x0 222#define DMA_DMEM_OFFSET 0x4000 223#define DMA_CPU 0x8000 224#define DMA_PER_OFFSET 0xb000 225 226#define DMA_MEMDMA_DMEM (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET) 227#define DMA_MEMDMA_IMEM (DMA_MEMDMA_OFFSET + DMA_IMEM_OFFSET) 228 229/* XP70 Slim core regs */ 230#define DMA_CPU_ID (DMA_MEMDMA_OFFSET + DMA_CPU + 0x0) 231#define DMA_CPU_VCR (DMA_MEMDMA_OFFSET + DMA_CPU + 0x4) 232#define DMA_CPU_RUN (DMA_MEMDMA_OFFSET + DMA_CPU + 0x8) 233#define DMA_CPU_CLOCKGATE (DMA_MEMDMA_OFFSET + DMA_CPU + 0xc) 234#define DMA_CPU_PC (DMA_MEMDMA_OFFSET + DMA_CPU + 0x20) 235 236/* Enable Interrupt for a IB */ 237#define DMA_PER_TPn_DREQ_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd00) 238/* Ack interrupt by setting corresponding bit */ 239#define DMA_PER_TPn_DACK_SET (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd80) 240#define DMA_PER_TPn_DREQ (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe00) 241#define DMA_PER_TPn_DACK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe80) 242#define DMA_PER_DREQ_MODE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf80) 243#define DMA_PER_STBUS_SYNC (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf88) 244#define DMA_PER_STBUS_ACCESS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf8c) 245#define DMA_PER_STBUS_ADDRESS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf90) 246#define DMA_PER_IDLE_INT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfa8) 247#define DMA_PER_PRIORITY (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfac) 248#define DMA_PER_MAX_OPCODE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb0) 249#define DMA_PER_MAX_CHUNK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb4) 250#define DMA_PER_PAGE_SIZE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfbc) 251#define DMA_PER_MBOX_STATUS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc0) 252#define DMA_PER_MBOX_SET (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc8) 253#define DMA_PER_MBOX_CLEAR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd0) 254#define DMA_PER_MBOX_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd8) 255#define DMA_PER_INJECT_PKT_SRC (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe0) 256#define DMA_PER_INJECT_PKT_DEST (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe4) 257#define DMA_PER_INJECT_PKT_ADDR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe8) 258#define DMA_PER_INJECT_PKT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfec) 259#define DMA_PER_PAT_PTR_INIT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff0) 260#define DMA_PER_PAT_PTR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff4) 261#define DMA_PER_SLEEP_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff8) 262#define DMA_PER_SLEEP_COUNTER (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xffc) 263/* #define DMA_RF_CPUREGn DMA_RFBASEADDR n=0 to 15) slim regsa */ 264 265/* The following are from DMA_DMEM_BaseAddress */ 266#define DMA_FIRMWARE_VERSION (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x0) 267#define DMA_PTRREC_BASE (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x4) 268#define DMA_PTRREC_INPUT_OFFSET (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x8) 269#define DMA_ERRREC_BASE (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0xc) 270#define DMA_ERROR_RECORD(n) ((n*4) + DMA_ERRREC_BASE + 0x4) 271#define DMA_IDLE_REQ (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x10) 272#define IDLEREQ BIT(31) 273 274#define DMA_FIRMWARE_CONFIG (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x14) 275 276/* Regs for PID Filter */ 277 278#define PIDF_OFFSET 0x2800 279#define PIDF_BASE(n) ((n*4) + PIDF_OFFSET) 280#define PIDF_LEAK_ENABLE (PIDF_OFFSET + 0x100) 281#define PIDF_LEAK_STATUS (PIDF_OFFSET + 0x108) 282#define PIDF_LEAK_COUNT_RESET (PIDF_OFFSET + 0x110) 283#define PIDF_LEAK_COUNTER (PIDF_OFFSET + 0x114) 284 285#endif /* _C8SECTPFE_CORE_H_ */ 286