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10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/of_device.h>
13#include <linux/platform_device.h>
14#include <linux/mfd/core.h>
15
16#include "mc13xxx.h"
17
18#define MC13XXX_IRQSTAT0 0
19#define MC13XXX_IRQMASK0 1
20#define MC13XXX_IRQSTAT1 3
21#define MC13XXX_IRQMASK1 4
22
23#define MC13XXX_REVISION 7
24#define MC13XXX_REVISION_REVMETAL (0x07 << 0)
25#define MC13XXX_REVISION_REVFULL (0x03 << 3)
26#define MC13XXX_REVISION_ICID (0x07 << 6)
27#define MC13XXX_REVISION_FIN (0x03 << 9)
28#define MC13XXX_REVISION_FAB (0x03 << 11)
29#define MC13XXX_REVISION_ICIDCODE (0x3f << 13)
30
31#define MC34708_REVISION_REVMETAL (0x07 << 0)
32#define MC34708_REVISION_REVFULL (0x07 << 3)
33#define MC34708_REVISION_FIN (0x07 << 6)
34#define MC34708_REVISION_FAB (0x07 << 9)
35
36#define MC13XXX_PWRCTRL 15
37#define MC13XXX_PWRCTRL_WDIRESET (1 << 12)
38
39#define MC13XXX_ADC1 44
40#define MC13XXX_ADC1_ADEN (1 << 0)
41#define MC13XXX_ADC1_RAND (1 << 1)
42#define MC13XXX_ADC1_ADSEL (1 << 3)
43#define MC13XXX_ADC1_ASC (1 << 20)
44#define MC13XXX_ADC1_ADTRIGIGN (1 << 21)
45
46#define MC13XXX_ADC2 45
47
48void mc13xxx_lock(struct mc13xxx *mc13xxx)
49{
50 if (!mutex_trylock(&mc13xxx->lock)) {
51 dev_dbg(mc13xxx->dev, "wait for %s from %ps\n",
52 __func__, __builtin_return_address(0));
53
54 mutex_lock(&mc13xxx->lock);
55 }
56 dev_dbg(mc13xxx->dev, "%s from %ps\n",
57 __func__, __builtin_return_address(0));
58}
59EXPORT_SYMBOL(mc13xxx_lock);
60
61void mc13xxx_unlock(struct mc13xxx *mc13xxx)
62{
63 dev_dbg(mc13xxx->dev, "%s from %ps\n",
64 __func__, __builtin_return_address(0));
65 mutex_unlock(&mc13xxx->lock);
66}
67EXPORT_SYMBOL(mc13xxx_unlock);
68
69int mc13xxx_reg_read(struct mc13xxx *mc13xxx, unsigned int offset, u32 *val)
70{
71 int ret;
72
73 ret = regmap_read(mc13xxx->regmap, offset, val);
74 dev_vdbg(mc13xxx->dev, "[0x%02x] -> 0x%06x\n", offset, *val);
75
76 return ret;
77}
78EXPORT_SYMBOL(mc13xxx_reg_read);
79
80int mc13xxx_reg_write(struct mc13xxx *mc13xxx, unsigned int offset, u32 val)
81{
82 dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x\n", offset, val);
83
84 if (val >= BIT(24))
85 return -EINVAL;
86
87 return regmap_write(mc13xxx->regmap, offset, val);
88}
89EXPORT_SYMBOL(mc13xxx_reg_write);
90
91int mc13xxx_reg_rmw(struct mc13xxx *mc13xxx, unsigned int offset,
92 u32 mask, u32 val)
93{
94 BUG_ON(val & ~mask);
95 dev_vdbg(mc13xxx->dev, "[0x%02x] <- 0x%06x (mask: 0x%06x)\n",
96 offset, val, mask);
97
98 return regmap_update_bits(mc13xxx->regmap, offset, mask, val);
99}
100EXPORT_SYMBOL(mc13xxx_reg_rmw);
101
102int mc13xxx_irq_mask(struct mc13xxx *mc13xxx, int irq)
103{
104 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
105
106 disable_irq_nosync(virq);
107
108 return 0;
109}
110EXPORT_SYMBOL(mc13xxx_irq_mask);
111
112int mc13xxx_irq_unmask(struct mc13xxx *mc13xxx, int irq)
113{
114 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
115
116 enable_irq(virq);
117
118 return 0;
119}
120EXPORT_SYMBOL(mc13xxx_irq_unmask);
121
122int mc13xxx_irq_status(struct mc13xxx *mc13xxx, int irq,
123 int *enabled, int *pending)
124{
125 int ret;
126 unsigned int offmask = irq < 24 ? MC13XXX_IRQMASK0 : MC13XXX_IRQMASK1;
127 unsigned int offstat = irq < 24 ? MC13XXX_IRQSTAT0 : MC13XXX_IRQSTAT1;
128 u32 irqbit = 1 << (irq < 24 ? irq : irq - 24);
129
130 if (irq < 0 || irq >= ARRAY_SIZE(mc13xxx->irqs))
131 return -EINVAL;
132
133 if (enabled) {
134 u32 mask;
135
136 ret = mc13xxx_reg_read(mc13xxx, offmask, &mask);
137 if (ret)
138 return ret;
139
140 *enabled = mask & irqbit;
141 }
142
143 if (pending) {
144 u32 stat;
145
146 ret = mc13xxx_reg_read(mc13xxx, offstat, &stat);
147 if (ret)
148 return ret;
149
150 *pending = stat & irqbit;
151 }
152
153 return 0;
154}
155EXPORT_SYMBOL(mc13xxx_irq_status);
156
157int mc13xxx_irq_request(struct mc13xxx *mc13xxx, int irq,
158 irq_handler_t handler, const char *name, void *dev)
159{
160 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
161
162 return devm_request_threaded_irq(mc13xxx->dev, virq, NULL, handler,
163 IRQF_ONESHOT, name, dev);
164}
165EXPORT_SYMBOL(mc13xxx_irq_request);
166
167int mc13xxx_irq_free(struct mc13xxx *mc13xxx, int irq, void *dev)
168{
169 int virq = regmap_irq_get_virq(mc13xxx->irq_data, irq);
170
171 devm_free_irq(mc13xxx->dev, virq, dev);
172
173 return 0;
174}
175EXPORT_SYMBOL(mc13xxx_irq_free);
176
177#define maskval(reg, mask) (((reg) & (mask)) >> __ffs(mask))
178static void mc13xxx_print_revision(struct mc13xxx *mc13xxx, u32 revision)
179{
180 dev_info(mc13xxx->dev, "%s: rev: %d.%d, "
181 "fin: %d, fab: %d, icid: %d/%d\n",
182 mc13xxx->variant->name,
183 maskval(revision, MC13XXX_REVISION_REVFULL),
184 maskval(revision, MC13XXX_REVISION_REVMETAL),
185 maskval(revision, MC13XXX_REVISION_FIN),
186 maskval(revision, MC13XXX_REVISION_FAB),
187 maskval(revision, MC13XXX_REVISION_ICID),
188 maskval(revision, MC13XXX_REVISION_ICIDCODE));
189}
190
191static void mc34708_print_revision(struct mc13xxx *mc13xxx, u32 revision)
192{
193 dev_info(mc13xxx->dev, "%s: rev %d.%d, fin: %d, fab: %d\n",
194 mc13xxx->variant->name,
195 maskval(revision, MC34708_REVISION_REVFULL),
196 maskval(revision, MC34708_REVISION_REVMETAL),
197 maskval(revision, MC34708_REVISION_FIN),
198 maskval(revision, MC34708_REVISION_FAB));
199}
200
201
202struct mc13xxx_variant mc13xxx_variant_mc13783 = {
203 .name = "mc13783",
204 .print_revision = mc13xxx_print_revision,
205};
206EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13783);
207
208struct mc13xxx_variant mc13xxx_variant_mc13892 = {
209 .name = "mc13892",
210 .print_revision = mc13xxx_print_revision,
211};
212EXPORT_SYMBOL_GPL(mc13xxx_variant_mc13892);
213
214struct mc13xxx_variant mc13xxx_variant_mc34708 = {
215 .name = "mc34708",
216 .print_revision = mc34708_print_revision,
217};
218EXPORT_SYMBOL_GPL(mc13xxx_variant_mc34708);
219
220static const char *mc13xxx_get_chipname(struct mc13xxx *mc13xxx)
221{
222 return mc13xxx->variant->name;
223}
224
225int mc13xxx_get_flags(struct mc13xxx *mc13xxx)
226{
227 return mc13xxx->flags;
228}
229EXPORT_SYMBOL(mc13xxx_get_flags);
230
231#define MC13XXX_ADC1_CHAN0_SHIFT 5
232#define MC13XXX_ADC1_CHAN1_SHIFT 8
233#define MC13783_ADC1_ATO_SHIFT 11
234#define MC13783_ADC1_ATOX (1 << 19)
235
236struct mc13xxx_adcdone_data {
237 struct mc13xxx *mc13xxx;
238 struct completion done;
239};
240
241static irqreturn_t mc13xxx_handler_adcdone(int irq, void *data)
242{
243 struct mc13xxx_adcdone_data *adcdone_data = data;
244
245 complete_all(&adcdone_data->done);
246
247 return IRQ_HANDLED;
248}
249
250#define MC13XXX_ADC_WORKING (1 << 0)
251
252int mc13xxx_adc_do_conversion(struct mc13xxx *mc13xxx, unsigned int mode,
253 unsigned int channel, u8 ato, bool atox,
254 unsigned int *sample)
255{
256 u32 adc0, adc1, old_adc0;
257 int i, ret;
258 struct mc13xxx_adcdone_data adcdone_data = {
259 .mc13xxx = mc13xxx,
260 };
261 init_completion(&adcdone_data.done);
262
263 dev_dbg(mc13xxx->dev, "%s\n", __func__);
264
265 mc13xxx_lock(mc13xxx);
266
267 if (mc13xxx->adcflags & MC13XXX_ADC_WORKING) {
268 ret = -EBUSY;
269 goto out;
270 }
271
272 mc13xxx->adcflags |= MC13XXX_ADC_WORKING;
273
274 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_ADC0, &old_adc0);
275 if (ret)
276 goto out;
277
278 adc0 = MC13XXX_ADC0_ADINC1 | MC13XXX_ADC0_ADINC2 |
279 MC13XXX_ADC0_CHRGRAWDIV;
280 adc1 = MC13XXX_ADC1_ADEN | MC13XXX_ADC1_ADTRIGIGN | MC13XXX_ADC1_ASC;
281
282
283
284
285
286
287
288 if (channel > 7 && channel < 16) {
289 adc1 |= MC13XXX_ADC1_ADSEL;
290 } else if (channel == 16) {
291 adc0 |= MC13XXX_ADC0_ADIN7SEL_UID;
292 channel = 7;
293 } else if (channel == 17) {
294 adc0 |= MC13XXX_ADC0_ADIN7SEL_DIE;
295 channel = 7;
296 }
297
298 switch (mode) {
299 case MC13XXX_ADC_MODE_TS:
300 adc0 |= MC13XXX_ADC0_ADREFEN | MC13XXX_ADC0_TSMOD0 |
301 MC13XXX_ADC0_TSMOD1;
302 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
303 break;
304
305 case MC13XXX_ADC_MODE_SINGLE_CHAN:
306 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
307 adc1 |= (channel & 0x7) << MC13XXX_ADC1_CHAN0_SHIFT;
308 adc1 |= MC13XXX_ADC1_RAND;
309 break;
310
311 case MC13XXX_ADC_MODE_MULT_CHAN:
312 adc0 |= old_adc0 & MC13XXX_ADC0_CONFIG_MASK;
313 adc1 |= 4 << MC13XXX_ADC1_CHAN1_SHIFT;
314 break;
315
316 default:
317 mc13xxx_unlock(mc13xxx);
318 return -EINVAL;
319 }
320
321 adc1 |= ato << MC13783_ADC1_ATO_SHIFT;
322 if (atox)
323 adc1 |= MC13783_ADC1_ATOX;
324
325 dev_dbg(mc13xxx->dev, "%s: request irq\n", __func__);
326 mc13xxx_irq_request(mc13xxx, MC13XXX_IRQ_ADCDONE,
327 mc13xxx_handler_adcdone, __func__, &adcdone_data);
328
329 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, adc0);
330 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC1, adc1);
331
332 mc13xxx_unlock(mc13xxx);
333
334 ret = wait_for_completion_interruptible_timeout(&adcdone_data.done, HZ);
335
336 if (!ret)
337 ret = -ETIMEDOUT;
338
339 mc13xxx_lock(mc13xxx);
340
341 mc13xxx_irq_free(mc13xxx, MC13XXX_IRQ_ADCDONE, &adcdone_data);
342
343 if (ret > 0)
344 for (i = 0; i < 4; ++i) {
345 ret = mc13xxx_reg_read(mc13xxx,
346 MC13XXX_ADC2, &sample[i]);
347 if (ret)
348 break;
349 }
350
351 if (mode == MC13XXX_ADC_MODE_TS)
352
353 mc13xxx_reg_write(mc13xxx, MC13XXX_ADC0, old_adc0);
354
355 mc13xxx->adcflags &= ~MC13XXX_ADC_WORKING;
356out:
357 mc13xxx_unlock(mc13xxx);
358
359 return ret;
360}
361EXPORT_SYMBOL_GPL(mc13xxx_adc_do_conversion);
362
363static int mc13xxx_add_subdevice_pdata(struct mc13xxx *mc13xxx,
364 const char *format, void *pdata, size_t pdata_size)
365{
366 char buf[30];
367 const char *name = mc13xxx_get_chipname(mc13xxx);
368
369 struct mfd_cell cell = {
370 .platform_data = pdata,
371 .pdata_size = pdata_size,
372 };
373
374
375 if (snprintf(buf, sizeof(buf), format, name) > sizeof(buf))
376 return -E2BIG;
377
378 cell.name = kmemdup(buf, strlen(buf) + 1, GFP_KERNEL);
379 if (!cell.name)
380 return -ENOMEM;
381
382 return mfd_add_devices(mc13xxx->dev, -1, &cell, 1, NULL, 0,
383 regmap_irq_get_domain(mc13xxx->irq_data));
384}
385
386static int mc13xxx_add_subdevice(struct mc13xxx *mc13xxx, const char *format)
387{
388 return mc13xxx_add_subdevice_pdata(mc13xxx, format, NULL, 0);
389}
390
391#ifdef CONFIG_OF
392static int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
393{
394 struct device_node *np = mc13xxx->dev->of_node;
395
396 if (!np)
397 return -ENODEV;
398
399 if (of_property_read_bool(np, "fsl,mc13xxx-uses-adc"))
400 mc13xxx->flags |= MC13XXX_USE_ADC;
401
402 if (of_property_read_bool(np, "fsl,mc13xxx-uses-codec"))
403 mc13xxx->flags |= MC13XXX_USE_CODEC;
404
405 if (of_property_read_bool(np, "fsl,mc13xxx-uses-rtc"))
406 mc13xxx->flags |= MC13XXX_USE_RTC;
407
408 if (of_property_read_bool(np, "fsl,mc13xxx-uses-touch"))
409 mc13xxx->flags |= MC13XXX_USE_TOUCHSCREEN;
410
411 return 0;
412}
413#else
414static inline int mc13xxx_probe_flags_dt(struct mc13xxx *mc13xxx)
415{
416 return -ENODEV;
417}
418#endif
419
420int mc13xxx_common_init(struct device *dev)
421{
422 struct mc13xxx_platform_data *pdata = dev_get_platdata(dev);
423 struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
424 u32 revision;
425 int i, ret;
426
427 mc13xxx->dev = dev;
428
429 ret = mc13xxx_reg_read(mc13xxx, MC13XXX_REVISION, &revision);
430 if (ret)
431 return ret;
432
433 mc13xxx->variant->print_revision(mc13xxx, revision);
434
435 ret = mc13xxx_reg_rmw(mc13xxx, MC13XXX_PWRCTRL,
436 MC13XXX_PWRCTRL_WDIRESET, MC13XXX_PWRCTRL_WDIRESET);
437 if (ret)
438 return ret;
439
440 for (i = 0; i < ARRAY_SIZE(mc13xxx->irqs); i++) {
441 mc13xxx->irqs[i].reg_offset = i / MC13XXX_IRQ_PER_REG;
442 mc13xxx->irqs[i].mask = BIT(i % MC13XXX_IRQ_PER_REG);
443 }
444
445 mc13xxx->irq_chip.name = dev_name(dev);
446 mc13xxx->irq_chip.status_base = MC13XXX_IRQSTAT0;
447 mc13xxx->irq_chip.mask_base = MC13XXX_IRQMASK0;
448 mc13xxx->irq_chip.ack_base = MC13XXX_IRQSTAT0;
449 mc13xxx->irq_chip.irq_reg_stride = MC13XXX_IRQSTAT1 - MC13XXX_IRQSTAT0;
450 mc13xxx->irq_chip.init_ack_masked = true;
451 mc13xxx->irq_chip.use_ack = true;
452 mc13xxx->irq_chip.num_regs = MC13XXX_IRQ_REG_CNT;
453 mc13xxx->irq_chip.irqs = mc13xxx->irqs;
454 mc13xxx->irq_chip.num_irqs = ARRAY_SIZE(mc13xxx->irqs);
455
456 ret = regmap_add_irq_chip(mc13xxx->regmap, mc13xxx->irq, IRQF_ONESHOT,
457 0, &mc13xxx->irq_chip, &mc13xxx->irq_data);
458 if (ret)
459 return ret;
460
461 mutex_init(&mc13xxx->lock);
462
463 if (mc13xxx_probe_flags_dt(mc13xxx) < 0 && pdata)
464 mc13xxx->flags = pdata->flags;
465
466 if (pdata) {
467 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-regulator",
468 &pdata->regulators, sizeof(pdata->regulators));
469 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-led",
470 pdata->leds, sizeof(*pdata->leds));
471 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-pwrbutton",
472 pdata->buttons, sizeof(*pdata->buttons));
473 if (mc13xxx->flags & MC13XXX_USE_CODEC)
474 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-codec",
475 pdata->codec, sizeof(*pdata->codec));
476 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
477 mc13xxx_add_subdevice_pdata(mc13xxx, "%s-ts",
478 &pdata->touch, sizeof(pdata->touch));
479 } else {
480 mc13xxx_add_subdevice(mc13xxx, "%s-regulator");
481 mc13xxx_add_subdevice(mc13xxx, "%s-led");
482 mc13xxx_add_subdevice(mc13xxx, "%s-pwrbutton");
483 if (mc13xxx->flags & MC13XXX_USE_CODEC)
484 mc13xxx_add_subdevice(mc13xxx, "%s-codec");
485 if (mc13xxx->flags & MC13XXX_USE_TOUCHSCREEN)
486 mc13xxx_add_subdevice(mc13xxx, "%s-ts");
487 }
488
489 if (mc13xxx->flags & MC13XXX_USE_ADC)
490 mc13xxx_add_subdevice(mc13xxx, "%s-adc");
491
492 if (mc13xxx->flags & MC13XXX_USE_RTC)
493 mc13xxx_add_subdevice(mc13xxx, "%s-rtc");
494
495 return 0;
496}
497EXPORT_SYMBOL_GPL(mc13xxx_common_init);
498
499int mc13xxx_common_exit(struct device *dev)
500{
501 struct mc13xxx *mc13xxx = dev_get_drvdata(dev);
502
503 mfd_remove_devices(dev);
504 regmap_del_irq_chip(mc13xxx->irq, mc13xxx->irq_data);
505 mutex_destroy(&mc13xxx->lock);
506
507 return 0;
508}
509EXPORT_SYMBOL_GPL(mc13xxx_common_exit);
510
511MODULE_DESCRIPTION("Core driver for Freescale MC13XXX PMIC");
512MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>");
513MODULE_LICENSE("GPL v2");
514
