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9#include <linux/kernel.h>
10#include <linux/module.h>
11#include <linux/types.h>
12#include <linux/slab.h>
13#include <linux/spinlock.h>
14#include <linux/platform_device.h>
15#include <linux/clk.h>
16#include <linux/io.h>
17#include <linux/err.h>
18#include <linux/pm_runtime.h>
19#include <linux/platform_data/usb-omap.h>
20#include <linux/of.h>
21
22#include "omap-usb.h"
23
24#define USBTLL_DRIVER_NAME "usbhs_tll"
25
26
27#define OMAP_USBTLL_REVISION (0x00)
28#define OMAP_USBTLL_SYSCONFIG (0x10)
29#define OMAP_USBTLL_SYSCONFIG_CACTIVITY (1 << 8)
30#define OMAP_USBTLL_SYSCONFIG_SIDLEMODE (1 << 3)
31#define OMAP_USBTLL_SYSCONFIG_ENAWAKEUP (1 << 2)
32#define OMAP_USBTLL_SYSCONFIG_SOFTRESET (1 << 1)
33#define OMAP_USBTLL_SYSCONFIG_AUTOIDLE (1 << 0)
34
35#define OMAP_USBTLL_SYSSTATUS (0x14)
36#define OMAP_USBTLL_SYSSTATUS_RESETDONE (1 << 0)
37
38#define OMAP_USBTLL_IRQSTATUS (0x18)
39#define OMAP_USBTLL_IRQENABLE (0x1C)
40
41#define OMAP_TLL_SHARED_CONF (0x30)
42#define OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN (1 << 6)
43#define OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN (1 << 5)
44#define OMAP_TLL_SHARED_CONF_USB_DIVRATION (1 << 2)
45#define OMAP_TLL_SHARED_CONF_FCLK_REQ (1 << 1)
46#define OMAP_TLL_SHARED_CONF_FCLK_IS_ON (1 << 0)
47
48#define OMAP_TLL_CHANNEL_CONF(num) (0x040 + 0x004 * num)
49#define OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT 24
50#define OMAP_TLL_CHANNEL_CONF_DRVVBUS (1 << 16)
51#define OMAP_TLL_CHANNEL_CONF_CHRGVBUS (1 << 15)
52#define OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF (1 << 11)
53#define OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE (1 << 10)
54#define OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE (1 << 9)
55#define OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE (1 << 8)
56#define OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI (2 << 1)
57#define OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS (1 << 1)
58#define OMAP_TLL_CHANNEL_CONF_CHANEN (1 << 0)
59
60#define OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0 0x0
61#define OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM 0x1
62#define OMAP_TLL_FSLSMODE_3PIN_PHY 0x2
63#define OMAP_TLL_FSLSMODE_4PIN_PHY 0x3
64#define OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0 0x4
65#define OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM 0x5
66#define OMAP_TLL_FSLSMODE_3PIN_TLL 0x6
67#define OMAP_TLL_FSLSMODE_4PIN_TLL 0x7
68#define OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0 0xA
69#define OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM 0xB
70
71#define OMAP_TLL_ULPI_FUNCTION_CTRL(num) (0x804 + 0x100 * num)
72#define OMAP_TLL_ULPI_INTERFACE_CTRL(num) (0x807 + 0x100 * num)
73#define OMAP_TLL_ULPI_OTG_CTRL(num) (0x80A + 0x100 * num)
74#define OMAP_TLL_ULPI_INT_EN_RISE(num) (0x80D + 0x100 * num)
75#define OMAP_TLL_ULPI_INT_EN_FALL(num) (0x810 + 0x100 * num)
76#define OMAP_TLL_ULPI_INT_STATUS(num) (0x813 + 0x100 * num)
77#define OMAP_TLL_ULPI_INT_LATCH(num) (0x814 + 0x100 * num)
78#define OMAP_TLL_ULPI_DEBUG(num) (0x815 + 0x100 * num)
79#define OMAP_TLL_ULPI_SCRATCH_REGISTER(num) (0x816 + 0x100 * num)
80
81#define OMAP_REV2_TLL_CHANNEL_COUNT 2
82#define OMAP_TLL_CHANNEL_COUNT 3
83#define OMAP_TLL_CHANNEL_1_EN_MASK (1 << 0)
84#define OMAP_TLL_CHANNEL_2_EN_MASK (1 << 1)
85#define OMAP_TLL_CHANNEL_3_EN_MASK (1 << 2)
86
87
88#define OMAP_USBTLL_REV1 0x00000015
89#define OMAP_USBTLL_REV2 0x00000018
90#define OMAP_USBTLL_REV3 0x00000004
91#define OMAP_USBTLL_REV4 0x00000006
92
93#define is_ehci_tll_mode(x) (x == OMAP_EHCI_PORT_MODE_TLL)
94
95
96#define omap_usb_mode_needs_tll(x) ((x) != OMAP_USBHS_PORT_MODE_UNUSED &&\
97 (x) != OMAP_EHCI_PORT_MODE_PHY)
98
99struct usbtll_omap {
100 void __iomem *base;
101 int nch;
102 struct clk *ch_clk[];
103};
104
105
106
107static const char usbtll_driver_name[] = USBTLL_DRIVER_NAME;
108static struct device *tll_dev;
109static DEFINE_SPINLOCK(tll_lock);
110
111
112
113static inline void usbtll_write(void __iomem *base, u32 reg, u32 val)
114{
115 writel_relaxed(val, base + reg);
116}
117
118static inline u32 usbtll_read(void __iomem *base, u32 reg)
119{
120 return readl_relaxed(base + reg);
121}
122
123static inline void usbtll_writeb(void __iomem *base, u32 reg, u8 val)
124{
125 writeb_relaxed(val, base + reg);
126}
127
128static inline u8 usbtll_readb(void __iomem *base, u32 reg)
129{
130 return readb_relaxed(base + reg);
131}
132
133
134
135static bool is_ohci_port(enum usbhs_omap_port_mode pmode)
136{
137 switch (pmode) {
138 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
139 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
140 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
141 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
142 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
143 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
144 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
145 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
146 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
147 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
148 return true;
149
150 default:
151 return false;
152 }
153}
154
155
156
157
158
159static unsigned ohci_omap3_fslsmode(enum usbhs_omap_port_mode mode)
160{
161 switch (mode) {
162 case OMAP_USBHS_PORT_MODE_UNUSED:
163 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0:
164 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
165
166 case OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM:
167 return OMAP_TLL_FSLSMODE_6PIN_PHY_DP_DM;
168
169 case OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0:
170 return OMAP_TLL_FSLSMODE_3PIN_PHY;
171
172 case OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM:
173 return OMAP_TLL_FSLSMODE_4PIN_PHY;
174
175 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0:
176 return OMAP_TLL_FSLSMODE_6PIN_TLL_DAT_SE0;
177
178 case OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM:
179 return OMAP_TLL_FSLSMODE_6PIN_TLL_DP_DM;
180
181 case OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0:
182 return OMAP_TLL_FSLSMODE_3PIN_TLL;
183
184 case OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM:
185 return OMAP_TLL_FSLSMODE_4PIN_TLL;
186
187 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0:
188 return OMAP_TLL_FSLSMODE_2PIN_TLL_DAT_SE0;
189
190 case OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM:
191 return OMAP_TLL_FSLSMODE_2PIN_DAT_DP_DM;
192 default:
193 pr_warn("Invalid port mode, using default\n");
194 return OMAP_TLL_FSLSMODE_6PIN_PHY_DAT_SE0;
195 }
196}
197
198
199
200
201
202
203
204
205static int usbtll_omap_probe(struct platform_device *pdev)
206{
207 struct device *dev = &pdev->dev;
208 struct resource *res;
209 struct usbtll_omap *tll;
210 void __iomem *base;
211 int i, nch, ver;
212
213 dev_dbg(dev, "starting TI HSUSB TLL Controller\n");
214
215 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
216 base = devm_ioremap_resource(dev, res);
217 if (IS_ERR(base))
218 return PTR_ERR(base);
219
220 pm_runtime_enable(dev);
221 pm_runtime_get_sync(dev);
222
223 ver = usbtll_read(base, OMAP_USBTLL_REVISION);
224 switch (ver) {
225 case OMAP_USBTLL_REV1:
226 case OMAP_USBTLL_REV4:
227 nch = OMAP_TLL_CHANNEL_COUNT;
228 break;
229 case OMAP_USBTLL_REV2:
230 case OMAP_USBTLL_REV3:
231 nch = OMAP_REV2_TLL_CHANNEL_COUNT;
232 break;
233 default:
234 nch = OMAP_TLL_CHANNEL_COUNT;
235 dev_dbg(dev, "rev 0x%x not recognized, assuming %d channels\n",
236 ver, nch);
237 break;
238 }
239
240 tll = devm_kzalloc(dev, sizeof(*tll) + sizeof(tll->ch_clk[nch]),
241 GFP_KERNEL);
242 if (!tll) {
243 pm_runtime_put_sync(dev);
244 pm_runtime_disable(dev);
245 return -ENOMEM;
246 }
247
248 tll->base = base;
249 tll->nch = nch;
250 platform_set_drvdata(pdev, tll);
251
252 for (i = 0; i < nch; i++) {
253 char clkname[] = "usb_tll_hs_usb_chx_clk";
254
255 snprintf(clkname, sizeof(clkname),
256 "usb_tll_hs_usb_ch%d_clk", i);
257 tll->ch_clk[i] = clk_get(dev, clkname);
258
259 if (IS_ERR(tll->ch_clk[i]))
260 dev_dbg(dev, "can't get clock : %s\n", clkname);
261 else
262 clk_prepare(tll->ch_clk[i]);
263 }
264
265 pm_runtime_put_sync(dev);
266
267 spin_lock(&tll_lock);
268 tll_dev = dev;
269 spin_unlock(&tll_lock);
270
271 return 0;
272}
273
274
275
276
277
278
279
280static int usbtll_omap_remove(struct platform_device *pdev)
281{
282 struct usbtll_omap *tll = platform_get_drvdata(pdev);
283 int i;
284
285 spin_lock(&tll_lock);
286 tll_dev = NULL;
287 spin_unlock(&tll_lock);
288
289 for (i = 0; i < tll->nch; i++) {
290 if (!IS_ERR(tll->ch_clk[i])) {
291 clk_unprepare(tll->ch_clk[i]);
292 clk_put(tll->ch_clk[i]);
293 }
294 }
295
296 pm_runtime_disable(&pdev->dev);
297 return 0;
298}
299
300static const struct of_device_id usbtll_omap_dt_ids[] = {
301 { .compatible = "ti,usbhs-tll" },
302 { }
303};
304
305MODULE_DEVICE_TABLE(of, usbtll_omap_dt_ids);
306
307static struct platform_driver usbtll_omap_driver = {
308 .driver = {
309 .name = usbtll_driver_name,
310 .of_match_table = usbtll_omap_dt_ids,
311 },
312 .probe = usbtll_omap_probe,
313 .remove = usbtll_omap_remove,
314};
315
316int omap_tll_init(struct usbhs_omap_platform_data *pdata)
317{
318 int i;
319 bool needs_tll;
320 unsigned reg;
321 struct usbtll_omap *tll;
322
323 if (!tll_dev)
324 return -ENODEV;
325
326 pm_runtime_get_sync(tll_dev);
327
328 spin_lock(&tll_lock);
329 tll = dev_get_drvdata(tll_dev);
330 needs_tll = false;
331 for (i = 0; i < tll->nch; i++)
332 needs_tll |= omap_usb_mode_needs_tll(pdata->port_mode[i]);
333
334 if (needs_tll) {
335 void __iomem *base = tll->base;
336
337
338 reg = usbtll_read(base, OMAP_TLL_SHARED_CONF);
339 reg |= (OMAP_TLL_SHARED_CONF_FCLK_IS_ON
340 | OMAP_TLL_SHARED_CONF_USB_DIVRATION);
341 reg &= ~OMAP_TLL_SHARED_CONF_USB_90D_DDR_EN;
342 reg &= ~OMAP_TLL_SHARED_CONF_USB_180D_SDR_EN;
343
344 usbtll_write(base, OMAP_TLL_SHARED_CONF, reg);
345
346
347 for (i = 0; i < tll->nch; i++) {
348 reg = usbtll_read(base, OMAP_TLL_CHANNEL_CONF(i));
349
350 if (is_ohci_port(pdata->port_mode[i])) {
351 reg |= ohci_omap3_fslsmode(pdata->port_mode[i])
352 << OMAP_TLL_CHANNEL_CONF_FSLSMODE_SHIFT;
353 reg |= OMAP_TLL_CHANNEL_CONF_CHANMODE_FSLS;
354 } else if (pdata->port_mode[i] ==
355 OMAP_EHCI_PORT_MODE_TLL) {
356
357
358
359
360 reg &= ~(OMAP_TLL_CHANNEL_CONF_UTMIAUTOIDLE
361 | OMAP_TLL_CHANNEL_CONF_ULPIDDRMODE);
362 reg |= OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
363 reg |= OMAP_TLL_CHANNEL_CONF_ULPI_ULPIAUTOIDLE;
364 } else if (pdata->port_mode[i] ==
365 OMAP_EHCI_PORT_MODE_HSIC) {
366
367
368
369 reg |= OMAP_TLL_CHANNEL_CONF_DRVVBUS
370 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
371 | OMAP_TLL_CHANNEL_CONF_MODE_TRANSPARENT_UTMI
372 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF;
373 } else {
374 continue;
375 }
376 reg |= OMAP_TLL_CHANNEL_CONF_CHANEN;
377 usbtll_write(base, OMAP_TLL_CHANNEL_CONF(i), reg);
378
379 usbtll_writeb(base,
380 OMAP_TLL_ULPI_SCRATCH_REGISTER(i),
381 0xbe);
382 }
383 }
384
385 spin_unlock(&tll_lock);
386 pm_runtime_put_sync(tll_dev);
387
388 return 0;
389}
390EXPORT_SYMBOL_GPL(omap_tll_init);
391
392int omap_tll_enable(struct usbhs_omap_platform_data *pdata)
393{
394 int i;
395 struct usbtll_omap *tll;
396
397 if (!tll_dev)
398 return -ENODEV;
399
400 pm_runtime_get_sync(tll_dev);
401
402 spin_lock(&tll_lock);
403 tll = dev_get_drvdata(tll_dev);
404
405 for (i = 0; i < tll->nch; i++) {
406 if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
407 int r;
408
409 if (IS_ERR(tll->ch_clk[i]))
410 continue;
411
412 r = clk_enable(tll->ch_clk[i]);
413 if (r) {
414 dev_err(tll_dev,
415 "Error enabling ch %d clock: %d\n", i, r);
416 }
417 }
418 }
419
420 spin_unlock(&tll_lock);
421
422 return 0;
423}
424EXPORT_SYMBOL_GPL(omap_tll_enable);
425
426int omap_tll_disable(struct usbhs_omap_platform_data *pdata)
427{
428 int i;
429 struct usbtll_omap *tll;
430
431 if (!tll_dev)
432 return -ENODEV;
433
434 spin_lock(&tll_lock);
435 tll = dev_get_drvdata(tll_dev);
436
437 for (i = 0; i < tll->nch; i++) {
438 if (omap_usb_mode_needs_tll(pdata->port_mode[i])) {
439 if (!IS_ERR(tll->ch_clk[i]))
440 clk_disable(tll->ch_clk[i]);
441 }
442 }
443
444 spin_unlock(&tll_lock);
445 pm_runtime_put_sync(tll_dev);
446
447 return 0;
448}
449EXPORT_SYMBOL_GPL(omap_tll_disable);
450
451MODULE_AUTHOR("Keshava Munegowda <keshava_mgowda@ti.com>");
452MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>");
453MODULE_LICENSE("GPL v2");
454MODULE_DESCRIPTION("usb tll driver for TI OMAP EHCI and OHCI controllers");
455
456static int __init omap_usbtll_drvinit(void)
457{
458 return platform_driver_register(&usbtll_omap_driver);
459}
460
461
462
463
464
465
466fs_initcall(omap_usbtll_drvinit);
467
468static void __exit omap_usbtll_drvexit(void)
469{
470 platform_driver_unregister(&usbtll_omap_driver);
471}
472module_exit(omap_usbtll_drvexit);
473
