1
2
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4
5
6#define pr_fmt(fmt) "%s: " fmt, __func__
7
8#include <linux/kernel.h>
9#include <linux/interrupt.h>
10#include <linux/irqchip/chained_irq.h>
11#include <linux/irq.h>
12#include <linux/irqdomain.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15#include <linux/slab.h>
16#include <linux/err.h>
17#include <linux/ssbi.h>
18#include <linux/regmap.h>
19#include <linux/of_platform.h>
20#include <linux/mfd/core.h>
21
22#define SSBI_REG_ADDR_IRQ_BASE 0x1BB
23
24#define SSBI_REG_ADDR_IRQ_ROOT (SSBI_REG_ADDR_IRQ_BASE + 0)
25#define SSBI_REG_ADDR_IRQ_M_STATUS1 (SSBI_REG_ADDR_IRQ_BASE + 1)
26#define SSBI_REG_ADDR_IRQ_M_STATUS2 (SSBI_REG_ADDR_IRQ_BASE + 2)
27#define SSBI_REG_ADDR_IRQ_M_STATUS3 (SSBI_REG_ADDR_IRQ_BASE + 3)
28#define SSBI_REG_ADDR_IRQ_M_STATUS4 (SSBI_REG_ADDR_IRQ_BASE + 4)
29#define SSBI_REG_ADDR_IRQ_BLK_SEL (SSBI_REG_ADDR_IRQ_BASE + 5)
30#define SSBI_REG_ADDR_IRQ_IT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 6)
31#define SSBI_REG_ADDR_IRQ_CONFIG (SSBI_REG_ADDR_IRQ_BASE + 7)
32#define SSBI_REG_ADDR_IRQ_RT_STATUS (SSBI_REG_ADDR_IRQ_BASE + 8)
33
34#define PM8821_SSBI_REG_ADDR_IRQ_BASE 0x100
35#define PM8821_SSBI_REG_ADDR_IRQ_MASTER0 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0x30)
36#define PM8821_SSBI_REG_ADDR_IRQ_MASTER1 (PM8821_SSBI_REG_ADDR_IRQ_BASE + 0xb0)
37#define PM8821_SSBI_REG(m, b, offset) \
38 ((m == 0) ? \
39 (PM8821_SSBI_REG_ADDR_IRQ_MASTER0 + b + offset) : \
40 (PM8821_SSBI_REG_ADDR_IRQ_MASTER1 + b + offset))
41#define PM8821_SSBI_ADDR_IRQ_ROOT(m, b) PM8821_SSBI_REG(m, b, 0x0)
42#define PM8821_SSBI_ADDR_IRQ_CLEAR(m, b) PM8821_SSBI_REG(m, b, 0x01)
43#define PM8821_SSBI_ADDR_IRQ_MASK(m, b) PM8821_SSBI_REG(m, b, 0x08)
44#define PM8821_SSBI_ADDR_IRQ_RT_STATUS(m, b) PM8821_SSBI_REG(m, b, 0x0f)
45
46#define PM8821_BLOCKS_PER_MASTER 7
47
48#define PM_IRQF_LVL_SEL 0x01
49#define PM_IRQF_MASK_FE 0x02
50#define PM_IRQF_MASK_RE 0x04
51#define PM_IRQF_CLR 0x08
52#define PM_IRQF_BITS_MASK 0x70
53#define PM_IRQF_BITS_SHIFT 4
54#define PM_IRQF_WRITE 0x80
55
56#define PM_IRQF_MASK_ALL (PM_IRQF_MASK_FE | \
57 PM_IRQF_MASK_RE)
58
59#define REG_HWREV 0x002
60#define REG_HWREV_2 0x0E8
61
62#define PM8XXX_NR_IRQS 256
63#define PM8821_NR_IRQS 112
64
65struct pm_irq_data {
66 int num_irqs;
67 struct irq_chip *irq_chip;
68 void (*irq_handler)(struct irq_desc *desc);
69};
70
71struct pm_irq_chip {
72 struct regmap *regmap;
73 spinlock_t pm_irq_lock;
74 struct irq_domain *irqdomain;
75 unsigned int num_blocks;
76 unsigned int num_masters;
77 const struct pm_irq_data *pm_irq_data;
78
79 u8 config[];
80};
81
82static int pm8xxx_read_block_irq(struct pm_irq_chip *chip, unsigned int bp,
83 unsigned int *ip)
84{
85 int rc;
86
87 spin_lock(&chip->pm_irq_lock);
88 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
89 if (rc) {
90 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
91 goto bail;
92 }
93
94 rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_IT_STATUS, ip);
95 if (rc)
96 pr_err("Failed Reading Status rc=%d\n", rc);
97bail:
98 spin_unlock(&chip->pm_irq_lock);
99 return rc;
100}
101
102static int
103pm8xxx_config_irq(struct pm_irq_chip *chip, unsigned int bp, unsigned int cp)
104{
105 int rc;
106
107 spin_lock(&chip->pm_irq_lock);
108 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, bp);
109 if (rc) {
110 pr_err("Failed Selecting Block %d rc=%d\n", bp, rc);
111 goto bail;
112 }
113
114 cp |= PM_IRQF_WRITE;
115 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_CONFIG, cp);
116 if (rc)
117 pr_err("Failed Configuring IRQ rc=%d\n", rc);
118bail:
119 spin_unlock(&chip->pm_irq_lock);
120 return rc;
121}
122
123static int pm8xxx_irq_block_handler(struct pm_irq_chip *chip, int block)
124{
125 int pmirq, i, ret = 0;
126 unsigned int bits;
127
128 ret = pm8xxx_read_block_irq(chip, block, &bits);
129 if (ret) {
130 pr_err("Failed reading %d block ret=%d", block, ret);
131 return ret;
132 }
133 if (!bits) {
134 pr_err("block bit set in master but no irqs: %d", block);
135 return 0;
136 }
137
138
139 for (i = 0; i < 8; i++) {
140 if (bits & (1 << i)) {
141 pmirq = block * 8 + i;
142 generic_handle_domain_irq(chip->irqdomain, pmirq);
143 }
144 }
145 return 0;
146}
147
148static int pm8xxx_irq_master_handler(struct pm_irq_chip *chip, int master)
149{
150 unsigned int blockbits;
151 int block_number, i, ret = 0;
152
153 ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_M_STATUS1 + master,
154 &blockbits);
155 if (ret) {
156 pr_err("Failed to read master %d ret=%d\n", master, ret);
157 return ret;
158 }
159 if (!blockbits) {
160 pr_err("master bit set in root but no blocks: %d", master);
161 return 0;
162 }
163
164 for (i = 0; i < 8; i++)
165 if (blockbits & (1 << i)) {
166 block_number = master * 8 + i;
167 ret |= pm8xxx_irq_block_handler(chip, block_number);
168 }
169 return ret;
170}
171
172static void pm8xxx_irq_handler(struct irq_desc *desc)
173{
174 struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
175 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
176 unsigned int root;
177 int i, ret, masters = 0;
178
179 chained_irq_enter(irq_chip, desc);
180
181 ret = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_ROOT, &root);
182 if (ret) {
183 pr_err("Can't read root status ret=%d\n", ret);
184 return;
185 }
186
187
188 masters = root >> 1;
189
190
191 for (i = 0; i < chip->num_masters; i++)
192 if (masters & (1 << i))
193 pm8xxx_irq_master_handler(chip, i);
194
195 chained_irq_exit(irq_chip, desc);
196}
197
198static void pm8821_irq_block_handler(struct pm_irq_chip *chip,
199 int master, int block)
200{
201 int pmirq, i, ret;
202 unsigned int bits;
203
204 ret = regmap_read(chip->regmap,
205 PM8821_SSBI_ADDR_IRQ_ROOT(master, block), &bits);
206 if (ret) {
207 pr_err("Reading block %d failed ret=%d", block, ret);
208 return;
209 }
210
211
212 block += (master * PM8821_BLOCKS_PER_MASTER) - 1;
213
214
215 for (i = 0; i < 8; i++) {
216 if (bits & BIT(i)) {
217 pmirq = block * 8 + i;
218 generic_handle_domain_irq(chip->irqdomain, pmirq);
219 }
220 }
221}
222
223static inline void pm8821_irq_master_handler(struct pm_irq_chip *chip,
224 int master, u8 master_val)
225{
226 int block;
227
228 for (block = 1; block < 8; block++)
229 if (master_val & BIT(block))
230 pm8821_irq_block_handler(chip, master, block);
231}
232
233static void pm8821_irq_handler(struct irq_desc *desc)
234{
235 struct pm_irq_chip *chip = irq_desc_get_handler_data(desc);
236 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
237 unsigned int master;
238 int ret;
239
240 chained_irq_enter(irq_chip, desc);
241 ret = regmap_read(chip->regmap,
242 PM8821_SSBI_REG_ADDR_IRQ_MASTER0, &master);
243 if (ret) {
244 pr_err("Failed to read master 0 ret=%d\n", ret);
245 goto done;
246 }
247
248
249 if (master & GENMASK(7, 1))
250 pm8821_irq_master_handler(chip, 0, master);
251
252
253 if (!(master & BIT(0)))
254 goto done;
255
256 ret = regmap_read(chip->regmap,
257 PM8821_SSBI_REG_ADDR_IRQ_MASTER1, &master);
258 if (ret) {
259 pr_err("Failed to read master 1 ret=%d\n", ret);
260 goto done;
261 }
262
263 pm8821_irq_master_handler(chip, 1, master);
264
265done:
266 chained_irq_exit(irq_chip, desc);
267}
268
269static void pm8xxx_irq_mask_ack(struct irq_data *d)
270{
271 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
272 unsigned int pmirq = irqd_to_hwirq(d);
273 u8 block, config;
274
275 block = pmirq / 8;
276
277 config = chip->config[pmirq] | PM_IRQF_MASK_ALL | PM_IRQF_CLR;
278 pm8xxx_config_irq(chip, block, config);
279}
280
281static void pm8xxx_irq_unmask(struct irq_data *d)
282{
283 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
284 unsigned int pmirq = irqd_to_hwirq(d);
285 u8 block, config;
286
287 block = pmirq / 8;
288
289 config = chip->config[pmirq];
290 pm8xxx_config_irq(chip, block, config);
291}
292
293static int pm8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
294{
295 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
296 unsigned int pmirq = irqd_to_hwirq(d);
297 int irq_bit;
298 u8 block, config;
299
300 block = pmirq / 8;
301 irq_bit = pmirq % 8;
302
303 chip->config[pmirq] = (irq_bit << PM_IRQF_BITS_SHIFT)
304 | PM_IRQF_MASK_ALL;
305 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
306 if (flow_type & IRQF_TRIGGER_RISING)
307 chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
308 if (flow_type & IRQF_TRIGGER_FALLING)
309 chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
310 } else {
311 chip->config[pmirq] |= PM_IRQF_LVL_SEL;
312
313 if (flow_type & IRQF_TRIGGER_HIGH)
314 chip->config[pmirq] &= ~PM_IRQF_MASK_RE;
315 else
316 chip->config[pmirq] &= ~PM_IRQF_MASK_FE;
317 }
318
319 config = chip->config[pmirq] | PM_IRQF_CLR;
320 return pm8xxx_config_irq(chip, block, config);
321}
322
323static int pm8xxx_irq_get_irqchip_state(struct irq_data *d,
324 enum irqchip_irq_state which,
325 bool *state)
326{
327 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
328 unsigned int pmirq = irqd_to_hwirq(d);
329 unsigned int bits;
330 int irq_bit;
331 u8 block;
332 int rc;
333
334 if (which != IRQCHIP_STATE_LINE_LEVEL)
335 return -EINVAL;
336
337 block = pmirq / 8;
338 irq_bit = pmirq % 8;
339
340 spin_lock(&chip->pm_irq_lock);
341 rc = regmap_write(chip->regmap, SSBI_REG_ADDR_IRQ_BLK_SEL, block);
342 if (rc) {
343 pr_err("Failed Selecting Block %d rc=%d\n", block, rc);
344 goto bail;
345 }
346
347 rc = regmap_read(chip->regmap, SSBI_REG_ADDR_IRQ_RT_STATUS, &bits);
348 if (rc) {
349 pr_err("Failed Reading Status rc=%d\n", rc);
350 goto bail;
351 }
352
353 *state = !!(bits & BIT(irq_bit));
354bail:
355 spin_unlock(&chip->pm_irq_lock);
356
357 return rc;
358}
359
360static struct irq_chip pm8xxx_irq_chip = {
361 .name = "pm8xxx",
362 .irq_mask_ack = pm8xxx_irq_mask_ack,
363 .irq_unmask = pm8xxx_irq_unmask,
364 .irq_set_type = pm8xxx_irq_set_type,
365 .irq_get_irqchip_state = pm8xxx_irq_get_irqchip_state,
366 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
367};
368
369static void pm8xxx_irq_domain_map(struct pm_irq_chip *chip,
370 struct irq_domain *domain, unsigned int irq,
371 irq_hw_number_t hwirq, unsigned int type)
372{
373 irq_domain_set_info(domain, irq, hwirq, chip->pm_irq_data->irq_chip,
374 chip, handle_level_irq, NULL, NULL);
375 irq_set_noprobe(irq);
376}
377
378static int pm8xxx_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
379 unsigned int nr_irqs, void *data)
380{
381 struct pm_irq_chip *chip = domain->host_data;
382 struct irq_fwspec *fwspec = data;
383 irq_hw_number_t hwirq;
384 unsigned int type;
385 int ret, i;
386
387 ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
388 if (ret)
389 return ret;
390
391 for (i = 0; i < nr_irqs; i++)
392 pm8xxx_irq_domain_map(chip, domain, virq + i, hwirq + i, type);
393
394 return 0;
395}
396
397static const struct irq_domain_ops pm8xxx_irq_domain_ops = {
398 .alloc = pm8xxx_irq_domain_alloc,
399 .free = irq_domain_free_irqs_common,
400 .translate = irq_domain_translate_twocell,
401};
402
403static void pm8821_irq_mask_ack(struct irq_data *d)
404{
405 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
406 unsigned int pmirq = irqd_to_hwirq(d);
407 u8 block, master;
408 int irq_bit, rc;
409
410 block = pmirq / 8;
411 master = block / PM8821_BLOCKS_PER_MASTER;
412 irq_bit = pmirq % 8;
413 block %= PM8821_BLOCKS_PER_MASTER;
414
415 rc = regmap_update_bits(chip->regmap,
416 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
417 BIT(irq_bit), BIT(irq_bit));
418 if (rc) {
419 pr_err("Failed to mask IRQ:%d rc=%d\n", pmirq, rc);
420 return;
421 }
422
423 rc = regmap_update_bits(chip->regmap,
424 PM8821_SSBI_ADDR_IRQ_CLEAR(master, block),
425 BIT(irq_bit), BIT(irq_bit));
426 if (rc)
427 pr_err("Failed to CLEAR IRQ:%d rc=%d\n", pmirq, rc);
428}
429
430static void pm8821_irq_unmask(struct irq_data *d)
431{
432 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
433 unsigned int pmirq = irqd_to_hwirq(d);
434 int irq_bit, rc;
435 u8 block, master;
436
437 block = pmirq / 8;
438 master = block / PM8821_BLOCKS_PER_MASTER;
439 irq_bit = pmirq % 8;
440 block %= PM8821_BLOCKS_PER_MASTER;
441
442 rc = regmap_update_bits(chip->regmap,
443 PM8821_SSBI_ADDR_IRQ_MASK(master, block),
444 BIT(irq_bit), ~BIT(irq_bit));
445 if (rc)
446 pr_err("Failed to read/write unmask IRQ:%d rc=%d\n", pmirq, rc);
447
448}
449
450static int pm8821_irq_get_irqchip_state(struct irq_data *d,
451 enum irqchip_irq_state which,
452 bool *state)
453{
454 struct pm_irq_chip *chip = irq_data_get_irq_chip_data(d);
455 int rc, pmirq = irqd_to_hwirq(d);
456 u8 block, irq_bit, master;
457 unsigned int bits;
458
459 block = pmirq / 8;
460 master = block / PM8821_BLOCKS_PER_MASTER;
461 irq_bit = pmirq % 8;
462 block %= PM8821_BLOCKS_PER_MASTER;
463
464 rc = regmap_read(chip->regmap,
465 PM8821_SSBI_ADDR_IRQ_RT_STATUS(master, block), &bits);
466 if (rc) {
467 pr_err("Reading Status of IRQ %d failed rc=%d\n", pmirq, rc);
468 return rc;
469 }
470
471 *state = !!(bits & BIT(irq_bit));
472
473 return rc;
474}
475
476static struct irq_chip pm8821_irq_chip = {
477 .name = "pm8821",
478 .irq_mask_ack = pm8821_irq_mask_ack,
479 .irq_unmask = pm8821_irq_unmask,
480 .irq_get_irqchip_state = pm8821_irq_get_irqchip_state,
481 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE,
482};
483
484static const struct regmap_config ssbi_regmap_config = {
485 .reg_bits = 16,
486 .val_bits = 8,
487 .max_register = 0x3ff,
488 .fast_io = true,
489 .reg_read = ssbi_reg_read,
490 .reg_write = ssbi_reg_write
491};
492
493static const struct pm_irq_data pm8xxx_data = {
494 .num_irqs = PM8XXX_NR_IRQS,
495 .irq_chip = &pm8xxx_irq_chip,
496 .irq_handler = pm8xxx_irq_handler,
497};
498
499static const struct pm_irq_data pm8821_data = {
500 .num_irqs = PM8821_NR_IRQS,
501 .irq_chip = &pm8821_irq_chip,
502 .irq_handler = pm8821_irq_handler,
503};
504
505static const struct of_device_id pm8xxx_id_table[] = {
506 { .compatible = "qcom,pm8018", .data = &pm8xxx_data},
507 { .compatible = "qcom,pm8058", .data = &pm8xxx_data},
508 { .compatible = "qcom,pm8821", .data = &pm8821_data},
509 { .compatible = "qcom,pm8921", .data = &pm8xxx_data},
510 { }
511};
512MODULE_DEVICE_TABLE(of, pm8xxx_id_table);
513
514static int pm8xxx_probe(struct platform_device *pdev)
515{
516 const struct pm_irq_data *data;
517 struct regmap *regmap;
518 int irq, rc;
519 unsigned int val;
520 u32 rev;
521 struct pm_irq_chip *chip;
522
523 data = of_device_get_match_data(&pdev->dev);
524 if (!data) {
525 dev_err(&pdev->dev, "No matching driver data found\n");
526 return -EINVAL;
527 }
528
529 irq = platform_get_irq(pdev, 0);
530 if (irq < 0)
531 return irq;
532
533 regmap = devm_regmap_init(&pdev->dev, NULL, pdev->dev.parent,
534 &ssbi_regmap_config);
535 if (IS_ERR(regmap))
536 return PTR_ERR(regmap);
537
538
539 rc = regmap_read(regmap, REG_HWREV, &val);
540 if (rc) {
541 pr_err("Failed to read hw rev reg %d:rc=%d\n", REG_HWREV, rc);
542 return rc;
543 }
544 pr_info("PMIC revision 1: %02X\n", val);
545 rev = val;
546
547
548 rc = regmap_read(regmap, REG_HWREV_2, &val);
549 if (rc) {
550 pr_err("Failed to read hw rev 2 reg %d:rc=%d\n",
551 REG_HWREV_2, rc);
552 return rc;
553 }
554 pr_info("PMIC revision 2: %02X\n", val);
555 rev |= val << BITS_PER_BYTE;
556
557 chip = devm_kzalloc(&pdev->dev,
558 struct_size(chip, config, data->num_irqs),
559 GFP_KERNEL);
560 if (!chip)
561 return -ENOMEM;
562
563 platform_set_drvdata(pdev, chip);
564 chip->regmap = regmap;
565 chip->num_blocks = DIV_ROUND_UP(data->num_irqs, 8);
566 chip->num_masters = DIV_ROUND_UP(chip->num_blocks, 8);
567 chip->pm_irq_data = data;
568 spin_lock_init(&chip->pm_irq_lock);
569
570 chip->irqdomain = irq_domain_add_linear(pdev->dev.of_node,
571 data->num_irqs,
572 &pm8xxx_irq_domain_ops,
573 chip);
574 if (!chip->irqdomain)
575 return -ENODEV;
576
577 irq_set_chained_handler_and_data(irq, data->irq_handler, chip);
578 irq_set_irq_wake(irq, 1);
579
580 rc = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
581 if (rc) {
582 irq_set_chained_handler_and_data(irq, NULL, NULL);
583 irq_domain_remove(chip->irqdomain);
584 }
585
586 return rc;
587}
588
589static int pm8xxx_remove_child(struct device *dev, void *unused)
590{
591 platform_device_unregister(to_platform_device(dev));
592 return 0;
593}
594
595static int pm8xxx_remove(struct platform_device *pdev)
596{
597 int irq = platform_get_irq(pdev, 0);
598 struct pm_irq_chip *chip = platform_get_drvdata(pdev);
599
600 device_for_each_child(&pdev->dev, NULL, pm8xxx_remove_child);
601 irq_set_chained_handler_and_data(irq, NULL, NULL);
602 irq_domain_remove(chip->irqdomain);
603
604 return 0;
605}
606
607static struct platform_driver pm8xxx_driver = {
608 .probe = pm8xxx_probe,
609 .remove = pm8xxx_remove,
610 .driver = {
611 .name = "pm8xxx-core",
612 .of_match_table = pm8xxx_id_table,
613 },
614};
615
616static int __init pm8xxx_init(void)
617{
618 return platform_driver_register(&pm8xxx_driver);
619}
620subsys_initcall(pm8xxx_init);
621
622static void __exit pm8xxx_exit(void)
623{
624 platform_driver_unregister(&pm8xxx_driver);
625}
626module_exit(pm8xxx_exit);
627
628MODULE_LICENSE("GPL v2");
629MODULE_DESCRIPTION("PMIC 8xxx core driver");
630MODULE_VERSION("1.0");
631MODULE_ALIAS("platform:pm8xxx-core");
632
