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6#include <linux/spinlock.h>
7#include <linux/kernel.h>
8#include <linux/module.h>
9#include <linux/device.h>
10#include <linux/mutex.h>
11#include <linux/init.h>
12#include <linux/list.h>
13#include <linux/mm.h>
14#include <linux/of.h>
15#include <linux/slab.h>
16#include <linux/idr.h>
17#include <linux/pci.h>
18#include <linux/sched/task.h>
19
20#include <asm/cputable.h>
21#include <asm/mmu.h>
22#include <misc/cxl-base.h>
23
24#include "cxl.h"
25#include "trace.h"
26
27static DEFINE_SPINLOCK(adapter_idr_lock);
28static DEFINE_IDR(cxl_adapter_idr);
29
30uint cxl_verbose;
31module_param_named(verbose, cxl_verbose, uint, 0600);
32MODULE_PARM_DESC(verbose, "Enable verbose dmesg output");
33
34const struct cxl_backend_ops *cxl_ops;
35
36int cxl_afu_slbia(struct cxl_afu *afu)
37{
38 unsigned long timeout = jiffies + (HZ * CXL_TIMEOUT);
39
40 pr_devel("cxl_afu_slbia issuing SLBIA command\n");
41 cxl_p2n_write(afu, CXL_SLBIA_An, CXL_TLB_SLB_IQ_ALL);
42 while (cxl_p2n_read(afu, CXL_SLBIA_An) & CXL_TLB_SLB_P) {
43 if (time_after_eq(jiffies, timeout)) {
44 dev_warn(&afu->dev, "WARNING: CXL AFU SLBIA timed out!\n");
45 return -EBUSY;
46 }
47
48
49
50 if (!cxl_ops->link_ok(afu->adapter, afu))
51 return -EIO;
52 cpu_relax();
53 }
54 return 0;
55}
56
57static inline void _cxl_slbia(struct cxl_context *ctx, struct mm_struct *mm)
58{
59 unsigned long flags;
60
61 if (ctx->mm != mm)
62 return;
63
64 pr_devel("%s matched mm - card: %i afu: %i pe: %i\n", __func__,
65 ctx->afu->adapter->adapter_num, ctx->afu->slice, ctx->pe);
66
67 spin_lock_irqsave(&ctx->sste_lock, flags);
68 trace_cxl_slbia(ctx);
69 memset(ctx->sstp, 0, ctx->sst_size);
70 spin_unlock_irqrestore(&ctx->sste_lock, flags);
71 mb();
72 cxl_afu_slbia(ctx->afu);
73}
74
75static inline void cxl_slbia_core(struct mm_struct *mm)
76{
77 struct cxl *adapter;
78 struct cxl_afu *afu;
79 struct cxl_context *ctx;
80 int card, slice, id;
81
82 pr_devel("%s called\n", __func__);
83
84 spin_lock(&adapter_idr_lock);
85 idr_for_each_entry(&cxl_adapter_idr, adapter, card) {
86
87 spin_lock(&adapter->afu_list_lock);
88 for (slice = 0; slice < adapter->slices; slice++) {
89 afu = adapter->afu[slice];
90 if (!afu || !afu->enabled)
91 continue;
92 rcu_read_lock();
93 idr_for_each_entry(&afu->contexts_idr, ctx, id)
94 _cxl_slbia(ctx, mm);
95 rcu_read_unlock();
96 }
97 spin_unlock(&adapter->afu_list_lock);
98 }
99 spin_unlock(&adapter_idr_lock);
100}
101
102static struct cxl_calls cxl_calls = {
103 .cxl_slbia = cxl_slbia_core,
104 .owner = THIS_MODULE,
105};
106
107int cxl_alloc_sst(struct cxl_context *ctx)
108{
109 unsigned long vsid;
110 u64 ea_mask, size, sstp0, sstp1;
111
112 sstp0 = 0;
113 sstp1 = 0;
114
115 ctx->sst_size = PAGE_SIZE;
116 ctx->sst_lru = 0;
117 ctx->sstp = (struct cxl_sste *)get_zeroed_page(GFP_KERNEL);
118 if (!ctx->sstp) {
119 pr_err("cxl_alloc_sst: Unable to allocate segment table\n");
120 return -ENOMEM;
121 }
122 pr_devel("SSTP allocated at 0x%p\n", ctx->sstp);
123
124 vsid = get_kernel_vsid((u64)ctx->sstp, mmu_kernel_ssize) << 12;
125
126 sstp0 |= (u64)mmu_kernel_ssize << CXL_SSTP0_An_B_SHIFT;
127 sstp0 |= (SLB_VSID_KERNEL | mmu_psize_defs[mmu_linear_psize].sllp) << 50;
128
129 size = (((u64)ctx->sst_size >> 8) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT;
130 if (unlikely(size & ~CXL_SSTP0_An_SegTableSize_MASK)) {
131 WARN(1, "Impossible segment table size\n");
132 return -EINVAL;
133 }
134 sstp0 |= size;
135
136 if (mmu_kernel_ssize == MMU_SEGSIZE_256M)
137 ea_mask = 0xfffff00ULL;
138 else
139 ea_mask = 0xffffffff00ULL;
140
141 sstp0 |= vsid >> (50-14);
142 sstp1 |= (vsid << (64-(50-14))) & ~ea_mask;
143 sstp1 |= (u64)ctx->sstp & ea_mask;
144 sstp1 |= CXL_SSTP1_An_V;
145
146 pr_devel("Looked up %#llx: slbfee. %#llx (ssize: %x, vsid: %#lx), copied to SSTP0: %#llx, SSTP1: %#llx\n",
147 (u64)ctx->sstp, (u64)ctx->sstp & ESID_MASK, mmu_kernel_ssize, vsid, sstp0, sstp1);
148
149
150 ctx->sstp0 = sstp0;
151 ctx->sstp1 = sstp1;
152
153 return 0;
154}
155
156
157void cxl_dump_debug_buffer(void *buf, size_t buf_len)
158{
159#ifdef DEBUG
160 int i, *ptr;
161
162
163
164
165
166 ptr = (int *) buf;
167 for (i = 0; i * 4 < buf_len; i += 4) {
168 if ((i + 3) * 4 < buf_len)
169 pr_devel("%.8x %.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
170 ptr[i + 2], ptr[i + 3]);
171 else if ((i + 2) * 4 < buf_len)
172 pr_devel("%.8x %.8x %.8x\n", ptr[i], ptr[i + 1],
173 ptr[i + 2]);
174 else if ((i + 1) * 4 < buf_len)
175 pr_devel("%.8x %.8x\n", ptr[i], ptr[i + 1]);
176 else
177 pr_devel("%.8x\n", ptr[i]);
178 }
179#endif
180}
181
182
183struct cxl *get_cxl_adapter(int num)
184{
185 struct cxl *adapter;
186
187 spin_lock(&adapter_idr_lock);
188 if ((adapter = idr_find(&cxl_adapter_idr, num)))
189 get_device(&adapter->dev);
190 spin_unlock(&adapter_idr_lock);
191
192 return adapter;
193}
194
195static int cxl_alloc_adapter_nr(struct cxl *adapter)
196{
197 int i;
198
199 idr_preload(GFP_KERNEL);
200 spin_lock(&adapter_idr_lock);
201 i = idr_alloc(&cxl_adapter_idr, adapter, 0, 0, GFP_NOWAIT);
202 spin_unlock(&adapter_idr_lock);
203 idr_preload_end();
204 if (i < 0)
205 return i;
206
207 adapter->adapter_num = i;
208
209 return 0;
210}
211
212void cxl_remove_adapter_nr(struct cxl *adapter)
213{
214 idr_remove(&cxl_adapter_idr, adapter->adapter_num);
215}
216
217struct cxl *cxl_alloc_adapter(void)
218{
219 struct cxl *adapter;
220
221 if (!(adapter = kzalloc(sizeof(struct cxl), GFP_KERNEL)))
222 return NULL;
223
224 spin_lock_init(&adapter->afu_list_lock);
225
226 if (cxl_alloc_adapter_nr(adapter))
227 goto err1;
228
229 if (dev_set_name(&adapter->dev, "card%i", adapter->adapter_num))
230 goto err2;
231
232
233 atomic_set(&adapter->contexts_num, -1);
234
235 return adapter;
236err2:
237 cxl_remove_adapter_nr(adapter);
238err1:
239 kfree(adapter);
240 return NULL;
241}
242
243struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice)
244{
245 struct cxl_afu *afu;
246
247 if (!(afu = kzalloc(sizeof(struct cxl_afu), GFP_KERNEL)))
248 return NULL;
249
250 afu->adapter = adapter;
251 afu->dev.parent = &adapter->dev;
252 afu->dev.release = cxl_ops->release_afu;
253 afu->slice = slice;
254 idr_init(&afu->contexts_idr);
255 mutex_init(&afu->contexts_lock);
256 spin_lock_init(&afu->afu_cntl_lock);
257 atomic_set(&afu->configured_state, -1);
258 afu->prefault_mode = CXL_PREFAULT_NONE;
259 afu->irqs_max = afu->adapter->user_irqs;
260
261 return afu;
262}
263
264int cxl_afu_select_best_mode(struct cxl_afu *afu)
265{
266 if (afu->modes_supported & CXL_MODE_DIRECTED)
267 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DIRECTED);
268
269 if (afu->modes_supported & CXL_MODE_DEDICATED)
270 return cxl_ops->afu_activate_mode(afu, CXL_MODE_DEDICATED);
271
272 dev_warn(&afu->dev, "No supported programming modes available\n");
273
274 return 0;
275}
276
277int cxl_adapter_context_get(struct cxl *adapter)
278{
279 int rc;
280
281 rc = atomic_inc_unless_negative(&adapter->contexts_num);
282 return rc ? 0 : -EBUSY;
283}
284
285void cxl_adapter_context_put(struct cxl *adapter)
286{
287 atomic_dec_if_positive(&adapter->contexts_num);
288}
289
290int cxl_adapter_context_lock(struct cxl *adapter)
291{
292 int rc;
293
294 rc = atomic_cmpxchg(&adapter->contexts_num, 0, -1);
295 return rc ? -EBUSY : 0;
296}
297
298void cxl_adapter_context_unlock(struct cxl *adapter)
299{
300 int val = atomic_cmpxchg(&adapter->contexts_num, -1, 0);
301
302
303
304
305
306
307
308 if (val != -1) {
309 atomic_set(&adapter->contexts_num, 0);
310 WARN(1, "Adapter context unlocked with %d active contexts",
311 val);
312 }
313}
314
315static int __init init_cxl(void)
316{
317 int rc = 0;
318
319 if (!tlbie_capable)
320 return -EINVAL;
321
322 if ((rc = cxl_file_init()))
323 return rc;
324
325 cxl_debugfs_init();
326
327
328
329
330
331 if (cxl_is_power8()) {
332 rc = register_cxl_calls(&cxl_calls);
333 if (rc)
334 goto err;
335 }
336
337 if (cpu_has_feature(CPU_FTR_HVMODE)) {
338 cxl_ops = &cxl_native_ops;
339 rc = pci_register_driver(&cxl_pci_driver);
340 }
341#ifdef CONFIG_PPC_PSERIES
342 else {
343 cxl_ops = &cxl_guest_ops;
344 rc = platform_driver_register(&cxl_of_driver);
345 }
346#endif
347 if (rc)
348 goto err1;
349
350 return 0;
351err1:
352 if (cxl_is_power8())
353 unregister_cxl_calls(&cxl_calls);
354err:
355 cxl_debugfs_exit();
356 cxl_file_exit();
357
358 return rc;
359}
360
361static void exit_cxl(void)
362{
363 if (cpu_has_feature(CPU_FTR_HVMODE))
364 pci_unregister_driver(&cxl_pci_driver);
365#ifdef CONFIG_PPC_PSERIES
366 else
367 platform_driver_unregister(&cxl_of_driver);
368#endif
369
370 cxl_debugfs_exit();
371 cxl_file_exit();
372 if (cxl_is_power8())
373 unregister_cxl_calls(&cxl_calls);
374 idr_destroy(&cxl_adapter_idr);
375}
376
377module_init(init_cxl);
378module_exit(exit_cxl);
379
380MODULE_DESCRIPTION("IBM Coherent Accelerator");
381MODULE_AUTHOR("Ian Munsie <imunsie@au1.ibm.com>");
382MODULE_LICENSE("GPL");
383
