1
2
3
4
5
6
7
8#ifndef GAUDIP_H_
9#define GAUDIP_H_
10
11#include <uapi/misc/habanalabs.h>
12#include "../common/habanalabs.h"
13#include "../include/common/hl_boot_if.h"
14#include "../include/gaudi/gaudi_packets.h"
15#include "../include/gaudi/gaudi.h"
16#include "../include/gaudi/gaudi_async_events.h"
17#include "../include/gaudi/gaudi_fw_if.h"
18
19#define NUMBER_OF_EXT_HW_QUEUES 8
20#define NUMBER_OF_CMPLT_QUEUES NUMBER_OF_EXT_HW_QUEUES
21#define NUMBER_OF_CPU_HW_QUEUES 1
22#define NUMBER_OF_INT_HW_QUEUES 100
23#define NUMBER_OF_HW_QUEUES (NUMBER_OF_EXT_HW_QUEUES + \
24 NUMBER_OF_CPU_HW_QUEUES + \
25 NUMBER_OF_INT_HW_QUEUES)
26
27
28#define NUMBER_OF_COLLECTIVE_QUEUES 12
29#define NUMBER_OF_SOBS_IN_GRP 11
30
31
32
33
34
35
36#define NUMBER_OF_INTERRUPTS (NUMBER_OF_CMPLT_QUEUES + \
37 NUMBER_OF_CPU_HW_QUEUES)
38
39#define GAUDI_STREAM_MASTER_ARR_SIZE 8
40
41#if (NUMBER_OF_INTERRUPTS > GAUDI_MSI_ENTRIES)
42#error "Number of MSI interrupts must be smaller or equal to GAUDI_MSI_ENTRIES"
43#endif
44
45#define CORESIGHT_TIMEOUT_USEC 100000
46
47#define GAUDI_MAX_CLK_FREQ 2200000000ull
48
49#define MAX_POWER_DEFAULT_PCI 200000
50#define MAX_POWER_DEFAULT_PMC 350000
51
52#define DC_POWER_DEFAULT_PCI 60000
53#define DC_POWER_DEFAULT_PMC 60000
54
55#define DC_POWER_DEFAULT_PMC_SEC 97000
56
57#define GAUDI_CPU_TIMEOUT_USEC 30000000
58
59#define TPC_ENABLED_MASK 0xFF
60
61#define GAUDI_HBM_SIZE_32GB 0x800000000ull
62#define GAUDI_HBM_DEVICES 4
63#define GAUDI_HBM_CHANNELS 8
64#define GAUDI_HBM_CFG_BASE (mmHBM0_BASE - CFG_BASE)
65#define GAUDI_HBM_CFG_OFFSET (mmHBM1_BASE - mmHBM0_BASE)
66
67#define DMA_MAX_TRANSFER_SIZE U32_MAX
68
69#define GAUDI_DEFAULT_CARD_NAME "HL205"
70
71#define GAUDI_MAX_PENDING_CS SZ_16K
72
73#if !IS_MAX_PENDING_CS_VALID(GAUDI_MAX_PENDING_CS)
74#error "GAUDI_MAX_PENDING_CS must be power of 2 and greater than 1"
75#endif
76
77#define PCI_DMA_NUMBER_OF_CHNLS 2
78#define HBM_DMA_NUMBER_OF_CHNLS 6
79#define DMA_NUMBER_OF_CHNLS (PCI_DMA_NUMBER_OF_CHNLS + \
80 HBM_DMA_NUMBER_OF_CHNLS)
81
82#define MME_NUMBER_OF_SLAVE_ENGINES 2
83#define MME_NUMBER_OF_ENGINES (MME_NUMBER_OF_MASTER_ENGINES + \
84 MME_NUMBER_OF_SLAVE_ENGINES)
85#define MME_NUMBER_OF_QMANS (MME_NUMBER_OF_MASTER_ENGINES * \
86 QMAN_STREAMS)
87
88#define QMAN_STREAMS 4
89#define PQ_FETCHER_CACHE_SIZE 8
90
91#define DMA_QMAN_OFFSET (mmDMA1_QM_BASE - mmDMA0_QM_BASE)
92#define TPC_QMAN_OFFSET (mmTPC1_QM_BASE - mmTPC0_QM_BASE)
93#define MME_QMAN_OFFSET (mmMME1_QM_BASE - mmMME0_QM_BASE)
94#define NIC_MACRO_QMAN_OFFSET (mmNIC1_QM0_BASE - mmNIC0_QM0_BASE)
95#define NIC_ENGINE_QMAN_OFFSET (mmNIC0_QM1_BASE - mmNIC0_QM0_BASE)
96
97#define TPC_CFG_OFFSET (mmTPC1_CFG_BASE - mmTPC0_CFG_BASE)
98
99#define DMA_CORE_OFFSET (mmDMA1_CORE_BASE - mmDMA0_CORE_BASE)
100
101#define QMAN_LDMA_SRC_OFFSET (mmDMA0_CORE_SRC_BASE_LO - mmDMA0_CORE_CFG_0)
102#define QMAN_LDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
103#define QMAN_LDMA_SIZE_OFFSET (mmDMA0_CORE_DST_TSIZE_0 - mmDMA0_CORE_CFG_0)
104
105#define QMAN_CPDMA_SRC_OFFSET (mmDMA0_QM_CQ_PTR_LO_4 - mmDMA0_CORE_CFG_0)
106#define QMAN_CPDMA_DST_OFFSET (mmDMA0_CORE_DST_BASE_LO - mmDMA0_CORE_CFG_0)
107#define QMAN_CPDMA_SIZE_OFFSET (mmDMA0_QM_CQ_TSIZE_4 - mmDMA0_CORE_CFG_0)
108
109#define SIF_RTR_CTRL_OFFSET (mmSIF_RTR_CTRL_1_BASE - mmSIF_RTR_CTRL_0_BASE)
110
111#define NIF_RTR_CTRL_OFFSET (mmNIF_RTR_CTRL_1_BASE - mmNIF_RTR_CTRL_0_BASE)
112
113#define MME_ACC_OFFSET (mmMME1_ACC_BASE - mmMME0_ACC_BASE)
114#define SRAM_BANK_OFFSET (mmSRAM_Y0_X1_RTR_BASE - mmSRAM_Y0_X0_RTR_BASE)
115
116#define NUM_OF_SOB_IN_BLOCK \
117 (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_2047 - \
118 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0) + 4) >> 2)
119
120#define NUM_OF_MONITORS_IN_BLOCK \
121 (((mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_511 - \
122 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_MON_STATUS_0) + 4) >> 2)
123
124#define MONITOR_MAX_SOBS 8
125
126
127
128#define CPU_FW_IMAGE_SIZE 0x10000000
129#define MMU_PAGE_TABLES_SIZE 0x0BF00000
130#define MMU_CACHE_MNG_SIZE 0x00100000
131#define RESERVED 0x04000000
132
133#define CPU_FW_IMAGE_ADDR DRAM_PHYS_BASE
134#define MMU_PAGE_TABLES_ADDR (CPU_FW_IMAGE_ADDR + CPU_FW_IMAGE_SIZE)
135#define MMU_CACHE_MNG_ADDR (MMU_PAGE_TABLES_ADDR + MMU_PAGE_TABLES_SIZE)
136
137#define DRAM_DRIVER_END_ADDR (MMU_CACHE_MNG_ADDR + MMU_CACHE_MNG_SIZE +\
138 RESERVED)
139
140#define DRAM_BASE_ADDR_USER 0x20000000
141
142#if (DRAM_DRIVER_END_ADDR > DRAM_BASE_ADDR_USER)
143#error "Driver must reserve no more than 512MB"
144#endif
145
146
147
148#define MME_QMAN_LENGTH 1024
149#define MME_QMAN_SIZE_IN_BYTES (MME_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
150
151#define HBM_DMA_QMAN_LENGTH 1024
152#define HBM_DMA_QMAN_SIZE_IN_BYTES \
153 (HBM_DMA_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
154
155#define TPC_QMAN_LENGTH 1024
156#define TPC_QMAN_SIZE_IN_BYTES (TPC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
157
158#define NIC_QMAN_LENGTH 1024
159#define NIC_QMAN_SIZE_IN_BYTES (NIC_QMAN_LENGTH * QMAN_PQ_ENTRY_SIZE)
160
161
162#define SRAM_USER_BASE_OFFSET GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START
163
164
165#define VA_HOST_SPACE_START 0x1000000000000ull
166#define VA_HOST_SPACE_END 0x3FF8000000000ull
167#define VA_HOST_SPACE_SIZE (VA_HOST_SPACE_END - \
168 VA_HOST_SPACE_START)
169#define HOST_SPACE_INTERNAL_CB_SZ SZ_2M
170
171#define HW_CAP_PLL BIT(0)
172#define HW_CAP_HBM BIT(1)
173#define HW_CAP_MMU BIT(2)
174#define HW_CAP_MME BIT(3)
175#define HW_CAP_CPU BIT(4)
176#define HW_CAP_PCI_DMA BIT(5)
177#define HW_CAP_MSI BIT(6)
178#define HW_CAP_CPU_Q BIT(7)
179#define HW_CAP_HBM_DMA BIT(8)
180#define HW_CAP_CLK_GATE BIT(9)
181#define HW_CAP_SRAM_SCRAMBLER BIT(10)
182#define HW_CAP_HBM_SCRAMBLER BIT(11)
183
184#define HW_CAP_NIC0 BIT(14)
185#define HW_CAP_NIC1 BIT(15)
186#define HW_CAP_NIC2 BIT(16)
187#define HW_CAP_NIC3 BIT(17)
188#define HW_CAP_NIC4 BIT(18)
189#define HW_CAP_NIC5 BIT(19)
190#define HW_CAP_NIC6 BIT(20)
191#define HW_CAP_NIC7 BIT(21)
192#define HW_CAP_NIC8 BIT(22)
193#define HW_CAP_NIC9 BIT(23)
194#define HW_CAP_NIC_MASK GENMASK(23, 14)
195#define HW_CAP_NIC_SHIFT 14
196
197#define HW_CAP_TPC0 BIT(24)
198#define HW_CAP_TPC1 BIT(25)
199#define HW_CAP_TPC2 BIT(26)
200#define HW_CAP_TPC3 BIT(27)
201#define HW_CAP_TPC4 BIT(28)
202#define HW_CAP_TPC5 BIT(29)
203#define HW_CAP_TPC6 BIT(30)
204#define HW_CAP_TPC7 BIT(31)
205#define HW_CAP_TPC_MASK GENMASK(31, 24)
206#define HW_CAP_TPC_SHIFT 24
207
208#define NEXT_SYNC_OBJ_ADDR_INTERVAL \
209 (mmSYNC_MNGR_W_N_SYNC_MNGR_OBJS_SOB_OBJ_0 - \
210 mmSYNC_MNGR_E_N_SYNC_MNGR_OBJS_SOB_OBJ_0)
211#define NUM_OF_MME_ENGINES 2
212#define NUM_OF_MME_SUB_ENGINES 2
213#define NUM_OF_TPC_ENGINES 8
214#define NUM_OF_DMA_ENGINES 8
215#define NUM_OF_QUEUES 5
216#define NUM_OF_STREAMS 4
217#define NUM_OF_FENCES 4
218
219
220#define GAUDI_CPU_PCI_MSB_ADDR(addr) (((addr) & GENMASK_ULL(49, 39)) >> 39)
221#define GAUDI_PCI_TO_CPU_ADDR(addr) \
222 do { \
223 (addr) &= ~GENMASK_ULL(49, 39); \
224 (addr) |= BIT_ULL(39); \
225 } while (0)
226#define GAUDI_CPU_TO_PCI_ADDR(addr, extension) \
227 do { \
228 (addr) &= ~GENMASK_ULL(49, 39); \
229 (addr) |= (u64) (extension) << 39; \
230 } while (0)
231
232enum gaudi_dma_channels {
233 GAUDI_PCI_DMA_1,
234 GAUDI_PCI_DMA_2,
235 GAUDI_HBM_DMA_1,
236 GAUDI_HBM_DMA_2,
237 GAUDI_HBM_DMA_3,
238 GAUDI_HBM_DMA_4,
239 GAUDI_HBM_DMA_5,
240 GAUDI_HBM_DMA_6,
241 GAUDI_DMA_MAX
242};
243
244enum gaudi_tpc_mask {
245 GAUDI_TPC_MASK_TPC0 = 0x01,
246 GAUDI_TPC_MASK_TPC1 = 0x02,
247 GAUDI_TPC_MASK_TPC2 = 0x04,
248 GAUDI_TPC_MASK_TPC3 = 0x08,
249 GAUDI_TPC_MASK_TPC4 = 0x10,
250 GAUDI_TPC_MASK_TPC5 = 0x20,
251 GAUDI_TPC_MASK_TPC6 = 0x40,
252 GAUDI_TPC_MASK_TPC7 = 0x80,
253 GAUDI_TPC_MASK_ALL = 0xFF
254};
255
256enum gaudi_nic_mask {
257 GAUDI_NIC_MASK_NIC0 = 0x01,
258 GAUDI_NIC_MASK_NIC1 = 0x02,
259 GAUDI_NIC_MASK_NIC2 = 0x04,
260 GAUDI_NIC_MASK_NIC3 = 0x08,
261 GAUDI_NIC_MASK_NIC4 = 0x10,
262 GAUDI_NIC_MASK_NIC5 = 0x20,
263 GAUDI_NIC_MASK_NIC6 = 0x40,
264 GAUDI_NIC_MASK_NIC7 = 0x80,
265 GAUDI_NIC_MASK_NIC8 = 0x100,
266 GAUDI_NIC_MASK_NIC9 = 0x200,
267 GAUDI_NIC_MASK_ALL = 0x3FF
268};
269
270
271
272
273
274
275
276
277struct gaudi_hw_sob_group {
278 struct hl_device *hdev;
279 struct kref kref;
280 u32 base_sob_id;
281 u32 queue_id;
282};
283
284#define NUM_SOB_GROUPS (HL_RSVD_SOBS * QMAN_STREAMS)
285
286
287
288
289
290
291
292
293struct gaudi_collective_properties {
294 struct gaudi_hw_sob_group hw_sob_group[NUM_SOB_GROUPS];
295 u16 next_sob_group_val[QMAN_STREAMS];
296 u8 curr_sob_group_idx[QMAN_STREAMS];
297 u8 mstr_sob_mask[HL_COLLECTIVE_RSVD_MSTR_MONS];
298};
299
300
301
302
303
304
305
306struct gaudi_internal_qman_info {
307 void *pq_kernel_addr;
308 dma_addr_t pq_dma_addr;
309 size_t pq_size;
310};
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336struct gaudi_device {
337 int (*cpucp_info_get)(struct hl_device *hdev);
338
339
340 spinlock_t hw_queues_lock;
341 struct mutex clk_gate_mutex;
342
343 struct gaudi_internal_qman_info internal_qmans[GAUDI_QUEUE_ID_SIZE];
344
345 struct gaudi_collective_properties collective_props;
346
347 u64 hbm_bar_cur_addr;
348 u64 max_freq_value;
349
350 u32 events[GAUDI_EVENT_SIZE];
351 u32 events_stat[GAUDI_EVENT_SIZE];
352 u32 events_stat_aggregate[GAUDI_EVENT_SIZE];
353 u32 hw_cap_initialized;
354 u8 multi_msi_mode;
355 u8 mmu_cache_inv_pi;
356};
357
358void gaudi_init_security(struct hl_device *hdev);
359void gaudi_ack_protection_bits_errors(struct hl_device *hdev);
360void gaudi_add_device_attr(struct hl_device *hdev,
361 struct attribute_group *dev_attr_grp);
362void gaudi_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
363int gaudi_debug_coresight(struct hl_device *hdev, void *data);
364void gaudi_halt_coresight(struct hl_device *hdev);
365int gaudi_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
366void gaudi_mmu_prepare_reg(struct hl_device *hdev, u64 reg, u32 asid);
367
368#endif
369