1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2018-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8#ifndef HL_BOOT_IF_H 9#define HL_BOOT_IF_H 10 11#define LKD_HARD_RESET_MAGIC 0xED7BD694 /* deprecated - do not use */ 12#define HL_POWER9_HOST_MAGIC 0x1DA30009 13 14#define BOOT_FIT_SRAM_OFFSET 0x200000 15 16#define VERSION_MAX_LEN 128 17 18/* 19 * CPU error bits in BOOT_ERROR registers 20 * 21 * CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed. 22 * DRAM is not reliable to use. 23 * 24 * CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the 25 * image provided by the host has failed. 26 * 27 * CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed. 28 * Boot continues as usual, but keep in 29 * mind this is a warning. 30 * 31 * CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped. 32 * Skipping DRAM initialization has been 33 * requested (e.g. strap, command, etc.) 34 * and FW skipped the DRAM initialization. 35 * Host can initialize the DRAM. 36 * 37 * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped. 38 * Meaning the BMC data might not be 39 * available until reset. 40 * 41 * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready. 42 * BMC has not provided the NIC data yet. 43 * Once provided this bit will be cleared. 44 * 45 * CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed. 46 * The NIC FW loading and initialization 47 * failed. This means NICs are not usable. 48 * 49 * CPU_BOOT_ERR0_SECURITY_NOT_RDY Chip security initialization has been 50 * started, but is not ready yet - chip 51 * cannot be accessed. 52 * 53 * CPU_BOOT_ERR0_SECURITY_FAIL Security related tasks have failed. 54 * The tasks are security init (root of 55 * trust), boot authentication (chain of 56 * trust), data packets authentication. 57 * 58 * CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed. 59 * The PCI device ID might be wrong. 60 * 61 * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed. 62 * It mean that ppboot checksum 63 * verification for the preboot primary 64 * image has failed to match expected 65 * checksum. Trying to program image again 66 * might solve this. 67 * 68 * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed. 69 * It mean that ppboot checksum 70 * verification for the preboot secondary 71 * image has failed to match expected 72 * checksum. Trying to program image again 73 * might solve this. 74 * 75 * CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one 76 * of the PLLs remains in REF_CLK 77 * 78 * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL Device is unusable and customer support 79 * should be contacted. 80 * 81 * CPU_BOOT_ERR0_ARC0_HALT_ACK_NOT_RCVD HALT ACK from ARC0 is not received 82 * within specified retries after issuing 83 * HALT request. ARC0 appears to be in bad 84 * reset. 85 * 86 * CPU_BOOT_ERR0_ARC1_HALT_ACK_NOT_RCVD HALT ACK from ARC1 is not received 87 * within specified retries after issuing 88 * HALT request. ARC1 appears to be in bad 89 * reset. 90 * 91 * CPU_BOOT_ERR0_ARC0_RUN_ACK_NOT_RCVD RUN ACK from ARC0 is not received 92 * within specified timeout after issuing 93 * RUN request. ARC0 appears to be in bad 94 * reset. 95 * 96 * CPU_BOOT_ERR0_ARC1_RUN_ACK_NOT_RCVD RUN ACK from ARC1 is not received 97 * within specified timeout after issuing 98 * RUN request. ARC1 appears to be in bad 99 * reset. 100 * 101 * CPU_BOOT_ERR0_ENABLED Error registers enabled. 102 * This is a main indication that the 103 * running FW populates the error 104 * registers. Meaning the error bits are 105 * not garbage, but actual error statuses. 106 */ 107#define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << 0) 108#define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << 1) 109#define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << 2) 110#define CPU_BOOT_ERR0_DRAM_SKIPPED (1 << 3) 111#define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED (1 << 4) 112#define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY (1 << 5) 113#define CPU_BOOT_ERR0_NIC_FW_FAIL (1 << 6) 114#define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << 7) 115#define CPU_BOOT_ERR0_SECURITY_FAIL (1 << 8) 116#define CPU_BOOT_ERR0_EFUSE_FAIL (1 << 9) 117#define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL (1 << 10) 118#define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL (1 << 11) 119#define CPU_BOOT_ERR0_PLL_FAIL (1 << 12) 120#define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << 13) 121#define CPU_BOOT_ERR0_ARC0_HALT_ACK_NOT_RCVD (1 << 14) 122#define CPU_BOOT_ERR0_ARC1_HALT_ACK_NOT_RCVD (1 << 15) 123#define CPU_BOOT_ERR0_ARC0_RUN_ACK_NOT_RCVD (1 << 16) 124#define CPU_BOOT_ERR0_ARC1_RUN_ACK_NOT_RCVD (1 << 17) 125#define CPU_BOOT_ERR0_ENABLED (1 << 31) 126#define CPU_BOOT_ERR1_ENABLED (1 << 31) 127 128/* 129 * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers 130 * 131 * CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled. 132 * This is an indication for security 133 * enabled in FW, which means that 134 * all conditions for security are met: 135 * device is indicated as security enabled, 136 * registers are protected, and device 137 * uses keys for image verification. 138 * Initialized in: preboot 139 * 140 * CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled. 141 * Enabled when JTAG or DEBUG is enabled 142 * in FW. 143 * Initialized in: preboot 144 * 145 * CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled. 146 * Watchdog is enabled in FW. 147 * Initialized in: preboot 148 * 149 * CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled. 150 * DRAM initialization has been done in FW. 151 * Initialized in: u-boot 152 * 153 * CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled. 154 * If set, it means that during boot, 155 * FW waited for BMC data. 156 * Initialized in: u-boot 157 * 158 * CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized. 159 * FW initialized E2E credits. 160 * Initialized in: u-boot 161 * 162 * CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized. 163 * FW initialized HBM credits. 164 * Initialized in: u-boot 165 * 166 * CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized. 167 * FW initialized rate limiter. 168 * Initialized in: u-boot 169 * 170 * CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled. 171 * FW initialized SRAM scrambler. 172 * Initialized in: linux 173 * 174 * CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled. 175 * FW initialized DRAM scrambler. 176 * Initialized in: u-boot 177 * 178 * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled. 179 * FW has the hard reset procedure 180 * implemented. This means that FW will 181 * perform hard reset procedure on 182 * receiving the halt-machine event. 183 * Initialized in: preboot, u-boot, linux 184 * 185 * CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled. 186 * Initialized in: linux 187 * 188 * CPU_BOOT_DEV_STS0_SP_SRAM_EN SP SRAM is initialized and available 189 * for use. 190 * Initialized in: preboot 191 * 192 * CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled. 193 * FW initialized Clock Gating. 194 * Initialized in: preboot 195 * 196 * CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled. 197 * FW handles HBM ECC indications. 198 * Initialized in: linux 199 * 200 * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN Packets ack value used in the armcpd 201 * is set to the PI counter. 202 * Initialized in: linux 203 * 204 * CPU_BOOT_DEV_STS0_FW_LD_COM_EN Flexible FW loading communication 205 * protocol is enabled. 206 * Initialized in: preboot 207 * 208 * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled. 209 * This bit if set, means the iATU has been 210 * configured and is ready for use. 211 * Initialized in: ppboot 212 * 213 * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN NIC MAC channels init is done by FW and 214 * any access to them is done via the FW. 215 * Initialized in: linux 216 * 217 * CPU_BOOT_DEV_STS0_DYN_PLL_EN Dynamic PLL configuration is enabled. 218 * FW sends to host a bitmap of supported 219 * PLLs. 220 * Initialized in: linux 221 * 222 * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN GIC access permission only from 223 * previleged entity. FW sets this status 224 * bit for host. If this bit is set then 225 * GIC can not be accessed from host. 226 * Initialized in: linux 227 * 228 * CPU_BOOT_DEV_STS0_EQ_INDEX_EN Event Queue (EQ) index is a running 229 * index for each new event sent to host. 230 * This is used as a method in host to 231 * identify that the waiting event in 232 * queue is actually a new event which 233 * was not served before. 234 * Initialized in: linux 235 * 236 * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN Use multiple scratchpad interfaces to 237 * prevent IRQs overriding each other. 238 * Initialized in: linux 239 * 240 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN 241 * NIC STAT and XPCS91 access is restricted 242 * and is done via FW only. 243 * Initialized in: linux 244 * 245 * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN 246 * NIC STAT get all is supported. 247 * Initialized in: linux 248 * 249 * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN 250 * F/W checks if the device is idle by reading defined set 251 * of registers. It returns a bitmask of all the engines, 252 * where a bit is set if the engine is not idle. 253 * Initialized in: linux 254 * 255 * CPU_BOOT_DEV_STS0_ENABLED Device status register enabled. 256 * This is a main indication that the 257 * running FW populates the device status 258 * register. Meaning the device status 259 * bits are not garbage, but actual 260 * statuses. 261 * Initialized in: preboot 262 * 263 */ 264#define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << 0) 265#define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << 1) 266#define CPU_BOOT_DEV_STS0_WATCHDOG_EN (1 << 2) 267#define CPU_BOOT_DEV_STS0_DRAM_INIT_EN (1 << 3) 268#define CPU_BOOT_DEV_STS0_BMC_WAIT_EN (1 << 4) 269#define CPU_BOOT_DEV_STS0_E2E_CRED_EN (1 << 5) 270#define CPU_BOOT_DEV_STS0_HBM_CRED_EN (1 << 6) 271#define CPU_BOOT_DEV_STS0_RL_EN (1 << 7) 272#define CPU_BOOT_DEV_STS0_SRAM_SCR_EN (1 << 8) 273#define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << 9) 274#define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << 10) 275#define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << 11) 276#define CPU_BOOT_DEV_STS0_SP_SRAM_EN (1 << 12) 277#define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << 13) 278#define CPU_BOOT_DEV_STS0_HBM_ECC_EN (1 << 14) 279#define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN (1 << 15) 280#define CPU_BOOT_DEV_STS0_FW_LD_COM_EN (1 << 16) 281#define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << 17) 282#define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN (1 << 18) 283#define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << 19) 284#define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN (1 << 20) 285#define CPU_BOOT_DEV_STS0_EQ_INDEX_EN (1 << 21) 286#define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN (1 << 22) 287#define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN (1 << 23) 288#define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN (1 << 24) 289#define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN (1 << 25) 290#define CPU_BOOT_DEV_STS0_ENABLED (1 << 31) 291#define CPU_BOOT_DEV_STS1_ENABLED (1 << 31) 292 293enum cpu_boot_status { 294 CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */ 295 CPU_BOOT_STATUS_IN_WFE = 1, 296 CPU_BOOT_STATUS_DRAM_RDY = 2, 297 CPU_BOOT_STATUS_SRAM_AVAIL = 3, 298 CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */ 299 CPU_BOOT_STATUS_IN_PREBOOT = 5, 300 CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */ 301 CPU_BOOT_STATUS_IN_UBOOT = 7, 302 CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */ 303 CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */ 304 /* U-Boot console prompt activated, commands are not processed */ 305 CPU_BOOT_STATUS_UBOOT_NOT_READY = 10, 306 /* Finished NICs init, reported after DRAM and NICs */ 307 CPU_BOOT_STATUS_NIC_FW_RDY = 11, 308 CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */ 309 CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */ 310 CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */ 311 /* Last boot loader progress status, ready to receive commands */ 312 CPU_BOOT_STATUS_READY_TO_BOOT = 15, 313 /* Internal Boot finished, ready for boot-fit */ 314 CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16, 315 /* Internal Security has been initialized, device can be accessed */ 316 CPU_BOOT_STATUS_SECURITY_READY = 17, 317}; 318 319enum kmd_msg { 320 KMD_MSG_NA = 0, 321 KMD_MSG_GOTO_WFE, 322 KMD_MSG_FIT_RDY, 323 KMD_MSG_SKIP_BMC, 324 RESERVED, 325 KMD_MSG_RST_DEV, 326 KMD_MSG_LAST 327}; 328 329enum cpu_msg_status { 330 CPU_MSG_CLR = 0, 331 CPU_MSG_OK, 332 CPU_MSG_ERR, 333}; 334 335/* communication registers mapping - consider ABI when changing */ 336struct cpu_dyn_regs { 337 __le32 cpu_pq_base_addr_low; 338 __le32 cpu_pq_base_addr_high; 339 __le32 cpu_pq_length; 340 __le32 cpu_pq_init_status; 341 __le32 cpu_eq_base_addr_low; 342 __le32 cpu_eq_base_addr_high; 343 __le32 cpu_eq_length; 344 __le32 cpu_eq_ci; 345 __le32 cpu_cq_base_addr_low; 346 __le32 cpu_cq_base_addr_high; 347 __le32 cpu_cq_length; 348 __le32 cpu_pf_pq_pi; 349 __le32 cpu_boot_dev_sts0; 350 __le32 cpu_boot_dev_sts1; 351 __le32 cpu_boot_err0; 352 __le32 cpu_boot_err1; 353 __le32 cpu_boot_status; 354 __le32 fw_upd_sts; 355 __le32 fw_upd_cmd; 356 __le32 fw_upd_pending_sts; 357 __le32 fuse_ver_offset; 358 __le32 preboot_ver_offset; 359 __le32 uboot_ver_offset; 360 __le32 hw_state; 361 __le32 kmd_msg_to_cpu; 362 __le32 cpu_cmd_status_to_host; 363 __le32 gic_host_pi_upd_irq; 364 __le32 gic_tpc_qm_irq_ctrl; 365 __le32 gic_mme_qm_irq_ctrl; 366 __le32 gic_dma_qm_irq_ctrl; 367 __le32 gic_nic_qm_irq_ctrl; 368 __le32 gic_dma_core_irq_ctrl; 369 __le32 gic_host_halt_irq; 370 __le32 gic_host_ints_irq; 371 __le32 gic_host_soft_rst_irq; 372 __le32 gic_rot_qm_irq_ctrl; 373 __le32 reserved1[22]; /* reserve for future use */ 374}; 375 376/* TODO: remove the desc magic after the code is updated to use message */ 377/* HCDM - Habana Communications Descriptor Magic */ 378#define HL_COMMS_DESC_MAGIC 0x4843444D 379#define HL_COMMS_DESC_VER 1 380 381/* HCMv - Habana Communications Message + header version */ 382#define HL_COMMS_MSG_MAGIC_VALUE 0x48434D00 383#define HL_COMMS_MSG_MAGIC_MASK 0xFFFFFF00 384#define HL_COMMS_MSG_MAGIC_VER_MASK 0xFF 385 386#define HL_COMMS_MSG_MAGIC_VER(ver) (HL_COMMS_MSG_MAGIC_VALUE | \ 387 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 388#define HL_COMMS_MSG_MAGIC_V0 HL_COMMS_DESC_MAGIC 389#define HL_COMMS_MSG_MAGIC_V1 HL_COMMS_MSG_MAGIC_VER(1) 390 391#define HL_COMMS_MSG_MAGIC HL_COMMS_MSG_MAGIC_V1 392 393#define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic) \ 394 (((magic) & HL_COMMS_MSG_MAGIC_MASK) == \ 395 HL_COMMS_MSG_MAGIC_VALUE) 396 397#define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver) \ 398 (((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >= \ 399 ((ver) & HL_COMMS_MSG_MAGIC_VER_MASK)) 400 401#define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver) \ 402 (HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) && \ 403 HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver))) 404 405enum comms_msg_type { 406 HL_COMMS_DESC_TYPE = 0, 407 HL_COMMS_RESET_CAUSE_TYPE = 1, 408}; 409 410/* TODO: remove this struct after the code is updated to use message */ 411/* this is the comms descriptor header - meta data */ 412struct comms_desc_header { 413 __le32 magic; /* magic for validation */ 414 __le32 crc32; /* CRC32 of the descriptor w/o header */ 415 __le16 size; /* size of the descriptor w/o header */ 416 __u8 version; /* descriptor version */ 417 __u8 reserved[5]; /* pad to 64 bit */ 418}; 419 420/* this is the comms message header - meta data */ 421struct comms_msg_header { 422 __le32 magic; /* magic for validation */ 423 __le32 crc32; /* CRC32 of the message w/o header */ 424 __le16 size; /* size of the message w/o header */ 425 __u8 version; /* message payload version */ 426 __u8 type; /* message type */ 427 __u8 reserved[4]; /* pad to 64 bit */ 428}; 429 430/* this is the main FW descriptor - consider ABI when changing */ 431struct lkd_fw_comms_desc { 432 struct comms_desc_header header; 433 struct cpu_dyn_regs cpu_dyn_regs; 434 char fuse_ver[VERSION_MAX_LEN]; 435 char cur_fw_ver[VERSION_MAX_LEN]; 436 /* can be used for 1 more version w/o ABI change */ 437 char reserved0[VERSION_MAX_LEN]; 438 __le64 img_addr; /* address for next FW component load */ 439}; 440 441enum comms_reset_cause { 442 HL_RESET_CAUSE_UNKNOWN = 0, 443 HL_RESET_CAUSE_HEARTBEAT = 1, 444 HL_RESET_CAUSE_TDR = 2, 445}; 446 447/* TODO: remove define after struct name is aligned on all projects */ 448#define lkd_msg_comms lkd_fw_comms_msg 449 450/* this is the comms message descriptor */ 451struct lkd_fw_comms_msg { 452 struct comms_msg_header header; 453 /* union for future expantions of new messages */ 454 union { 455 struct { 456 struct cpu_dyn_regs cpu_dyn_regs; 457 char fuse_ver[VERSION_MAX_LEN]; 458 char cur_fw_ver[VERSION_MAX_LEN]; 459 /* can be used for 1 more version w/o ABI change */ 460 char reserved0[VERSION_MAX_LEN]; 461 /* address for next FW component load */ 462 __le64 img_addr; 463 }; 464 struct { 465 __u8 reset_cause; 466 }; 467 }; 468}; 469 470/* 471 * LKD commands: 472 * 473 * COMMS_NOOP Used to clear the command register and no actual 474 * command is send. 475 * 476 * COMMS_CLR_STS Clear status command - FW should clear the 477 * status register. Used for synchronization 478 * between the commands as part of the race free 479 * protocol. 480 * 481 * COMMS_RST_STATE Reset the current communication state which is 482 * kept by FW for proper responses. 483 * Should be used in the beginning of the 484 * communication cycle to clean any leftovers from 485 * previous communication attempts. 486 * 487 * COMMS_PREP_DESC Prepare descriptor for setting up the 488 * communication and other dynamic data: 489 * struct lkd_fw_comms_desc. 490 * This command has a parameter stating the next FW 491 * component size, so the FW can actually prepare a 492 * space for it and in the status response provide 493 * the descriptor offset. The Offset of the next FW 494 * data component is a part of the descriptor 495 * structure. 496 * 497 * COMMS_DATA_RDY The FW data has been uploaded and is ready for 498 * validation. 499 * 500 * COMMS_EXEC Execute the next FW component. 501 * 502 * COMMS_RST_DEV Reset the device. 503 * 504 * COMMS_GOTO_WFE Execute WFE command. Allowed only on non-secure 505 * devices. 506 * 507 * COMMS_SKIP_BMC Perform actions required for BMC-less servers. 508 * Do not wait for BMC response. 509 * 510 * COMMS_LOW_PLL_OPP Initialize PLLs for low OPP. 511 * 512 * COMMS_PREP_DESC_ELBI Same as COMMS_PREP_DESC only that the memory 513 * space is allocated in a ELBI access only 514 * address range. 515 * 516 */ 517enum comms_cmd { 518 COMMS_NOOP = 0, 519 COMMS_CLR_STS = 1, 520 COMMS_RST_STATE = 2, 521 COMMS_PREP_DESC = 3, 522 COMMS_DATA_RDY = 4, 523 COMMS_EXEC = 5, 524 COMMS_RST_DEV = 6, 525 COMMS_GOTO_WFE = 7, 526 COMMS_SKIP_BMC = 8, 527 COMMS_LOW_PLL_OPP = 9, 528 COMMS_PREP_DESC_ELBI = 10, 529 COMMS_INVLD_LAST 530}; 531 532#define COMMS_COMMAND_SIZE_SHIFT 0 533#define COMMS_COMMAND_SIZE_MASK 0x1FFFFFF 534#define COMMS_COMMAND_CMD_SHIFT 27 535#define COMMS_COMMAND_CMD_MASK 0xF8000000 536 537/* 538 * LKD command to FW register structure 539 * @size - FW component size 540 * @cmd - command from enum comms_cmd 541 */ 542struct comms_command { 543 union { /* bit fields are only for FW use */ 544 struct { 545 u32 size :25; /* 32MB max. */ 546 u32 reserved :2; 547 enum comms_cmd cmd :5; /* 32 commands */ 548 }; 549 __le32 val; 550 }; 551}; 552 553/* 554 * FW status 555 * 556 * COMMS_STS_NOOP Used to clear the status register and no actual 557 * status is provided. 558 * 559 * COMMS_STS_ACK Command has been received and recognized. 560 * 561 * COMMS_STS_OK Command execution has finished successfully. 562 * 563 * COMMS_STS_ERR Command execution was unsuccessful and resulted 564 * in error. 565 * 566 * COMMS_STS_VALID_ERR FW validation has failed. 567 * 568 * COMMS_STS_TIMEOUT_ERR Command execution has timed out. 569 */ 570enum comms_sts { 571 COMMS_STS_NOOP = 0, 572 COMMS_STS_ACK = 1, 573 COMMS_STS_OK = 2, 574 COMMS_STS_ERR = 3, 575 COMMS_STS_VALID_ERR = 4, 576 COMMS_STS_TIMEOUT_ERR = 5, 577 COMMS_STS_INVLD_LAST 578}; 579 580/* RAM types for FW components loading - defines the base address */ 581enum comms_ram_types { 582 COMMS_SRAM = 0, 583 COMMS_DRAM = 1, 584}; 585 586#define COMMS_STATUS_OFFSET_SHIFT 0 587#define COMMS_STATUS_OFFSET_MASK 0x03FFFFFF 588#define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2 589#define COMMS_STATUS_RAM_TYPE_SHIFT 26 590#define COMMS_STATUS_RAM_TYPE_MASK 0x0C000000 591#define COMMS_STATUS_STATUS_SHIFT 28 592#define COMMS_STATUS_STATUS_MASK 0xF0000000 593 594/* 595 * FW status to LKD register structure 596 * @offset - an offset from the base of the ram_type shifted right by 597 * 2 bits (always aligned to 32 bits). 598 * Allows a maximum addressable offset of 256MB from RAM base. 599 * Example: for real offset in RAM of 0x800000 (8MB), the value 600 * in offset field is (0x800000 >> 2) = 0x200000. 601 * @ram_type - the RAM type that should be used for offset from 602 * enum comms_ram_types 603 * @status - status from enum comms_sts 604 */ 605struct comms_status { 606 union { /* bit fields are only for FW use */ 607 struct { 608 u32 offset :26; 609 enum comms_ram_types ram_type :2; 610 enum comms_sts status :4; /* 16 statuses */ 611 }; 612 __le32 val; 613 }; 614}; 615 616#endif /* HL_BOOT_IF_H */ 617