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8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/iopoll.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/ioport.h>
17#include <linux/dma-mapping.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/mmc.h>
20#include <linux/mmc/sdio.h>
21#include <linux/mmc/slot-gpio.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/clk-provider.h>
25#include <linux/regulator/consumer.h>
26#include <linux/reset.h>
27#include <linux/interrupt.h>
28#include <linux/bitfield.h>
29#include <linux/pinctrl/consumer.h>
30
31#define DRIVER_NAME "meson-gx-mmc"
32
33#define SD_EMMC_CLOCK 0x0
34#define CLK_DIV_MASK GENMASK(5, 0)
35#define CLK_SRC_MASK GENMASK(7, 6)
36#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
37#define CLK_TX_PHASE_MASK GENMASK(11, 10)
38#define CLK_RX_PHASE_MASK GENMASK(13, 12)
39#define CLK_PHASE_0 0
40#define CLK_PHASE_180 2
41#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
42#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
43#define CLK_V2_ALWAYS_ON BIT(24)
44
45#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
46#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
47#define CLK_V3_ALWAYS_ON BIT(28)
48
49#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
50#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
51#define CLK_ALWAYS_ON(h) (h->data->always_on)
52
53#define SD_EMMC_DELAY 0x4
54#define SD_EMMC_ADJUST 0x8
55#define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
56#define ADJUST_DS_EN BIT(15)
57#define ADJUST_ADJ_EN BIT(13)
58
59#define SD_EMMC_DELAY1 0x4
60#define SD_EMMC_DELAY2 0x8
61#define SD_EMMC_V3_ADJUST 0xc
62
63#define SD_EMMC_CALOUT 0x10
64#define SD_EMMC_START 0x40
65#define START_DESC_INIT BIT(0)
66#define START_DESC_BUSY BIT(1)
67#define START_DESC_ADDR_MASK GENMASK(31, 2)
68
69#define SD_EMMC_CFG 0x44
70#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
71#define CFG_BUS_WIDTH_1 0x0
72#define CFG_BUS_WIDTH_4 0x1
73#define CFG_BUS_WIDTH_8 0x2
74#define CFG_DDR BIT(2)
75#define CFG_BLK_LEN_MASK GENMASK(7, 4)
76#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
77#define CFG_RC_CC_MASK GENMASK(15, 12)
78#define CFG_STOP_CLOCK BIT(22)
79#define CFG_CLK_ALWAYS_ON BIT(18)
80#define CFG_CHK_DS BIT(20)
81#define CFG_AUTO_CLK BIT(23)
82#define CFG_ERR_ABORT BIT(27)
83
84#define SD_EMMC_STATUS 0x48
85#define STATUS_BUSY BIT(31)
86#define STATUS_DESC_BUSY BIT(30)
87#define STATUS_DATI GENMASK(23, 16)
88
89#define SD_EMMC_IRQ_EN 0x4c
90#define IRQ_RXD_ERR_MASK GENMASK(7, 0)
91#define IRQ_TXD_ERR BIT(8)
92#define IRQ_DESC_ERR BIT(9)
93#define IRQ_RESP_ERR BIT(10)
94#define IRQ_CRC_ERR \
95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
96#define IRQ_RESP_TIMEOUT BIT(11)
97#define IRQ_DESC_TIMEOUT BIT(12)
98#define IRQ_TIMEOUTS \
99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
100#define IRQ_END_OF_CHAIN BIT(13)
101#define IRQ_RESP_STATUS BIT(14)
102#define IRQ_SDIO BIT(15)
103#define IRQ_EN_MASK \
104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
105 IRQ_SDIO)
106
107#define SD_EMMC_CMD_CFG 0x50
108#define SD_EMMC_CMD_ARG 0x54
109#define SD_EMMC_CMD_DAT 0x58
110#define SD_EMMC_CMD_RSP 0x5c
111#define SD_EMMC_CMD_RSP1 0x60
112#define SD_EMMC_CMD_RSP2 0x64
113#define SD_EMMC_CMD_RSP3 0x68
114
115#define SD_EMMC_RXD 0x94
116#define SD_EMMC_TXD 0x94
117#define SD_EMMC_LAST_REG SD_EMMC_TXD
118
119#define SD_EMMC_SRAM_DATA_BUF_LEN 1536
120#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
121
122#define SD_EMMC_CFG_BLK_SIZE 512
123#define SD_EMMC_CFG_RESP_TIMEOUT 256
124#define SD_EMMC_CMD_TIMEOUT 1024
125#define SD_EMMC_CMD_TIMEOUT_DATA 4096
126#define SD_EMMC_CFG_CMD_GAP 16
127#define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
128
129#define SD_EMMC_PRE_REQ_DONE BIT(0)
130#define SD_EMMC_DESC_CHAIN_MODE BIT(1)
131
132#define MUX_CLK_NUM_PARENTS 2
133
134struct meson_mmc_data {
135 unsigned int tx_delay_mask;
136 unsigned int rx_delay_mask;
137 unsigned int always_on;
138 unsigned int adjust;
139};
140
141struct sd_emmc_desc {
142 u32 cmd_cfg;
143 u32 cmd_arg;
144 u32 cmd_data;
145 u32 cmd_resp;
146};
147
148struct meson_host {
149 struct device *dev;
150 struct meson_mmc_data *data;
151 struct mmc_host *mmc;
152 struct mmc_command *cmd;
153
154 void __iomem *regs;
155 struct clk *core_clk;
156 struct clk *mux_clk;
157 struct clk *mmc_clk;
158 unsigned long req_rate;
159 bool ddr;
160
161 bool dram_access_quirk;
162
163 struct pinctrl *pinctrl;
164 struct pinctrl_state *pins_clk_gate;
165
166 unsigned int bounce_buf_size;
167 void *bounce_buf;
168 void __iomem *bounce_iomem_buf;
169 dma_addr_t bounce_dma_addr;
170 struct sd_emmc_desc *descs;
171 dma_addr_t descs_dma_addr;
172
173 int irq;
174
175 bool vqmmc_enabled;
176};
177
178#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
179#define CMD_CFG_BLOCK_MODE BIT(9)
180#define CMD_CFG_R1B BIT(10)
181#define CMD_CFG_END_OF_CHAIN BIT(11)
182#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
183#define CMD_CFG_NO_RESP BIT(16)
184#define CMD_CFG_NO_CMD BIT(17)
185#define CMD_CFG_DATA_IO BIT(18)
186#define CMD_CFG_DATA_WR BIT(19)
187#define CMD_CFG_RESP_NOCRC BIT(20)
188#define CMD_CFG_RESP_128 BIT(21)
189#define CMD_CFG_RESP_NUM BIT(22)
190#define CMD_CFG_DATA_NUM BIT(23)
191#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
192#define CMD_CFG_ERROR BIT(30)
193#define CMD_CFG_OWNER BIT(31)
194
195#define CMD_DATA_MASK GENMASK(31, 2)
196#define CMD_DATA_BIG_ENDIAN BIT(1)
197#define CMD_DATA_SRAM BIT(0)
198#define CMD_RESP_MASK GENMASK(31, 1)
199#define CMD_RESP_SRAM BIT(0)
200
201static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
202{
203 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
204
205 if (!timeout)
206 return SD_EMMC_CMD_TIMEOUT_DATA;
207
208 timeout = roundup_pow_of_two(timeout);
209
210 return min(timeout, 32768U);
211}
212
213static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
214{
215 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
216 return cmd->mrq->cmd;
217 else if (mmc_op_multi(cmd->opcode) &&
218 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
219 return cmd->mrq->stop;
220 else
221 return NULL;
222}
223
224static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
225 struct mmc_request *mrq)
226{
227 struct meson_host *host = mmc_priv(mmc);
228 struct mmc_data *data = mrq->data;
229 struct scatterlist *sg;
230 int i;
231
232
233
234
235
236
237 if (host->dram_access_quirk)
238 return;
239
240
241 if (data->blocks > 1 || mrq->cmd->opcode == SD_IO_RW_EXTENDED) {
242
243
244
245
246
247
248
249
250 for_each_sg(data->sg, sg, data->sg_len, i) {
251 if (sg->length % data->blksz) {
252 dev_warn_once(mmc_dev(mmc),
253 "unaligned sg len %u blksize %u, disabling descriptor DMA for transfer\n",
254 sg->length, data->blksz);
255 return;
256 }
257 }
258 }
259
260 for_each_sg(data->sg, sg, data->sg_len, i) {
261
262 if (sg->offset % 8) {
263 dev_warn_once(mmc_dev(mmc),
264 "unaligned sg offset %u, disabling descriptor DMA for transfer\n",
265 sg->offset);
266 return;
267 }
268 }
269
270 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
271}
272
273static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
274{
275 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
276}
277
278static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
279{
280 return data && data->flags & MMC_DATA_READ &&
281 !meson_mmc_desc_chain_mode(data);
282}
283
284static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
285{
286 struct mmc_data *data = mrq->data;
287
288 if (!data)
289 return;
290
291 meson_mmc_get_transfer_mode(mmc, mrq);
292 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
293
294 if (!meson_mmc_desc_chain_mode(data))
295 return;
296
297 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
298 mmc_get_dma_dir(data));
299 if (!data->sg_count)
300 dev_err(mmc_dev(mmc), "dma_map_sg failed");
301}
302
303static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
304 int err)
305{
306 struct mmc_data *data = mrq->data;
307
308 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
309 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
310 mmc_get_dma_dir(data));
311}
312
313
314
315
316
317
318
319static void meson_mmc_clk_gate(struct meson_host *host)
320{
321 u32 cfg;
322
323 if (host->pins_clk_gate) {
324 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
325 } else {
326
327
328
329
330 cfg = readl(host->regs + SD_EMMC_CFG);
331 cfg |= CFG_STOP_CLOCK;
332 writel(cfg, host->regs + SD_EMMC_CFG);
333 }
334}
335
336static void meson_mmc_clk_ungate(struct meson_host *host)
337{
338 u32 cfg;
339
340 if (host->pins_clk_gate)
341 pinctrl_select_default_state(host->dev);
342
343
344 cfg = readl(host->regs + SD_EMMC_CFG);
345 cfg &= ~CFG_STOP_CLOCK;
346 writel(cfg, host->regs + SD_EMMC_CFG);
347}
348
349static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
350 bool ddr)
351{
352 struct mmc_host *mmc = host->mmc;
353 int ret;
354 u32 cfg;
355
356
357 if (host->ddr == ddr && host->req_rate == rate)
358 return 0;
359
360
361 meson_mmc_clk_gate(host);
362 host->req_rate = 0;
363 mmc->actual_clock = 0;
364
365
366 if (!rate)
367 return 0;
368
369
370 cfg = readl(host->regs + SD_EMMC_CFG);
371 cfg |= CFG_STOP_CLOCK;
372 writel(cfg, host->regs + SD_EMMC_CFG);
373
374 if (ddr) {
375
376 rate <<= 1;
377 cfg |= CFG_DDR;
378 } else {
379 cfg &= ~CFG_DDR;
380 }
381 writel(cfg, host->regs + SD_EMMC_CFG);
382 host->ddr = ddr;
383
384 ret = clk_set_rate(host->mmc_clk, rate);
385 if (ret) {
386 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
387 rate, ret);
388 return ret;
389 }
390
391 host->req_rate = rate;
392 mmc->actual_clock = clk_get_rate(host->mmc_clk);
393
394
395 if (ddr) {
396 host->req_rate >>= 1;
397 mmc->actual_clock >>= 1;
398 }
399
400 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
401 if (rate != mmc->actual_clock)
402 dev_dbg(host->dev, "requested rate was %lu\n", rate);
403
404
405 meson_mmc_clk_ungate(host);
406
407 return 0;
408}
409
410
411
412
413
414
415static int meson_mmc_clk_init(struct meson_host *host)
416{
417 struct clk_init_data init;
418 struct clk_mux *mux;
419 struct clk_divider *div;
420 char clk_name[32];
421 int i, ret = 0;
422 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
423 const char *clk_parent[1];
424 u32 clk_reg;
425
426
427 clk_reg = CLK_ALWAYS_ON(host);
428 clk_reg |= CLK_DIV_MASK;
429 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
430 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
431 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
432 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
433
434
435 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
436 struct clk *clk;
437 char name[16];
438
439 snprintf(name, sizeof(name), "clkin%d", i);
440 clk = devm_clk_get(host->dev, name);
441 if (IS_ERR(clk))
442 return dev_err_probe(host->dev, PTR_ERR(clk),
443 "Missing clock %s\n", name);
444
445 mux_parent_names[i] = __clk_get_name(clk);
446 }
447
448
449 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
450 if (!mux)
451 return -ENOMEM;
452
453 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
454 init.name = clk_name;
455 init.ops = &clk_mux_ops;
456 init.flags = 0;
457 init.parent_names = mux_parent_names;
458 init.num_parents = MUX_CLK_NUM_PARENTS;
459
460 mux->reg = host->regs + SD_EMMC_CLOCK;
461 mux->shift = __ffs(CLK_SRC_MASK);
462 mux->mask = CLK_SRC_MASK >> mux->shift;
463 mux->hw.init = &init;
464
465 host->mux_clk = devm_clk_register(host->dev, &mux->hw);
466 if (WARN_ON(IS_ERR(host->mux_clk)))
467 return PTR_ERR(host->mux_clk);
468
469
470 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
471 if (!div)
472 return -ENOMEM;
473
474 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
475 init.name = clk_name;
476 init.ops = &clk_divider_ops;
477 init.flags = CLK_SET_RATE_PARENT;
478 clk_parent[0] = __clk_get_name(host->mux_clk);
479 init.parent_names = clk_parent;
480 init.num_parents = 1;
481
482 div->reg = host->regs + SD_EMMC_CLOCK;
483 div->shift = __ffs(CLK_DIV_MASK);
484 div->width = __builtin_popcountl(CLK_DIV_MASK);
485 div->hw.init = &init;
486 div->flags = CLK_DIVIDER_ONE_BASED;
487
488 host->mmc_clk = devm_clk_register(host->dev, &div->hw);
489 if (WARN_ON(IS_ERR(host->mmc_clk)))
490 return PTR_ERR(host->mmc_clk);
491
492
493 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
494 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
495 if (ret)
496 return ret;
497
498 return clk_prepare_enable(host->mmc_clk);
499}
500
501static void meson_mmc_disable_resampling(struct meson_host *host)
502{
503 unsigned int val = readl(host->regs + host->data->adjust);
504
505 val &= ~ADJUST_ADJ_EN;
506 writel(val, host->regs + host->data->adjust);
507}
508
509static void meson_mmc_reset_resampling(struct meson_host *host)
510{
511 unsigned int val;
512
513 meson_mmc_disable_resampling(host);
514
515 val = readl(host->regs + host->data->adjust);
516 val &= ~ADJUST_ADJ_DELAY_MASK;
517 writel(val, host->regs + host->data->adjust);
518}
519
520static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
521{
522 struct meson_host *host = mmc_priv(mmc);
523 unsigned int val, dly, max_dly, i;
524 int ret;
525
526
527 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
528 clk_get_rate(host->mmc_clk));
529
530 val = readl(host->regs + host->data->adjust);
531 val |= ADJUST_ADJ_EN;
532 writel(val, host->regs + host->data->adjust);
533
534 if (mmc_doing_retune(mmc))
535 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
536 else
537 dly = 0;
538
539 for (i = 0; i < max_dly; i++) {
540 val &= ~ADJUST_ADJ_DELAY_MASK;
541 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
542 writel(val, host->regs + host->data->adjust);
543
544 ret = mmc_send_tuning(mmc, opcode, NULL);
545 if (!ret) {
546 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
547 (dly + i) % max_dly);
548 return 0;
549 }
550 }
551
552 meson_mmc_reset_resampling(host);
553 return -EIO;
554}
555
556static int meson_mmc_prepare_ios_clock(struct meson_host *host,
557 struct mmc_ios *ios)
558{
559 bool ddr;
560
561 switch (ios->timing) {
562 case MMC_TIMING_MMC_DDR52:
563 case MMC_TIMING_UHS_DDR50:
564 ddr = true;
565 break;
566
567 default:
568 ddr = false;
569 break;
570 }
571
572 return meson_mmc_clk_set(host, ios->clock, ddr);
573}
574
575static void meson_mmc_check_resampling(struct meson_host *host,
576 struct mmc_ios *ios)
577{
578 switch (ios->timing) {
579 case MMC_TIMING_LEGACY:
580 case MMC_TIMING_MMC_HS:
581 case MMC_TIMING_SD_HS:
582 case MMC_TIMING_MMC_DDR52:
583 meson_mmc_disable_resampling(host);
584 break;
585 }
586}
587
588static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
589{
590 struct meson_host *host = mmc_priv(mmc);
591 u32 bus_width, val;
592 int err;
593
594
595
596
597
598 switch (ios->power_mode) {
599 case MMC_POWER_OFF:
600 if (!IS_ERR(mmc->supply.vmmc))
601 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
602
603 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
604 regulator_disable(mmc->supply.vqmmc);
605 host->vqmmc_enabled = false;
606 }
607
608 break;
609
610 case MMC_POWER_UP:
611 if (!IS_ERR(mmc->supply.vmmc))
612 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
613
614 break;
615
616 case MMC_POWER_ON:
617 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
618 int ret = regulator_enable(mmc->supply.vqmmc);
619
620 if (ret < 0)
621 dev_err(host->dev,
622 "failed to enable vqmmc regulator\n");
623 else
624 host->vqmmc_enabled = true;
625 }
626
627 break;
628 }
629
630
631 switch (ios->bus_width) {
632 case MMC_BUS_WIDTH_1:
633 bus_width = CFG_BUS_WIDTH_1;
634 break;
635 case MMC_BUS_WIDTH_4:
636 bus_width = CFG_BUS_WIDTH_4;
637 break;
638 case MMC_BUS_WIDTH_8:
639 bus_width = CFG_BUS_WIDTH_8;
640 break;
641 default:
642 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
643 ios->bus_width);
644 bus_width = CFG_BUS_WIDTH_4;
645 }
646
647 val = readl(host->regs + SD_EMMC_CFG);
648 val &= ~CFG_BUS_WIDTH_MASK;
649 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
650 writel(val, host->regs + SD_EMMC_CFG);
651
652 meson_mmc_check_resampling(host, ios);
653 err = meson_mmc_prepare_ios_clock(host, ios);
654 if (err)
655 dev_err(host->dev, "Failed to set clock: %d\n,", err);
656
657 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
658}
659
660static void meson_mmc_request_done(struct mmc_host *mmc,
661 struct mmc_request *mrq)
662{
663 struct meson_host *host = mmc_priv(mmc);
664
665 host->cmd = NULL;
666 mmc_request_done(host->mmc, mrq);
667}
668
669static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
670{
671 struct meson_host *host = mmc_priv(mmc);
672 u32 cfg, blksz_old;
673
674 cfg = readl(host->regs + SD_EMMC_CFG);
675 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
676
677 if (!is_power_of_2(blksz))
678 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
679
680 blksz = ilog2(blksz);
681
682
683 if (blksz == blksz_old)
684 return;
685
686 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
687 blksz_old, blksz);
688
689 cfg &= ~CFG_BLK_LEN_MASK;
690 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
691 writel(cfg, host->regs + SD_EMMC_CFG);
692}
693
694static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
695{
696 if (cmd->flags & MMC_RSP_PRESENT) {
697 if (cmd->flags & MMC_RSP_136)
698 *cmd_cfg |= CMD_CFG_RESP_128;
699 *cmd_cfg |= CMD_CFG_RESP_NUM;
700
701 if (!(cmd->flags & MMC_RSP_CRC))
702 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
703
704 if (cmd->flags & MMC_RSP_BUSY)
705 *cmd_cfg |= CMD_CFG_R1B;
706 } else {
707 *cmd_cfg |= CMD_CFG_NO_RESP;
708 }
709}
710
711static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
712{
713 struct meson_host *host = mmc_priv(mmc);
714 struct sd_emmc_desc *desc = host->descs;
715 struct mmc_data *data = host->cmd->data;
716 struct scatterlist *sg;
717 u32 start;
718 int i;
719
720 if (data->flags & MMC_DATA_WRITE)
721 cmd_cfg |= CMD_CFG_DATA_WR;
722
723 if (data->blocks > 1) {
724 cmd_cfg |= CMD_CFG_BLOCK_MODE;
725 meson_mmc_set_blksz(mmc, data->blksz);
726 }
727
728 for_each_sg(data->sg, sg, data->sg_count, i) {
729 unsigned int len = sg_dma_len(sg);
730
731 if (data->blocks > 1)
732 len /= data->blksz;
733
734 desc[i].cmd_cfg = cmd_cfg;
735 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
736 if (i > 0)
737 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
738 desc[i].cmd_arg = host->cmd->arg;
739 desc[i].cmd_resp = 0;
740 desc[i].cmd_data = sg_dma_address(sg);
741 }
742 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
743
744 dma_wmb();
745 start = host->descs_dma_addr | START_DESC_BUSY;
746 writel(start, host->regs + SD_EMMC_START);
747}
748
749
750static void meson_mmc_copy_buffer(struct meson_host *host, struct mmc_data *data,
751 size_t buflen, bool to_buffer)
752{
753 unsigned int sg_flags = SG_MITER_ATOMIC;
754 struct scatterlist *sgl = data->sg;
755 unsigned int nents = data->sg_len;
756 struct sg_mapping_iter miter;
757 unsigned int offset = 0;
758
759 if (to_buffer)
760 sg_flags |= SG_MITER_FROM_SG;
761 else
762 sg_flags |= SG_MITER_TO_SG;
763
764 sg_miter_start(&miter, sgl, nents, sg_flags);
765
766 while ((offset < buflen) && sg_miter_next(&miter)) {
767 unsigned int buf_offset = 0;
768 unsigned int len, left;
769 u32 *buf = miter.addr;
770
771 len = min(miter.length, buflen - offset);
772 left = len;
773
774 if (to_buffer) {
775 do {
776 writel(*buf++, host->bounce_iomem_buf + offset + buf_offset);
777
778 buf_offset += 4;
779 left -= 4;
780 } while (left);
781 } else {
782 do {
783 *buf++ = readl(host->bounce_iomem_buf + offset + buf_offset);
784
785 buf_offset += 4;
786 left -= 4;
787 } while (left);
788 }
789
790 offset += len;
791 }
792
793 sg_miter_stop(&miter);
794}
795
796static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
797{
798 struct meson_host *host = mmc_priv(mmc);
799 struct mmc_data *data = cmd->data;
800 u32 cmd_cfg = 0, cmd_data = 0;
801 unsigned int xfer_bytes = 0;
802
803
804 dma_rmb();
805
806 host->cmd = cmd;
807
808 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
809 cmd_cfg |= CMD_CFG_OWNER;
810 cmd_cfg |= CMD_CFG_ERROR;
811
812 meson_mmc_set_response_bits(cmd, &cmd_cfg);
813
814
815 if (data) {
816 data->bytes_xfered = 0;
817 cmd_cfg |= CMD_CFG_DATA_IO;
818 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
819 ilog2(meson_mmc_get_timeout_msecs(data)));
820
821 if (meson_mmc_desc_chain_mode(data)) {
822 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
823 return;
824 }
825
826 if (data->blocks > 1) {
827 cmd_cfg |= CMD_CFG_BLOCK_MODE;
828 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
829 data->blocks);
830 meson_mmc_set_blksz(mmc, data->blksz);
831 } else {
832 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
833 }
834
835 xfer_bytes = data->blksz * data->blocks;
836 if (data->flags & MMC_DATA_WRITE) {
837 cmd_cfg |= CMD_CFG_DATA_WR;
838 WARN_ON(xfer_bytes > host->bounce_buf_size);
839 if (host->dram_access_quirk)
840 meson_mmc_copy_buffer(host, data, xfer_bytes, true);
841 else
842 sg_copy_to_buffer(data->sg, data->sg_len,
843 host->bounce_buf, xfer_bytes);
844 dma_wmb();
845 }
846
847 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
848 } else {
849 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
850 ilog2(SD_EMMC_CMD_TIMEOUT));
851 }
852
853
854 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
855 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
856 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
857 writel(0, host->regs + SD_EMMC_CMD_RSP);
858 wmb();
859 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
860}
861
862static int meson_mmc_validate_dram_access(struct mmc_host *mmc, struct mmc_data *data)
863{
864 struct scatterlist *sg;
865 int i;
866
867
868 for_each_sg(data->sg, sg, data->sg_len, i) {
869 if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
870 !IS_ALIGNED(sg->length, sizeof(u32))) {
871 dev_err(mmc_dev(mmc), "unaligned sg offset %u len %u\n",
872 data->sg->offset, data->sg->length);
873 return -EINVAL;
874 }
875 }
876
877 return 0;
878}
879
880static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
881{
882 struct meson_host *host = mmc_priv(mmc);
883 bool needs_pre_post_req = mrq->data &&
884 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
885
886
887
888
889
890
891 if (host->dram_access_quirk && mrq->data) {
892 mrq->cmd->error = meson_mmc_validate_dram_access(mmc, mrq->data);
893 if (mrq->cmd->error) {
894 mmc_request_done(mmc, mrq);
895 return;
896 }
897 }
898
899 if (needs_pre_post_req) {
900 meson_mmc_get_transfer_mode(mmc, mrq);
901 if (!meson_mmc_desc_chain_mode(mrq->data))
902 needs_pre_post_req = false;
903 }
904
905 if (needs_pre_post_req)
906 meson_mmc_pre_req(mmc, mrq);
907
908
909 writel(0, host->regs + SD_EMMC_START);
910
911 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
912
913 if (needs_pre_post_req)
914 meson_mmc_post_req(mmc, mrq, 0);
915}
916
917static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
918{
919 struct meson_host *host = mmc_priv(mmc);
920
921 if (cmd->flags & MMC_RSP_136) {
922 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
923 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
924 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
925 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
926 } else if (cmd->flags & MMC_RSP_PRESENT) {
927 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
928 }
929}
930
931static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
932{
933 struct meson_host *host = dev_id;
934 struct mmc_command *cmd;
935 struct mmc_data *data;
936 u32 irq_en, status, raw_status;
937 irqreturn_t ret = IRQ_NONE;
938
939 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
940 raw_status = readl(host->regs + SD_EMMC_STATUS);
941 status = raw_status & irq_en;
942
943 if (!status) {
944 dev_dbg(host->dev,
945 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
946 irq_en, raw_status);
947 return IRQ_NONE;
948 }
949
950 if (WARN_ON(!host) || WARN_ON(!host->cmd))
951 return IRQ_NONE;
952
953
954 writel(status, host->regs + SD_EMMC_STATUS);
955
956 cmd = host->cmd;
957 data = cmd->data;
958 cmd->error = 0;
959 if (status & IRQ_CRC_ERR) {
960 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
961 cmd->error = -EILSEQ;
962 ret = IRQ_WAKE_THREAD;
963 goto out;
964 }
965
966 if (status & IRQ_TIMEOUTS) {
967 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
968 cmd->error = -ETIMEDOUT;
969 ret = IRQ_WAKE_THREAD;
970 goto out;
971 }
972
973 meson_mmc_read_resp(host->mmc, cmd);
974
975 if (status & IRQ_SDIO) {
976 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
977 ret = IRQ_HANDLED;
978 }
979
980 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
981 if (data && !cmd->error)
982 data->bytes_xfered = data->blksz * data->blocks;
983 if (meson_mmc_bounce_buf_read(data) ||
984 meson_mmc_get_next_command(cmd))
985 ret = IRQ_WAKE_THREAD;
986 else
987 ret = IRQ_HANDLED;
988 }
989
990out:
991 if (cmd->error) {
992
993 u32 start = readl(host->regs + SD_EMMC_START);
994
995 start &= ~START_DESC_BUSY;
996 writel(start, host->regs + SD_EMMC_START);
997 }
998
999 if (ret == IRQ_HANDLED)
1000 meson_mmc_request_done(host->mmc, cmd->mrq);
1001
1002 return ret;
1003}
1004
1005static int meson_mmc_wait_desc_stop(struct meson_host *host)
1006{
1007 u32 status;
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
1018 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
1019 100, 5000);
1020}
1021
1022static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1023{
1024 struct meson_host *host = dev_id;
1025 struct mmc_command *next_cmd, *cmd = host->cmd;
1026 struct mmc_data *data;
1027 unsigned int xfer_bytes;
1028
1029 if (WARN_ON(!cmd))
1030 return IRQ_NONE;
1031
1032 if (cmd->error) {
1033 meson_mmc_wait_desc_stop(host);
1034 meson_mmc_request_done(host->mmc, cmd->mrq);
1035
1036 return IRQ_HANDLED;
1037 }
1038
1039 data = cmd->data;
1040 if (meson_mmc_bounce_buf_read(data)) {
1041 xfer_bytes = data->blksz * data->blocks;
1042 WARN_ON(xfer_bytes > host->bounce_buf_size);
1043 if (host->dram_access_quirk)
1044 meson_mmc_copy_buffer(host, data, xfer_bytes, false);
1045 else
1046 sg_copy_from_buffer(data->sg, data->sg_len,
1047 host->bounce_buf, xfer_bytes);
1048 }
1049
1050 next_cmd = meson_mmc_get_next_command(cmd);
1051 if (next_cmd)
1052 meson_mmc_start_cmd(host->mmc, next_cmd);
1053 else
1054 meson_mmc_request_done(host->mmc, cmd->mrq);
1055
1056 return IRQ_HANDLED;
1057}
1058
1059
1060
1061
1062
1063static int meson_mmc_get_cd(struct mmc_host *mmc)
1064{
1065 int status = mmc_gpio_get_cd(mmc);
1066
1067 if (status == -ENOSYS)
1068 return 1;
1069
1070 return status;
1071}
1072
1073static void meson_mmc_cfg_init(struct meson_host *host)
1074{
1075 u32 cfg = 0;
1076
1077 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1078 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1079 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1080 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1081
1082
1083 cfg |= CFG_ERR_ABORT;
1084
1085 writel(cfg, host->regs + SD_EMMC_CFG);
1086}
1087
1088static int meson_mmc_card_busy(struct mmc_host *mmc)
1089{
1090 struct meson_host *host = mmc_priv(mmc);
1091 u32 regval;
1092
1093 regval = readl(host->regs + SD_EMMC_STATUS);
1094
1095
1096 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1097}
1098
1099static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1100{
1101 int ret;
1102
1103
1104 if (!IS_ERR(mmc->supply.vqmmc)) {
1105
1106
1107
1108
1109
1110
1111
1112 ret = mmc_regulator_set_vqmmc(mmc, ios);
1113 return ret < 0 ? ret : 0;
1114 }
1115
1116
1117 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1118 return 0;
1119
1120 return -EINVAL;
1121}
1122
1123static const struct mmc_host_ops meson_mmc_ops = {
1124 .request = meson_mmc_request,
1125 .set_ios = meson_mmc_set_ios,
1126 .get_cd = meson_mmc_get_cd,
1127 .pre_req = meson_mmc_pre_req,
1128 .post_req = meson_mmc_post_req,
1129 .execute_tuning = meson_mmc_resampling_tuning,
1130 .card_busy = meson_mmc_card_busy,
1131 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1132};
1133
1134static int meson_mmc_probe(struct platform_device *pdev)
1135{
1136 struct resource *res;
1137 struct meson_host *host;
1138 struct mmc_host *mmc;
1139 int ret;
1140
1141 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1142 if (!mmc)
1143 return -ENOMEM;
1144 host = mmc_priv(mmc);
1145 host->mmc = mmc;
1146 host->dev = &pdev->dev;
1147 dev_set_drvdata(&pdev->dev, host);
1148
1149
1150 host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1151 "amlogic,dram-access-quirk");
1152
1153
1154 host->vqmmc_enabled = false;
1155 ret = mmc_regulator_get_supply(mmc);
1156 if (ret)
1157 goto free_host;
1158
1159 ret = mmc_of_parse(mmc);
1160 if (ret) {
1161 if (ret != -EPROBE_DEFER)
1162 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1163 goto free_host;
1164 }
1165
1166 host->data = (struct meson_mmc_data *)
1167 of_device_get_match_data(&pdev->dev);
1168 if (!host->data) {
1169 ret = -EINVAL;
1170 goto free_host;
1171 }
1172
1173 ret = device_reset_optional(&pdev->dev);
1174 if (ret)
1175 return dev_err_probe(&pdev->dev, ret, "device reset failed\n");
1176
1177 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1178 host->regs = devm_ioremap_resource(&pdev->dev, res);
1179 if (IS_ERR(host->regs)) {
1180 ret = PTR_ERR(host->regs);
1181 goto free_host;
1182 }
1183
1184 host->irq = platform_get_irq(pdev, 0);
1185 if (host->irq <= 0) {
1186 ret = -EINVAL;
1187 goto free_host;
1188 }
1189
1190 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1191 if (IS_ERR(host->pinctrl)) {
1192 ret = PTR_ERR(host->pinctrl);
1193 goto free_host;
1194 }
1195
1196 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1197 "clk-gate");
1198 if (IS_ERR(host->pins_clk_gate)) {
1199 dev_warn(&pdev->dev,
1200 "can't get clk-gate pinctrl, using clk_stop bit\n");
1201 host->pins_clk_gate = NULL;
1202 }
1203
1204 host->core_clk = devm_clk_get(&pdev->dev, "core");
1205 if (IS_ERR(host->core_clk)) {
1206 ret = PTR_ERR(host->core_clk);
1207 goto free_host;
1208 }
1209
1210 ret = clk_prepare_enable(host->core_clk);
1211 if (ret)
1212 goto free_host;
1213
1214 ret = meson_mmc_clk_init(host);
1215 if (ret)
1216 goto err_core_clk;
1217
1218
1219 meson_mmc_cfg_init(host);
1220
1221
1222 writel(0, host->regs + SD_EMMC_START);
1223
1224
1225 writel(0, host->regs + SD_EMMC_IRQ_EN);
1226 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1227 host->regs + SD_EMMC_STATUS);
1228 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1229 host->regs + SD_EMMC_IRQ_EN);
1230
1231 ret = request_threaded_irq(host->irq, meson_mmc_irq,
1232 meson_mmc_irq_thread, IRQF_ONESHOT,
1233 dev_name(&pdev->dev), host);
1234 if (ret)
1235 goto err_init_clk;
1236
1237 mmc->caps |= MMC_CAP_CMD23;
1238 if (host->dram_access_quirk) {
1239
1240 mmc->max_segs = 1;
1241
1242 mmc->max_blk_count = SD_EMMC_SRAM_DATA_BUF_LEN /
1243 mmc->max_blk_size;
1244 } else {
1245 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1246 mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1247 sizeof(struct sd_emmc_desc);
1248 }
1249 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1250 mmc->max_seg_size = mmc->max_req_size;
1251
1252
1253
1254
1255
1256
1257 mmc->caps2 &= ~MMC_CAP2_HS400;
1258
1259 if (host->dram_access_quirk) {
1260
1261
1262
1263
1264
1265
1266 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1267 host->bounce_iomem_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1268 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1269 } else {
1270
1271 host->bounce_buf_size = mmc->max_req_size;
1272 host->bounce_buf =
1273 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1274 &host->bounce_dma_addr, GFP_KERNEL);
1275 if (host->bounce_buf == NULL) {
1276 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1277 ret = -ENOMEM;
1278 goto err_free_irq;
1279 }
1280 }
1281
1282 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1283 &host->descs_dma_addr, GFP_KERNEL);
1284 if (!host->descs) {
1285 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1286 ret = -ENOMEM;
1287 goto err_bounce_buf;
1288 }
1289
1290 mmc->ops = &meson_mmc_ops;
1291 mmc_add_host(mmc);
1292
1293 return 0;
1294
1295err_bounce_buf:
1296 if (!host->dram_access_quirk)
1297 dma_free_coherent(host->dev, host->bounce_buf_size,
1298 host->bounce_buf, host->bounce_dma_addr);
1299err_free_irq:
1300 free_irq(host->irq, host);
1301err_init_clk:
1302 clk_disable_unprepare(host->mmc_clk);
1303err_core_clk:
1304 clk_disable_unprepare(host->core_clk);
1305free_host:
1306 mmc_free_host(mmc);
1307 return ret;
1308}
1309
1310static int meson_mmc_remove(struct platform_device *pdev)
1311{
1312 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1313
1314 mmc_remove_host(host->mmc);
1315
1316
1317 writel(0, host->regs + SD_EMMC_IRQ_EN);
1318 free_irq(host->irq, host);
1319
1320 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1321 host->descs, host->descs_dma_addr);
1322
1323 if (!host->dram_access_quirk)
1324 dma_free_coherent(host->dev, host->bounce_buf_size,
1325 host->bounce_buf, host->bounce_dma_addr);
1326
1327 clk_disable_unprepare(host->mmc_clk);
1328 clk_disable_unprepare(host->core_clk);
1329
1330 mmc_free_host(host->mmc);
1331 return 0;
1332}
1333
1334static const struct meson_mmc_data meson_gx_data = {
1335 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1336 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1337 .always_on = CLK_V2_ALWAYS_ON,
1338 .adjust = SD_EMMC_ADJUST,
1339};
1340
1341static const struct meson_mmc_data meson_axg_data = {
1342 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1343 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1344 .always_on = CLK_V3_ALWAYS_ON,
1345 .adjust = SD_EMMC_V3_ADJUST,
1346};
1347
1348static const struct of_device_id meson_mmc_of_match[] = {
1349 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1350 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1351 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1352 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1353 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
1354 {}
1355};
1356MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1357
1358static struct platform_driver meson_mmc_driver = {
1359 .probe = meson_mmc_probe,
1360 .remove = meson_mmc_remove,
1361 .driver = {
1362 .name = DRIVER_NAME,
1363 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1364 .of_match_table = meson_mmc_of_match,
1365 },
1366};
1367
1368module_platform_driver(meson_mmc_driver);
1369
1370MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1371MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1372MODULE_LICENSE("GPL v2");
1373
